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2013-06-28drm/radeon/kms: add dpm support for rv7xx (v4)Alex Deucher18-13/+4876
This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add dpm support for rv6xx (v3)Alex Deucher16-3/+2477
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-06-27drm/radeon/kms: add dpm support for rs780/rs880Alex Deucher7-1/+1203
This adds dpm support for rs780/rs880 asics. This includes: - clockgating - dynamic engine clock scaling - dynamic voltage scaling set radeon.dpm=1 to enable it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add common r600 dpm functionsAlex Deucher5-1/+1116
These are shared by rs780/rs880, rv6xx, and newer chips. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: fix up dce6 display watermark calc for dpmAlex Deucher1-25/+71
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: fix up dce4/5 display watermark calc for dpmAlex Deucher1-23/+66
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: fix up 6xx/7xx display watermark calc for dpmAlex Deucher1-92/+132
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: fix up rs780/rs880 display watermark calc for dpmAlex Deucher1-124/+167
calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add common dpm infrastructureAlex Deucher3-9/+591
This adds the common dpm (dynamic power management) infrastructure: - dpm callbacks - dpm init/fini/suspend/resume - dpm power state selection No device specific code is enabled yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add new asic struct for rv6xx (v4)Alex Deucher1-5/+97
Has a different dpm controller than r600. v2: rebase on gpu reset changes v3: rebase on get_xclk changes v4: update rptr/wtpr callbacks Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add atom helper functions for dpm (v3)Alex Deucher3-7/+743
dpm needs access to atombios data and command tables for setup and calculation of a number of parameters. v2: endian fix v3: fix mc reg table bug Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: properly set up the RLC on ON/LN/TN (v3)Alex Deucher9-43/+2721
This is required for certain advanced functionality. v2: save/restore list takes dword offsets v3: rebase on gpu reset changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: move ucode defines to a separate headerAlex Deucher4-33/+56
Avoids confusion and duplication. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add support for thermal sensor on tnAlex Deucher4-0/+13
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: make get_temperature functions a callbackAlex Deucher4-27/+19
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/evergreen: add indirect register accessors for CG registersAlex Deucher2-0/+20
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add accessors for RCU indirect spaceAlex Deucher3-4/+22
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add current KB pci idsAlex Deucher1-0/+16
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add current Bonaire PCI idsAlex Deucher1-0/+8
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add cik tile mode array queryAlex Deucher4-8/+14
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add radeon_asic struct for CIK (v12)Alex Deucher2-0/+376
v2: fix up for latest reset changes v3: use CP for pt updates for now v4: update for 2 level PTs v5: update for ib_parse removal v6: vm_flush api change v7: rebase v8: fix gfx ring function pointers v9: fix vm_set_page function params v10: update for compute changes v11: cleanup for release v12: update rptr/wptr callbacks Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add support for golden register initAlex Deucher1-0/+438
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add support for compute interruptsAlex Deucher1-5/+116
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: fix up ring functions for compute ringsAlex Deucher1-6/+47
The compute rings use RELEASE_MEM rather then EOP packets for writing fences and there is no SYNC_PFP_ME packet on the compute rings. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: switch to type3 nop packet for compute rings (v2)Alex Deucher1-2/+4
Type 2 packets are deprecated on CIK MEC and we should use type 3 nop packets. Setting the count field to the max value (0x3fff) indicates that only one dword should be skipped like a type 2 packet. v2: add comment to code Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon/cik: Add support for compute queues (v4)Alex Deucher4-12/+595
On CIK, the compute rings work slightly differently than on previous asics, however the basic concepts are the same. The main differences: - New MEC engines for compute queues - Multiple queues per MEC: - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues - KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues - Queues can be allocated and scheduled by another queue - New doorbell aperture allows you to assign space in the aperture for the wptr which allows for userspace access to queues v2: add wptr shadow, fix eop setup v3: fix comment v4: switch to new callback method Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon: implement simple doorbell page allocatorAlex Deucher3-0/+153
The doorbell aperture is a PCI BAR whose pages can be mapped to compute resources for things like wptrs for userspace queues. This patch maps the BAR and sets up a simple allocator to allocate pages from the BAR. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: use callbacks for ring pointer handling (v3)Alex Deucher4-14/+182
Add callbacks to the radeon_asic struct to handle rptr/wptr fetchs and wptr updates. We currently use one version for all rings, but this allows us to override with a ring specific versions. Needed for compute rings on CIK. v2: udpate as per Christian's comments v3: fix some rebase cruft Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add srbm_select functionAlex Deucher1-2/+25
Allows us to select instanced registers based on: - ME (micro engine - Pipe - Queue - VMID Switch MC setup to use this new function. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add UVD support for CIK (v3)Christian König4-0/+149
v2: agd5f: fix clock dividers setup for bonaire v3: agd5f: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update radeon_atom_get_clock_dividers for CIKAlex Deucher2-1/+22
CIK uses a slightly different variant of the table structs and params. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update radeon_atom_get_clock_dividers() for SIAlex Deucher1-1/+5
SI uses v5 of the command table and uses a different table for memory PLLs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add pcie_port indirect register accessorsAlex Deucher4-1/+31
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add get_xclk() callback for CIKAlex Deucher3-0/+30
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add indirect register accessors for SMC registersAlex Deucher2-0/+21
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update CIK soft resetAlex Deucher2-146/+253
Update to the newer programming model. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add get_gpu_clock_counter() callback for cikAlex Deucher3-1/+29
Used for GPU clock counter snapshots. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: Update radeon_info_ioctl for CIK (v2)Alex Deucher1-7/+26
v2: rebase changes, fix a couple missed cases Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add SS override support for KB/KVAlex Deucher1-0/+17
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: use frac fb div on DCE8Alex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: Handle PPLL0 powerdown on DCE8Alex Deucher1-1/+1
Only Bonaire has PPLL0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add support pll selection for DCE8 (v4)Alex Deucher1-1/+47
v2: make PPLL0 is available for non-DP on CI v3: rebase changes, update documentation v4: fix kabini Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update DISPCLK programming for DCE8Alex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/atom: add support for new DVO tablesAlex Deucher1-1/+8
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/atom: add DCE8 encoder supportAlex Deucher2-5/+27
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dce8: crtc_set_base updatesAlex Deucher2-5/+108
Some new fields and DESKTOP_HEIGHT register moved. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dce8: properly handle interlaced timingAlex Deucher2-1/+10
The register bits changed on DCE8 compared to previous families. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: add hw cursor support (v2)Alex Deucher6-7/+94
CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit v2: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dce8: add support for display watermark setupAlex Deucher2-0/+548
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update power state parsing for CIAlex Deucher1-0/+10
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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