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2019-06-18arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhzBiju Das1-0/+6
Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on dhrystone. Based on work done by Gaku Inami <gaku.inami.xw@bp.renesas.com> for r8a7796 SoC. The average dhrystone result for 5 iterations is as below: r8a774a1 SoC (CA57x2 + CA53x4) CPU max-freq dhrystone --------------------------------- CA57 1500 MHz 11428571 lps/s CA53 1200 MHz 5000000 lps/s From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated as follows: r8a774a1 SoC CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024 CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) = 560 Since each CPUs have different max frequencies, the final CPU capacities of A53 scaled by the above difference is as below $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 448 448 448 448 Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: r8a774a1: Add CPU topology on r8a774a1 SoCBiju Das1-0/+26
This patch adds the "cpu-map" into r8a774a1 composed of multi-cluster. This definition is used to parse the cpu topology. Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> for r8a7796 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: hihope-common: Add LEDs supportFabrizio Castro1-0/+24
This patch adds LEDs support to the HiHope RZ/G2[MN] Main Board common device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: hihope-common: Enable USB3.0Biju Das1-0/+29
This patch enables USB3.0 host/peripheral device node for the HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-17arm64: dts: renesas: hihope-common: Add USB 2.0 supportFabrizio Castro1-0/+76
Add USB 2.0 support to the HiHope RZ/G2M. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-17arm64: dts: renesas: r8a774a1: Fix USB 2.0 clocksFabrizio Castro1-8/+8
Similarly to what done for the r8a7796 with commit 737e05bf034e ("arm64: dts: renesas: revise properties for R-Car Gen3 SoCs' usb 2.0"), this patch lists the clock for the USB High-Speed Module (HS-USB) with the USB2.0 Host (EHCI/OHCI) IP DT node, and it lists the clock for the USB2.0 Host IP with the HS-USB module DT node. Fixes: 4c2c2fb99876 ("arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI) device nodes") Fixes: ed898d4fc19d ("arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes") Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: r8a774a1: Add TMU device nodesFabrizio Castro1-0/+65
This patch adds TMU[01234] device tree nodes to the r8a774a1 SoC specific DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: r8a774a1: Add CMT device nodesFabrizio Castro1-0/+70
This patch adds the CMT[0123] device tree nodes to the r8a774a1 SoC specific DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: hihope-common: Add uSD and eMMCFabrizio Castro1-0/+77
This patch adds uSD and eMMC support to the HiHope RZ/G2M board. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: r8a77990: Fix register range of display nodeTakeshi Kihara1-1/+1
Since the R8A77990 SoC uses DU{0,1}, the range from the base address to the 0x4000 address is used. This patch fixed it. Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: cat874: Enable usb role switch supportBiju Das1-0/+32
This patch enables TI HD3SS3220 device and support usb role switch for the CAT 874 platform. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: cat874: Enable USB3.0 host/peripheral device nodeBiju Das1-0/+17
This patch enables USB3.0 host/peripheral device node for the cat874 board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: r8a7799[05]: Point LVDS0 to its companion LVDS1Laurent Pinchart2-0/+4
Add the new renesas,companion property to the LVDS0 node to point to the companion LVDS encoder LVDS1. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: hihope-common: Add RWDT supportBiju Das1-0/+5
Enable RWDT and use 60 seconds as default timeout. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: hihope-rzg2-ex: Enable PCIe supportBiju Das1-0/+8
This patch enables PCIEC[01] PCI express controller on the sub board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: hihope-common: Declare pcie bus clockBiju Das1-0/+4
Declare pcie bus clock, since it is generated on the HiHope RZ/G2M main board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-12arm64: dts: renesas: r8a774a1: Add PCIe device nodesBiju Das1-0/+54
This patch adds PCIe{0,1} device nodes for R8A774A1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: Add HiHope RZ/G2M sub board supportBiju Das4-0/+73
The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board. This patch also adds ethernet support along with a dtsi common to both HiHope RZ/G2M and RZ/G2N sub boards. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: hihope-common: Add pincontrol support to scif2/scif clockBiju Das1-0/+18
This patch adds pincontrol support to scif2/scif clock. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: Add HiHope RZ/G2M main board supportBiju Das3-0/+60
Basic support for the HiHope RZ/G2M main board: - Memory, - Main crystal, - Serial console This patch also includes a dtsi common to both HiHope RZ/G2M and RZ/G2N main boards. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a774a1: Add operating pointsFabrizio Castro1-0/+48
The RZ/G2M (a.k.a. r8a774a1) comes with two clusters of processors, similarly to the r8a7796. The first cluster is made of A57s, the second cluster is made of A53s. The operating points for the cluster with the A57s are: Frequency | Voltage -----------|--------- 500 MHz | 0.82V 1.0 GHz | 0.82V 1.5 GHz | 0.82V The operating points for the cluster with the A53s are: Frequency | Voltage -----------|--------- 800 MHz | 0.82V 1.0 GHz | 0.82V 1.2 GHz | 0.82V This patch adds the definitions for the operating points to the SoC specific DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a77990: Add dynamic power coefficientSimon Horman1-0/+1
Describe the dynamic power coefficient of A53 CPUs. Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a77990: Create thermal zone to support IPADien Pham1-3/+16
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. In R-Car Gen3, IPA is supported for only one channel Reason: Currently, IPA controls base on only CPU temperature. And only one thermal channel is assembled closest CPU cores is selected as target of IPA. If other channels are used, IPA controlling is not properly. A single cooling device is described for all A53 CPUs as this reflects that physically there is only one cooling device present. This patch improves on an earlier version by: * Omitting cooling-max-level and cooling-min-level properties which are no longer present in mainline as of v4.17 * Removing an unused trip-point0 node sub-property from the trips property. * Defers adding dynamic-power-coefficient properties to a separate patch as these are properties of the CPU. The long signed-off by chain below reflects many revisions, mainly internal, that this patch has been through. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a77965: Add dynamic power coefficientSimon Horman1-0/+1
Describe the dynamic power coefficient of A57 and A53 CPUs. Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a77965: Create thermal zone to support IPADien Pham1-0/+19
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. In R-Car Gen3, IPA is supported for only one channel (on H3/M3/M3N SoCs, it is channel THS3). Reason: Currently, IPA controls base on only CPU temperature. And only one thermal channel is assembled closest CPU cores is selected as target of IPA. If other channels are used, IPA controlling is not properly. The A57 cooling device supports 5 cooling states which can be categorised as follows: 0 & 1) boost (clocking up) 2) default 3 & 4) cooling (clocking down) Currently the thermal framework assumes that the default is the minimum, or in other words there is no provision for handling boost states. So this patch only describes the upper 3 states, default and cooling. A single cooling device is described for all A57 CPUs and a separate cooling device is described for all A53 CPUs. This reflects that physically there is only one cooling device present for each type of CPU. This patch improves on an earlier version by: * Omitting cooling-max-level and cooling-min-level properties which are no longer present in mainline as of v4.17 * Removing an unused trip-point0 node sub-property from the trips property. * Using cooling-device indexes such that maximum refers to maximum cooling rather than the inverse. * Defers adding dynamic-power-coefficient properties to a separate patch as these are properties of the CPU. The long signed-off by chain below reflects many revisions, mainly internal, that this patch has been through. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: An Huynh <an.huynh.uj@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a7796: Add dynamic power coefficientSimon Horman1-0/+2
Describe the dynamic power coefficient of A57 and A53 CPUs. Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a7796: Create thermal zone to support IPADien Pham1-29/+15
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. In R-Car Gen3, IPA is supported for only one channel (on H3/M3/M3N SoCs, it is channel THS3). Reason: Currently, IPA controls base on only CPU temperature. And only one thermal channel is assembled closest CPU cores is selected as target of IPA. If other channels are used, IPA controlling is not properly. The A57 cooling device supports 5 cooling states which can be categorised as follows: 0 & 1) boost (clocking up) 2) default 3 & 4) cooling (clocking down) Currently the thermal framework assumes that the default is the minimum, or in other words there is no provision for handling boost states. So this patch only describes the upper 3 states, default and cooling. A single cooling device is described for all A57 CPUs and a separate cooling device is described for all A53 CPUs. This reflects that physically there is only one cooling device present for each type of CPU. This patch improves on an earlier version by: * Omitting cooling-max-level and cooling-min-level properties which are no longer present in mainline as of v4.17 * Removing an unused trip-point0 node sub-property from the trips property. * Using cooling-device indexes such that maximum refers to maximum cooling rather than the inverse. * Defers adding dynamic-power-coefficient properties to a separate patch as these are properties of the CPU. The long signed-off by chain below reflects many revisions, mainly internal, that this patch has been through. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Hien Dang <hien.dang.eb@rvc.renesas.com> Signed-off-by: An Huynh <an.huynh.uj@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a7795: Add dynamic power coefficientSimon Horman1-0/+2
Describe the dynamic power coefficient of A57 and A53 CPUs. Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a7795: Create thermal zone to support IPADien Pham1-37/+15
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. In R-Car Gen3, IPA is supported for only one channel (on H3/M3/M3N SoCs, it is channel THS3). Reason: Currently, IPA controls base on only CPU temperature. And only one thermal channel is assembled closest CPU cores is selected as target of IPA. If other channels are used, IPA controlling is not properly. The A5 cooling device supports 5 cooling states which can be categorised as follows: 0 & 1) boost (clocking up) 2) default 3 & 4) cooling (clocking down) Currently the thermal framework assumes that the default is the minimum, or in other words there is no provision for handling boost states. So this patch only describes the upper 3 states, default and cooling. A single cooling device is described for all A57 CPUs and a separate cooling device is described for all A53 CPUs. This reflects that physically there is only one cooling device present for each type of CPU. This patch improves on an earlier version by: * Omitting cooling-max-level and cooling-min-level properties which are no longer present in mainline as of v4.17 * Removing an unused trip-point0 node sub-property from the trips property. * Using cooling-device indexes such that maximum refers to maximum cooling rather than the inverse. * Defers adding dynamic-power-coefficient properties to a separate patch as these are properties of the CPU. The long signed-off by chain below reflects many revisions, mainly internal, that this patch has been through. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Hien Dang <hien.dang.eb@rvc.renesas.com> Signed-off-by: An Huynh <an.huynh.uj@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: Revise usb2_phy nodes and phys propertiesYoshihiro Shimoda7-47/+47
Since the commit 233da2c9ec22 ("dt-bindings: phy: rcar-gen3-phy-usb2: Revise #phy-cells property") revised the #phy-cells, this patch follows the updated document for R-Car Gen3 and RZ/A2 SoCs. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: ebisu: Remove renesas, no-ether-link propertyTakeshi Kihara1-1/+0
It is incorrect to specify the no-ether-link property for the AVB device on the Ebisu board. This is because the property should only be used when a board does not provide a proper AVB_LINK signal. However, the Ebisu board does provide this signal. As per 87c059e9c39d ("arm64: dts: renesas: salvator-x: Remove renesas, no-ether-link property") this fixes a bug: Steps to reproduce: - start AVB TX stream (Using aplay via MSE), - disconnect+reconnect the eth cable, - after a reconnection the eth connection goes iteratively up/down without user interaction, - this may heal after some seconds or even stay for minutes. As the documentation specifies, the "renesas,no-ether-link" option should be used when a board does not provide a proper AVB_LINK signal. There is no need for this option enabled on RCAR H3/M3 Salvator-X/XS and ULCB starter kits since the AVB_LINK is correctly handled by HW. Choosing to keep or remove the "renesas,no-ether-link" option will have impact on the code flow in the following ways: - keeping this option enabled may lead to unexpected behavior since the RX & TX are enabled/disabled directly from adjust_link function without any HW interrogation, - removing this option, the RX & TX will only be enabled/disabled after HW interrogation. The HW check is made through the LMON pin in PSR register which specifies AVB_LINK signal value (0 - at low level; 1 - at high level). In conclusion, the present change is also a safety improvement because it removes the "renesas,no-ether-link" option leading to a proper way of detecting the link state based on HW interrogation and not on software heuristic. Fixes: 8441ef643d7d ("arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: updated changelog] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: r8a774c0: Clean up CPU compatiblesRobin Murphy1-2/+2
Apparently this DTS crossed over with commit 31af04cd60d3 ("arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string") and missed out on the cleanup, so put it right. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-06arm64: dts: renesas: Use ip=on for bootargsMagnus Damm6-6/+6
Convert bootargs from ip=dhcp to ip=on Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-28arm64: dts: renesas: cat874: Add BT supportBiju Das1-0/+19
This patch enables BT support for the CAT874 board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-28arm64: dts: renesas: cat874: Add WLAN supportBiju Das1-0/+38
This patch enables WLAN support for the CAT874 board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a7795: Add TPU supportCao Van Dong1-0/+11
Add tpu device node to dtsi for TPU support on r8a7795 SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a77965: Add TPU supportCao Van Dong1-0/+11
Add tpu device node to dtsi for TPU support on r8a77965 SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a7796: Add TPU supportCao Van Dong1-0/+11
Add tpu device node to dtsi for TPU support on r8a7796 SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: ulcb-kf: Add support for TI WL1837Spyridon Papageorgiou1-0/+49
This patch adds description of TI WL1837 and links interfaces to communicate with the IC, namely the SDIO interface to WLAN. Signed-off-by: Spyridon Papageorgiou <spapageorgiou@de.adit-jv.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: draak: Remove unnecessary index from vin4 portSimon Horman1-6/+1
The ports node of vin4 only has one sub-node and thus does not need #address-cells/#size-cells and the sub-node does not need an exit. This addresses the following warning: # make dtbs W=1 ... arch/arm64/boot/dts/renesas/r8a77995-draak.dts:492.8-503.4: Warning (graph_child_address): /soc/video@e6ef4000/ports: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary Fixes: 6a0942c20f5c ("arm64: dts: renesas: draak: Describe CVBS input") Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-05-20arm64: dts: renesas: cat874: Add HDMI audioFabrizio Castro1-0/+56
The CAT874 board pushes sound via I2S over SSI0 into the TDA19988BET chip. This commit wires things up so that we can get sound out of the HDMI interface. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: cat874: Add HDMI video supportFabrizio Castro1-0/+82
The CAT874 board comes with a HDMI connector, managed by a TDA19988BET chip, connected to the RZ/G2E SoC via DPAD. This patch adds the necessary support to the board DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a774a1: Connect Ethernet-AVB to IPMMU-DS0Biju Das1-0/+1
Add IPMMU-DS0 to the Ethernet-AVB device node. Based on work by Magnus Damm for the r8a7795. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a774a1: Tie Audio-DMAC to IPMMU-MPBiju Das1-0/+16
Hook up r8a774a1 Audio-DMAC nodes to the IPMMU-MP. Based on work for the r8a7795 by Magnus Damm. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a774a1: Tie SYS-DMAC to IPMMU-DS0/1Biju Das1-0/+24
Hook up r8a774a1 DMAC nodes to the IPMMUs. In particular SYS-DMAC0 gets tied to IPMMU-DS0, and SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1. Based on work for the r8a7796 by Magnus Damm. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a774a1: Add FDP1 instanceBiju Das1-0/+10
The r8a774a1 has a single FDP1 instance similar to r8a7796. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a774a1: Add DU device to DTBiju Das1-0/+63
Add the DU device to r8a774a1.dtsi in a disabled state. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20arm64: dts: renesas: r8a774a1: Add VSP instancesBiju Das1-0/+55
The r8a774a1 soc has 5 VSP instances similar to r8a7796. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-20Linux 5.2-rc1Linus Torvalds1-2/+2
2019-05-20Merge tag 'upstream-5.2-rc2' of ↵Linus Torvalds3-4/+8
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBIFS fixes from Richard Weinberger: - build errors wrt xattrs - mismerge which lead to a wrong Kconfig ifdef - missing endianness conversion * tag 'upstream-5.2-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubifs: Convert xattr inum to host order ubifs: Use correct config name for encryption ubifs: Fix build error without CONFIG_UBIFS_FS_XATTR
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 05:15:30 +0300