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2022-07-17arm64: dts: qcom: reorder USB interruptsJohan Hovold2-16/+24
Three SoCs did not follow the interrupt order specified by the USB controller binding. While keeping the non-SuperSpeed interrupts together seems natural, reorder the interrupts to match the binding. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> [bjorn: Omitted sdx65 part from this patch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org
2022-07-17arm64: dts: qcom: sc7280: reorder USB interruptsJohan Hovold1-7/+8
Only one of the USB controllers supports SuperSpeed and have an SS PHY wakeup interrupt. Reorder the interrupts so that they match the updated binding which specifically has the optional interrupt last. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220715070248.19078-4-johan+linaro@kernel.org
2022-07-17arm64: dts: qcom: sc8280xp: fix USB interruptsJohan Hovold1-5/+9
The two single-port SC8280XP USB controllers do not have an hs_phy_irq interrupt. Instead they have a pwr_event interrupt which is distinct from the former and not yet supported by the driver. Fix the USB node interrupt names so that they match the devicetree binding. Also fix the pwr_event interrupt of the second controller which should be 811 as noticed by Andrew Halaney. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220715070248.19078-3-johan+linaro@kernel.org
2022-07-17arm64: dts: qcom: sc8280xp: fix USB clock order and namingJohan Hovold1-8/+8
Fix the USB controller clock order and naming so that they match the devicetree binding. Note that the driver currently simply enables all clocks in the order that they are specified in the devicetree. Reordering the clocks as per the binding means that the only explicit ordering constraint found in the vendor driver, that cfg_noc should be enabled before the core_clk, is now honoured. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220715070248.19078-2-johan+linaro@kernel.org
2022-07-16arm64: dts: qcom: sc8280xp: fix usb_1 ssphy irqJohan Hovold1-1/+1
Fix the usb_1 SS PHY interrupt, which was mistakingly replaced with one of the usb_2 PHY interrupts. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220715165344.28822-1-johan+linaro@kernel.org
2022-07-16arm64: dts: qcom: sc8280xp: Fix PMU interruptManivannan Sadhasivam1-1/+1
PPI interrupt should be 7 for the PMU. Cc: Johan Hovold <johan+linaro@kernel.org> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Reported-by: Steve Capper <Steve.Capper@arm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220713143429.22624-1-manivannan.sadhasivam@linaro.org
2022-07-16arm64: dts: qcom: sc8280xp: fix the smmu interrupt valuesParikshit Pareek1-1/+1
There has been wrong values introduced for context interrupt for smu node apps_smmu. Fix those ones with due correction. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Parikshit Pareek <quic_ppareek@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220711174133.28882-1-quic_ppareek@quicinc.com
2022-07-16arm64: dts: qcom: qcs404: Fix incorrect USB2 PHYs assignmentSumit Garg1-2/+2
Currently the DT for QCS404 SoC has setup for 2 USB2 PHYs with one each assigned to USB3 controller and USB2 controller. This assignment is incorrect which only works by luck: as when each USB HCI comes up it configures the *other* controllers PHY which is enough to make them happy. If, for any reason, we were to disable one of the controllers then both would stop working. This was a difficult inconsistency to be caught which was found while trying to enable USB support in u-boot. So with all the required drivers ported to u-boot, I couldn't get the same USB storage device enumerated in u-boot which was being enumerated fine by the kernel. The root cause of the problem came out to be that I wasn't enabling USB2 PHY: "usb2_phy_prim" in u-boot. Then I realised that via simply disabling the same USB2 PHY currently assigned to USB2 host controller in the kernel disabled enumeration for USB3 host controller as well. So fix this inconsistency by correctly assigning USB2 PHYs. Fixes: 9375e7d719b3 ("arm64: dts: qcom: qcs404: Add USB devices and PHYs") Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220711083038.1518529-1-sumit.garg@linaro.org
2022-07-16arm64: dts: qcom: sc7280: drop unused clocks from eDP nodeDmitry Baryshkov1-6/+2
The eDP node includes two clocks which are used by the eDP PHY rather than eDP controller itself. Drop these clocks to remove extra difference between eDP and DP controllers. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220710084133.30976-7-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sc7280: drop address/size-cells from eDP nodeDmitry Baryshkov1-3/+0
Drop #address/#size-cells from eDP device node. For eDP the panels are not described directly under the controller node. They are either present under aux-bus child node, or they are declared separately (e.g. in a /soc node). Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220710084133.30976-6-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sc7280: drop #clock-cells from displayport-controllerDmitry Baryshkov1-2/+0
Drop #clock-cells from DP device node. It is a leftover from the times before splitting the deviice into controller and PHY devices. Now the clocks are provided by the PHY, while the controller doesn't provide any clocks. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220710084133.30976-5-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sc7280: split register block for DP controllerDmitry Baryshkov1-1/+5
Follow the schema for the DP controller and declare 5 register regions instead of using a single region for all the registers. Note, this extends the dts by adding p1 region to the DP node (to be used for DP MST). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220710084133.30976-4-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sc7180: drop #clock-cells from displayport-controllerDmitry Baryshkov1-1/+0
Drop #clock-cells from DP device node. It is a leftover from the times before splitting the device into controller and PHY devices. Now the clocks are provided by the PHY, while the controller doesn't provide any clocks. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220710084133.30976-3-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sc7180: split register block for DP controllerDmitry Baryshkov1-1/+5
Follow the schema for the DP controller and declare 5 register regions instead of using a single region for all the registers. Note, this extends the dts by adding p1 region to the DP node (to be used for DP MST). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220710084133.30976-2-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sc7280: Move wcd specific pin conf to common fileSrinivasa Rao Mandadapu2-61/+64
Move wcd specific pin conf to common file to support various herbronie variant boards and to avoid duplicate nodes in dts files. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1657197381-1271-1-git-send-email-quic_srivasam@quicinc.com
2022-07-16arm64: dts: qcom: msm8998: Make regulator voltages multiple of step-sizeMarijn Suijten1-4/+6
These voltages are not a multiple of the given step-size 8000 (with base voltage 1664000) in pm8998_pldo, resulting in PLDO regulators l18 and l22 failing to validate and in turn not probing the rpm-pm8998-regulator driver: l18: unsupportable voltage constraints 2856000-2848000uV qcom_rpm_smd_regulator rpm-glink:rpm-requests:pm8998-regulators: l18: devm_regulator_register() failed, ret=-22 Round the voltages down for the sake of erring on the safe side, leaving a comment in place to document this discrepancy wrt downstream sources. Fixes: 390883af89d2 ("arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform") Reported-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220507153627.1478268-1-marijn.suijten@somainline.org
2022-07-16arm64: dts: qcom: sm6350: Replace literal rpmhpd indices with constantsMarijn Suijten1-2/+2
It seems the SM6350_CX definition was temporarily replaced with its literal value 0 in 1797e1c9a95c ("arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes") to prevent a dependency on the qcom-rpmpd.h header patch being available prior to this DT patch being applied, similar to c23f1b77358c ("arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX"). However, unlike the revert of that in the sm6125 tree the next merge window around in a90b8adfa2dd ("Revert "arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX""), this has not yet happened for sm6350: replace them back now that the definitions are definitely available. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220507224645.2238421-1-marijn.suijten@somainline.org
2022-07-16arm64: dts: qcom: ipq8074: add interrupt-parent to DTSIRobert Marko3-3/+1
Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board DTS file. Remove interrupt-parent from existing board DTS files. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708133846.599735-2-robimarko@gmail.com
2022-07-16arm64: dts: qcom: ipq8074: add #size/address-cells to DTSIRobert Marko3-5/+3
Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating the same properties in board DTS files. Remove the mentioned properties from current board DTS files. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com
2022-07-16arm64: dts: qcom: sm8250: rename DPU device nodeDmitry Baryshkov1-1/+1
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708091656.2769390-3-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sc7180: rename DPU device nodeDmitry Baryshkov1-1/+1
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708091656.2769390-2-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: sdm845: rename DPU device nodeDmitry Baryshkov1-1/+1
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708091656.2769390-1-dmitry.baryshkov@linaro.org
2022-07-16arm64: dts: qcom: ipq8074: add APCS nodeRobert Marko1-0/+8
APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the required DT node for it as it will later be used as the CPU clocksource. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Sorted node based on address] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220707173733.404947-4-robimarko@gmail.com
2022-07-13arm64: dts: qcom: sc8280xp: Add lost ranges for timerBjorn Andersson1-0/+1
The timer node needs ranges specified to map the 1-cell children to the 2-cell address range used in /soc. This addition never made it into the patch that was posted and merged, so add it now. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220707160858.3178771-1-bjorn.andersson@linaro.org
2022-07-09arm64: dts: qcom: sc8280xp: fix DP PHY node unit addressesJohan Hovold1-1/+1
Fix up the DP PHY node which had the wrong unit address. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708072556.4687-1-johan+linaro@kernel.org
2022-07-09arm64: dts: qcom: sc8280xp: fix usb_0 HS PHY ref clockJohan Hovold1-1/+1
Fix the usb_0 HS PHY reference clock which was mistakingly replaced with the first usb_2 PHY clock. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708072358.4583-1-johan+linaro@kernel.org
2022-07-09arm64: dts: qcom: sc7280: fix PCIe clock referenceJohan Hovold1-1/+1
The recent commit that dropped the PCIe PHY clock index failed to update the PCIe node reference. Fixes: 531c738fb360 ("arm64: dts: qcom: sc7280: drop PCIe PHY clock index") Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220707064222.15717-1-johan+linaro@kernel.org
2022-07-09docs: arm: index.rst: add google/chromebook-boot-flowMauro Carvalho Chehab1-0/+2
This document was added without placing it at arm book. Fixes: 59228d3b9060 ("dt-bindings: Document how Chromebooks with depthcharge boot") Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/0ae8251f97c642cfd618f2e32eb1e66339e5dfde.1656759989.git.mchehab@kernel.org
2022-07-07arm64: dts: qcom: msm8996: clean up PCIe PHY nodeJohan Hovold1-10/+17
Clean up the PCIe PHY node by renaming the wrapper node and grouping the child node properties. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-15-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYsJohan Hovold1-13/+13
Clean up the PCIe PHY nodes by using a non-empty ranges property. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-14-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: sm8450: drop UFS PHY clock-cellsJohan Hovold1-1/+0
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-12-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: sm8250: drop UFS PHY clock-cellsJohan Hovold1-1/+0
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-11-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cellsJohan Hovold1-2/+0
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-10-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: sm8450: drop USB PHY clock indexJohan Hovold1-1/+1
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-9-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: sm8350: drop USB PHY clock indexJohan Hovold1-2/+2
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-8-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: msm8998: drop USB PHY clock indexJohan Hovold1-1/+1
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-7-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: ipq8074: drop USB PHY clock indexJohan Hovold1-2/+2
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: ipq6018: drop USB PHY clock indexJohan Hovold1-1/+1
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-4-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cellsJohan Hovold1-0/+6
Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-3-johan+linaro@kernel.org
2022-07-07arm64: dts: qcom: sc7280: drop PCIe PHY clock indexJohan Hovold1-2/+2
The QMP PCIe PHY provides a single clock so drop the redundant clock index. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support") Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220705114032.22787-2-johan+linaro@kernel.org
2022-07-07Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"Douglas Anderson6-8/+8
This reverts commit afcbe252e9c19161e4d4c95f33faaf592f1de086. The commit in question caused my sc7280-herobrine-herobrine-r1 board not to boot anymore. This shouldn't be too surprising since the driver is relying on the name "cqhci". The issue seems to be that someone decided to change the names of things when the binding moved from .txt to .yaml. We should go back to the names that the bindings have historically specified. For some history, see commit d3392339cae9 ("mmc: cqhci: Update cqhci memory ioresource name") and commit d79100c91ae5 ("dt-bindings: mmc: sdhci-msm: Add CQE reg map"). Fixes: afcbe252e9c1 ("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid
2022-07-07arm64: dts: qcom: sc7180-idp: add vdds supply to the DSI PHYDmitry Baryshkov1-0/+1
Add the (required) vdss-supply property to the DSI PHY node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-3-dmitry.baryshkov@linaro.org
2022-07-07arm64: dts: qcom: sc7280: use constants for gpucc clocks and power-domainsDmitry Baryshkov1-16/+16
To ease merging of bindings and dts files, the constants were replaced with numeric values. Change them back to defined constants. While we are at it, fix the indentation of these clocks properties to follow established guidelines. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-2-dmitry.baryshkov@linaro.org
2022-07-07arm64: dts: qcom: msm8996: add missing DSI clock assignmentsDmitry Baryshkov1-0/+4
Add missing DSI clock assignments to properly use DSI PHY clocks as DSI byte and pixel clock parents. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-1-dmitry.baryshkov@linaro.org
2022-07-07arm64: dts: qcom: ipq8074: add reset to SDHCIRobert Marko1-0/+1
Add reset to SDHCI controller so it can be reset to avoid timeout issues after software reset due to bootloader set configuration. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com
2022-07-07arm64: dts: qcom: sdm845: Add CPU BWMONKrzysztof Kozlowski1-0/+37
Add device node for CPU-memory BWMON device (bandwidth monitoring) on SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. Co-developed-by: Thara Gopinath <thara.gopinath@gmail.com> Signed-off-by: Thara Gopinath <thara.gopinath@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704121730.127925-5-krzysztof.kozlowski@linaro.org
2022-07-07arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC nodeRobert Marko1-8/+8
The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Robert Marko <robimarko@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> [bjorn: Moved node after "soc" for alphabetical ordering] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
2022-07-07arm64: dta: qcom: sc7180: delete vdda-1p2 and vdda-0p9 from mdss_dpKuogee Hsieh1-2/+0
Both vdda-1p2-supply and vdda-0p9-supply regulators are controlled by dp combo phy. Therefore remove them from dp controller. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1656690436-15221-1-git-send-email-quic_khsieh@quicinc.com
2022-07-07arm64: dts: qcom: sdm845: Switch PSCI cpu idle states from PC to OSIAbel Vesa2-54/+213
Switch from the flat PC idle states of sdm845 to OSI hierarchical idle states. The exceptions are the cheza plaftorms, which need to remain with PC idle states. So in order allow all the other platforms to switch, while cheza platforms to remain the same, replace the PC idle states with the OSI ones in the main SDM845 dtsi, and then override the inherited OSI states with PC ones, delete inherited psci cpus nodes, domain idle states and power domain properties. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220630101403.1888541-1-abel.vesa@linaro.org
2022-07-07arm64: dts: qcom: extend scm compatible stringsDavid Heidelberg4-4/+4
First device specific compatible, then general one. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626183247.142776-2-david@ixit.cz
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