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2024-02-29dt-bindings: pinctrl: at91: add sam9x7Varshini Rajendran1-0/+2
Add device tree binding for SAM9X7 pin controller. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240223172531.671993-1-varshini.rajendran@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-29pinctrl: ocelot: remove redundant assignment to variable retColin Ian King1-1/+0
The variable ret is being assigned a value that is never read, it is being re-assigned a value in every case statement in the following switch statement. The assignment is redundant and can be removed. Cleans up clang scan build warning: drivers/pinctrl/pinctrl-ocelot.c:1404:3: warning: Value stored to 'ret' is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20240223162850.3914349-1-colin.i.king@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-29dt-bindings: pinctrl: mobileye,eyeq5-pinctrl: add bindingsThéo Lebrun1-0/+242
Add dt-schema type bindings for the Mobileye EyeQ5 pin controller. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20240227-mbly-clk-v8-1-c57fbda7664a@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-26Merge tag 'renesas-pinctrl-for-v6.9-tag2' of ↵Linus Walleij7-32/+4440
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.9 (take two) - Add support for the R-Car V4M (R8A779H0) SoC, - Add support for suspend/resume on the RZ/G2L family, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-22pinctrl: qcom: sm8650-lpass-lpi: correct Kconfig nameKrzysztof Kozlowski1-1/+1
Use proper model name in SM8650 LPASS pin controller Kconfig entry. Cc: <stable@vger.kernel.org> Fixes: c4e47673853f ("pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240216102435.89867-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-21pinctrl: renesas: Allow the compiler to optimize away sh_pfc_pmGeert Uytterhoeven1-1/+3
The conversion to DEFINE_NOIRQ_DEV_PM_OPS() lost the ability of the compiler to optimize away the struct dev_pm_ops object when it is not needed. Fix this by replacing the use of pm_sleep_ptr() by a custom wrapper. Fixes: 727eb02eb753375e ("pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/6238a78e32fa21f0c795406b6cba7bce7af92577.1708513940.git.geert+renesas@glider.be
2024-02-21pinctrl: renesas: rzg2l: Add suspend/resume supportClaudiu Beznea1-4/+404
pinctrl-rzg2l driver is used on RZ/G3S which support deep sleep states where power to most of the SoC components is turned off. For this add suspend/resume support. This involves saving and restoring configured registers along with disabling clock in case there is no pin configured as wakeup sources. To save/restore registers 2 caches were allocated: one for GPIO pins and one for dedicated pins. On suspend path the pin controller registers are saved and if none of the pins are configured as wakeup sources the pinctrl clock is disabled. Otherwise it remains on. On resume path the configuration is done as follows: 1/ setup PFCs by writing to registers on pin based accesses 2/ setup GPIOs by writing to registers on port based accesses and following configuration steps specified in hardware manual 3/ setup dedicated pins by writing to registers on port based accesses 4/ setup interrupts. Because interrupt signals are routed to IA55 interrupt controller and IA55 interrupt controller resumes before pin controller, patch restores also the configured interrupts just after pin settings are restored to avoid invalid interrupts while resuming. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240215124112.2259103-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-21pinctrl: renesas: rzg2l: Select GPIOLIB_IRQCHIP and IRQ_DOMAIN_HIERARCHYClaudiu Beznea1-0/+2
The pinctrl-rzg2l driver accesses gpio_chip.irq, which is available only if CONFIG_GPIOLIB_IRQCHIP=y, and uses APIs that are defined only if CONFIG_IRQ_DOMAIN_HIERARCHY=y (irq_chip_*_parent() APIs). On ARCH_RZG2L, CONFIG_IRQ_DOMAIN_HIERARCHY is selected anyway, e.g. by CONFIG_ARM_GIC_V3, but CONFIG_GPIOLIB_IRQCHIP is not (it is on R-Car). Make this explicit at the driver level for a clearer view of the dependencies. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240215124112.2259103-2-claudiu.beznea.uj@bp.renesas.com [geert: select GPIOLIB_IRQCHIP, too] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-21pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*(Biju Das1-4/+2
Currently on irq_disable(), we are disabling gpio interrupt enable(ISEL). That means the pin is just gpio input and not gpio input interrupt any more. So, move configuring ISEL in rzg2l_gpio_child_to_parent_hwirq()/ rzg2l_gpio_irq_domain_free() so that the pin will be gpioint always even during irq_disable(). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240206135318.165426-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-21pinctrl: renesas: rzg2l: Simplify rzg2l_gpio_irq_{en,dis}able()Biju Das1-24/+16
Simplify rzg2l_gpio_irq_{en,dis}able() by adding a helper function rzg2l_gpio_irq_endisable(). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240206135115.151218-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-21pinctrl: renesas: rzg2l: Configure interrupt input modeBiju Das1-2/+35
Configure GPIO interrupt as input mode. Also if the bootloader sets gpio interrupt pin as function, override it as gpio. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240206135115.151218-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-20pinctrl: renesas: r8a779h0: Add Audio pins, groups, functionsCong Dang1-0/+52
Add pins, groups and functions for Audio on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e7d5024c23929d2eccb02bb5daf44c914db07d80.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add PCIe pins, groups, functionsCong Dang1-0/+18
Add pins, groups and functions for the PCIe Controller on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d32909f5197fa2df0ca6bd6e5fda7cae8863101e.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add CANFD pins, groups, functionsCong Dang1-0/+77
Add pins, groups and functions for the CAN-FD interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fd380a402ec4c6238aa8cafc2e602d9e0f1c8cf2.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add PWM/TPU pins, groups, functionsCong Dang1-0/+236
Add pins, groups and functions for the PWM and 16-Bit Timer Pulse Units (TPU) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ddbd37b1815169a8b18c5026bc4fd957f0b25dde.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add MSIOF pins, groups, functionsCong Dang1-0/+367
Add pins, groups and functions for the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cbfc61f0c02e9dbeec0ea689e10bdd5ebf5bf1e3.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add I2C pins, groups, functionsCong Dang1-0/+62
Add pins, groups and functions for the I2C Bus Interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/23fc01c6e97e544abd23168439f5d45d3ac8fa5b.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add HSCIF pins, groups, functionsCong Dang1-0/+192
Add pins, groups and functions for the High Speed Serial Communication Interfaces with FIFO (HSCIF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/27577af0042928e4b673a2774c68a14c4ea7c157.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add SCIF_CLK pins, groups, functionsCong Dang1-0/+29
Add pins, groups and functions for the baud rate generation clock pins (SCIF_CLK) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ee056d78d3a339bdbcca2cc5281f1fe01bbc3953.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add SCIF pins, groups, functionsCong Dang1-0/+192
Add pins, groups and functions for the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/4ad8127a54fb36044ae85db07ff30be05fa5d0f0.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add QSPI pins, groups, functionsCong Dang1-0/+58
Add pins, groups and functions for the QSPI functionality proviced by the SPI Multi I/O Bus Controller (RPC-IF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ebe123bca4888382bc76ccf1a3a9e85ced31f3f3.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add SD/MMC pins, groups, functionsCong Dang1-0/+63
Add pins, groups and functions for the SD Card/MMC Interface on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c4c06f5be8ffeb32c48993c138f89c8f463751f4.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: r8a779h0: Add Ethernet AVB pins, groups, functionsCong Dang1-1/+301
Add pins, groups and functions for Ethernet AVB on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f79d8f75582f44a7441faed550fb37e44a917558.1706264667.git.geert+renesas@glider.be
2024-02-20pinctrl: renesas: Initial R8A779H0 (R-Car V4M) PFC supportCong Dang5-0/+2334
Add initial pin control support for the R-Car V4M (R8A779H0) SoC, including bias, drive strength and voltage control. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> [geert: Fixes and cleanups] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5f59263e75be713dc954007cfeb2c99274c9d761.1706264667.git.geert+renesas@glider.be
2024-02-20dt-bindings: pinctrl: renesas,pfc: Document R-Car V4M supportGeert Uytterhoeven1-0/+1
Document support for the Pin Function Controller (PFC) in the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/56685dc04af3cee7cb3751e855ed5b3679b14122.1706264667.git.geert+renesas@glider.be
2024-02-13Merge tag 'renesas-pinctrl-for-v6.9-tag1' of ↵Linus Walleij4-53/+276
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.9 - Add pin groups for SCIF_CLK2 on R-Car V4H, - Add support for port pins P19 to P28 on RZ/Five, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-09pinctrl: mcp23s08: Check only GPIOs which have interrupts enabledArturas Moskvinas1-4/+11
GPINTEN register contains information about GPIOs with enabled interrupts no need to check other GPIOs for changes. Signed-off-by: Arturas Moskvinas <arturas.moskvinas@gmail.com> Link: https://lore.kernel.org/r/20240201141406.32484-2-arturas.moskvinas@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-09dt-bindings: pinctrl: cy8c95x0: Update gpio-reserved-rangesNaresh Solanki1-2/+22
Update maxItems to 60 for gpio-reserved-ranges to allow multiple gpio reserved ranges. Add input-enable property to allow configuring a pin as input. Also update example. Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240206112501.715042-1-naresh.solanki@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-09dt-bindings: pinctrl: nvidia,tegra234-pinmux: Restructure common schemaRob Herring3-53/+45
The structure of the NVIDIA Tegra234 common pinmux schema doesn't work for restricting properties because a child node schema can't be extended with additional properties from another schema defining the same child node. The 2 child node schemas are evaluated independently as the schemas are not recursively combined in any way. As the common schema is almost all the child node schema anyways, just remove the parent node from the common schema. Then add 'reg' and adjust the $ref's in the users of the common schema. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240202223454.1667383-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-07pinctrl: mediatek: Drop bogus slew rate register range for MT8192Chen-Yu Tsai1-1/+0
The MT8192 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: d32f38f2a8fc ("pinctrl: mediatek: Add pinctrl driver for mt8192") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240131071910.3950450-2-wenst@chromium.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-07pinctrl: mediatek: Drop bogus slew rate register range for MT8186Chen-Yu Tsai1-1/+0
The MT8186 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: 8b483bda1e46 ("pinctrl: add pinctrl driver on mt8186") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240131071910.3950450-1-wenst@chromium.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-07pinctrl: nuvoton: Constify wpcm450_groupsAndy Shevchenko1-1/+1
There is no modifications are assumed for wpcm450_groups. Constify it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211154239.4190429-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-31pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28Lad Prabhakar2-9/+208
Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and are not identical for the complete port so introduce struct rzg2l_variable_pin_cfg to handle such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config is then assigned in rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK(). Update the gpio-ranges property in the RZ/Five SoC DTSI, as it must match the driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135556.63466-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macroLad Prabhakar1-27/+29
Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. As the pincount can be calculated based on pinmap drop this from RZG2L_GPIO_PORT_PACK() macro. Previously we had a max of 7 pins on each port but on RZ/Five Port-20 has 8 pins, so move the single pin configuration to BIT(63). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135556.63466-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31pinctrl: renesas: rzg2l: Improve code for readabilityLad Prabhakar1-19/+25
As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and has experienced substantial growth, enhance code readability by incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135556.63466-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31pinctrl: renesas: checker: Limit cfg reg enum checks to provided IDsGeert Uytterhoeven1-1/+3
If the number of provided enum IDs in a variable width config register description does not match the expected number, the checker uses the expected number for validating the individual enum IDs. However, this may cause out-of-bounds accesses on the array holding the enum IDs, leading to bogus enum_id conflict warnings. Worse, if the bug is an incorrect bit field description (e.g. accidentally using "12" instead of "-12" for a reserved field), thousands of warnings may be printed, overflowing the kernel log buffer. Fix this by limiting the enum ID check to the number of provided enum IDs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c7385f44f2faebb8856bcbb4e908d846fc1531fb.1705930809.git.geert+renesas@glider.be
2024-01-31pinctrl: renesas: r8a779g0: Add missing SCIF_CLK2 pin group/functionGeert Uytterhoeven1-0/+14
R-Car V4H actually has two SCIF_CLK pins. The second pin provides the SCIF_CLK signal for HSCIF2 and SCIF4. Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6352ec9b63fdd38c2c70d8d203e46f21fbfeccdc.1705589612.git.geert+renesas@glider.be
2024-01-31pinctrl: renesas: rzg2l: Fix locking in rzg2l_dt_subnode_to_map()Claudiu Beznea1-10/+10
Commit d3aaa7203a17 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") introduced the possibility to parse pin configuration for pinmux groups. It did that by calling rzg2l_map_add_config() at the end of rzg2l_dt_subnode_to_map() and jumping to the remove_group label in case rzg2l_map_add_config() failed. But if that happens, the mutex will already be unlocked, thus this it will lead to double mutex unlock operation. To fix this move the rzg2l_map_add_config() call just after all the name argument is ready and before the mutex is locked. There is no harm in doing this, as this only parses the data from device tree that will be further processed by pinctrl core code. Fixes: d3aaa7203a17 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/f8c3a3a0-7c48-4e40-8af0-ed4e9d9b049f@moroto.mountain Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240115153453.99226-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31dt-bindings: pinctr: pinctrl-zynq: Fix compatible stringMichal Simek1-3/+3
Compatible string doesn't really match with compatible string listed in the driver itself. While binding was converted from txt to yaml xlnx,zynq-pinctrl was listed as compatible string but example was using xlnx,pinctrl-zynq and also this string is used in all DTSes. xlnx,zynq-pinctrl is used only in dt binding and not present in any DT which is stable for quite a long time that's why use old compatible string and update binding document instead of starting to use unused compatible string. Fixes: 153df45acda0 ("dt-bindings: pinctrl: pinctrl-zynq: Convert to yaml") Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/c1307a4dd5e30290acacc786cb2170deb9eaa539.1706087258.git.michal.simek@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-31pinctrl: cs42l43: Use str_high_low()Charles Keepax1-1/+1
Use str_high_low() rather than open coding. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240129153138.3221604-3-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-31pinctrl: cs42l43: Remove some needless inlinesCharles Keepax1-6/+6
Remove some pointless inline declarations, no reason not to let the compiler decide. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240129153138.3221604-2-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-31pinctrl: cs42l43: Tidy up header includesCharles Keepax1-2/+2
Fixup a couple of incorrect header includes. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240129153138.3221604-1-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-31dt-bindings: pinctrl: nuvoton,npcm845: Drop redundant type for "slew-rate"Rob Herring1-1/+0
pincfg-node.yaml already defines the type for "slew-rate", so drop the type from the nuvoton,npcm845-pinctrl binding. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240124190106.1540585-2-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-31dt-bindings: pinctrl: Unify "input-debounce" schemaRob Herring4-4/+5
nuvoton,npcm845-pinctrl defines the common "input-debounce" property as an array rather than an scalar. Update the common definition to expand it to an uint32-array, and update all the users of the property with array constraints. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240124190106.1540585-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-28dt-bindings: pinctrl: amlogic: narrow regex for unit address to hex numbersKrzysztof Kozlowski5-5/+5
Regular expression used to match the unit address part should not allow non-hex numbers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240123083511.21063-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-28pinctrl: pinctrl-zynqmp: Use devm_kcalloc() instead of devm_kzalloc()Erick Archer1-4/+4
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, use the purpose specific devm_kcalloc() function instead of the argument size * count in the devm_kzalloc() function. Link: https://www.kernel.org/doc/html/next/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/162 Signed-off-by: Erick Archer <erick.archer@gmx.com> Acked-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20240119181909.7079-1-erick.archer@gmx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-28pinctrl: mediatek: mt7981: add additional emmc groupsJean Thomas1-1/+16
Add new emmc groups in the pinctrl driver for the MediaTek MT7981 SoC: * emmc reset, with pin 15. * emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25. * emmc 8-bit bus-width, with pins 16 to 25. The existing emmc_45 group is kept for legacy reasons, even if this is the union of emmc_reset and emmc_8 groups. Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr> Reviewed-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20240117145547.3354242-1-jean.thomas@wifirst.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-28pinctrl: mediatek: mt7981: add additional uart groupJean Thomas1-1/+6
Add uart1_3 (pins 26, 27) group to the pinctrl driver for the MediaTek MT7981 SoC. Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr> Reviewed-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20240117124234.3137050-1-jean.thomas@wifirst.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-28pinctrl: mt7986: excise kernel-doc warningsRandy Dunlap1-1/+1
Fix kernel-doc warnings for enum (anonymous): the enum values are not documented, so don't indicate that the comment contains kernel-doc notation. pinctrl-mt7986.c:68: warning: Enum value 'GPIO_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_RT_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_RB_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_LT_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_LB_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_TR_BASE' not described in enum '(anonymous)' pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_TL_BASE' not described in enum '(anonymous)' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312110210.x3vxq42A-lkp@intel.com/ Cc: Linus Walleij <linus.walleij@linaro.org> Cc: <linux-gpio@vger.kernel.org> Cc: Sean Wang <sean.wang@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: <linux-mediatek@lists.infradead.org> Cc: <linux-arm-kernel@lists.infradead.org> Link: https://lore.kernel.org/r/20240111045126.13768-1-rdunlap@infradead.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-28pinctrl: st: Return pinctrl_gpio_direction_output to transfer the errorChen Ni1-2/+1
Return pinctrl_gpio_direction_output() in order to transfer the error if it fails. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240103085058.3771653-1-nichen@iscas.ac.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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