summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-10-06net: phy: at803x: add QCA9561 supportDavid Bauer1-2/+21
Add support for the embedded fast-ethernet PHY found on the QCA9561 WiSoC platform. It supports the usual Atheros PHY featureset including the cable tester. Tested on a Xiaomi MiRouter 4Q (QCA9561) Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David Bauer <mail@david-bauer.net> Link: https://lore.kernel.org/r/20211005225401.10653-1-mail@david-bauer.net Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-10-05Merge tag 'for-net-next-2021-10-01' of ↵Jakub Kicinski35-1084/+2789
git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next Luiz Augusto von Dentz says: ==================== bluetooth-next pull request for net-next: - Add support for MediaTek MT7922 and MT7921 - Enable support for AOSP extention in Qualcomm WCN399x and Realtek 8822C/8852A. - Add initial support for link quality and audio/codec offload. - Rework of sockets sendmsg to avoid locking issues. - Add vhci suspend/resume emulation. ==================== Link: https://lore.kernel.org/r/20211001230850.3635543-1-luiz.dentz@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-10-05net: usb: use eth_hw_addr_set() for dev->addr_len casesJakub Kicinski5-5/+5
Convert usb drivers from memcpy(... dev->addr_len) to eth_hw_addr_set(): @@ expression dev, np; @@ - memcpy(dev->dev_addr, np, dev->addr_len) + eth_hw_addr_set(dev, np) Manually checked these are either usbnet or pure etherdevs. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05ethernet: use eth_hw_addr_set() for dev->addr_len casesJakub Kicinski76-93/+90
Convert all Ethernet drivers from memcpy(... dev->addr_len) to eth_hw_addr_set(): @@ expression dev, np; @@ - memcpy(dev->dev_addr, np, dev->addr_len) + eth_hw_addr_set(dev, np) In theory addr_len may not be ETH_ALEN, but we don't expect non-Ethernet devices to live under this directory, and only the following cases of setting addr_len exist: - cxgb4 for mgmt device, and the drivers which set it to ETH_ALEN: s2io, mlx4, vxge. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05Merge branch 'mlx4-const-dev_addr'David S. Miller8-48/+26
Jakub Kicinski says: ==================== mlx4: prep for constant dev->dev_addr This patch converts mlx4 for dev->dev_addr being const. It converts to use of common helpers but also removes some seemingly unnecessary idiosyncrasies. Please review. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05mlx4: constify args for const dev_addrJakub Kicinski3-5/+7
netdev->dev_addr will become const soon. Make sure all functions which pass it around mark appropriate args as const. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05mlx4: remove custom dev_addr clearingJakub Kicinski1-8/+6
mlx4_en_u64_to_mac() takes the dev->dev_addr pointer and writes to it byte by byte. It also clears the two bytes _after_ ETH_ALEN which seems unnecessary. dev->addr_len is set to ETH_ALEN just before the call. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05mlx4: replace mlx4_u64_to_mac() with u64_to_ether_addr()Jakub Kicinski2-11/+1
mlx4_u64_to_mac() predates the common helper but doesn't make the argument constant. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05mlx4: replace mlx4_mac_to_u64() with ether_addr_to_u64()Jakub Kicinski6-24/+12
mlx4_mac_to_u64() predates and opencodes ether_addr_to_u64(). It doesn't make the argument constant so it'll be problematic when dev->dev_addr becomes a const. Convert to the generic helper. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05netlink: remove netlink_broadcast_filteredFlorian Westphal2-25/+2
No users in tree since commit a3498436b3a0 ("netns: restrict uevents"), so remove this functionality. Cc: Christian Brauner <christian.brauner@ubuntu.com> Signed-off-by: Florian Westphal <fw@strlen.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05Merge tag 'mlx5-updates-2021-10-04' of ↵David S. Miller21-149/+597
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-updates-2021-10-04 Misc updates for mlx5 driver 1) Add TX max rate support for MQPRIO channel mode 2) Trivial TC action and modify header refactoring 3) TC support for accept action in fdb offloads 4) Allow single IRQ for PCI functions 5) Bridge offload: Pop PVID VLAN header on egress miss Vlad Buslov says: ================= With current architecture of mlx5 bridge offload it is possible for a packet to match in ingress table by source MAC (resulting VLAN header push in case of port with configured PVID) and then miss in egress table when destination MAC is not in FDB. Due to the lack of hardware learning in NICs, this, in turn, results packet going to software data path with PVID VLAN already added by hardware. This doesn't break software bridge since it accepts either untagged packets or packets with any provisioned VLAN on ports with PVID, but can break ingress TC, if affected part of Ethernet header is matched by classifier. Improve compatibility with software TC by restoring the packet header on egress miss. Effectively, this change implements atomicity of mlx5 bridge offload implementation - packet is either modified and redirected to destination port or appears unmodified in software. ================= ================= Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05net: bgmac: support MDIO described in DTRafał Miłecki1-1/+5
Check ethernet controller DT node for "mdio" subnode and use it with of_mdiobus_register() when present. That allows specifying MDIO and its PHY devices in a standard DT based way. This is required for BCM53573 SoC support. That family is sometimes called Northstar (by marketing?) but is quite different from it. It uses different CPU(s) and many different hw blocks. One of shared blocks in BCM53573 is Ethernet controller. Switch however is not SRAB accessible (as it Northstar) but is MDIO attached. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05net: bgmac: improve handling PHYRafał Miłecki1-12/+21
1. Use info from DT if available It allows describing for example a fixed link. It's more accurate than just guessing there may be one (depending on a chipset). 2. Verify PHY ID before trying to connect PHY PHY addr 0x1e (30) is special in Broadcom routers and means a switch connected as MDIO devices instead of a real PHY. Don't try connecting to it. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05ethernet: ehea: add missing castJakub Kicinski1-1/+1
We need to cast the pointer, unlike memcpy() eth_hw_addr_set() does not take void *. The driver already casts &port->mac_addr to u8 * in other places. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: a96d317fb1a3 ("ethernet: use eth_hw_addr_set()") Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05sparc: Fix typo.David S. Miller1-1/+1
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-05Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.gitKalle Valo41-2668/+4897
ath.git patches for v5.16. Major changes: ath9k * load calibration data and pci init values via nvmem subsystem ath11k * include channel rx and tx time in survey dump statistics * support for setting fixed Wi-Fi 6 rates from user space * support for 80P80 and 160 MHz bandwidths * spectral scan support for QCN9074 * support for calibration data files per radio * support for calibration data via eeprom * support for rx decapsulation offload (data frames in 802.3 format) * support channel 2 in 6 GHz band ath10k * include frame time stamp in beacon and probe response frames wcn36xx * enable Idle Mode Power Save (IMPS) to reduce power consumption during idle
2021-10-05rtl8xxxu: Use lower tx rates for the ack packetChris Chiu2-1/+7
According to the Realtek propritary driver and the rtw88 driver, the tx rates of the ack (includes block ack) are initialized with lower tx rates (no HT rates) which is set by the RRSR register value. In real cases, ack rate higher than current tx rate could lead to difficulty for the receiving end to receive management/control frames. The retransmission rate would be higher then expected when the driver is acting as receiver and the RSSI is not good. Cross out higer rates for ack packet before implementing dynamic rrsr configuration like the commit 4830872685f8 ("rtw88: add dynamic rrsr configuration"). Signed-off-by: Chris Chiu <chris.chiu@canonical.com> Acked-by: Jes Sorensen <Jes.Sorensen@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20211001040044.1028708-1-chris.chiu@canonical.com
2021-10-05bcma: drop unneeded initialization valueSohaib Mohamed1-1/+1
Do not initialise statics to 0 ERROR found by checkpatch.pl Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210930194920.15847-1-sohaib.amhmd@gmail.com
2021-10-05brcmfmac: Add DMI nvram filename quirk for Cyberbook T116 tabletHans de Goede1-0/+10
The Cyberbook T116 tablet contains quite generic names in the sys_vendor and product_name DMI strings, without this patch brcmfmac will try to load: "brcmfmac43455-sdio.Default string-Default string.txt" as nvram file which is way too generic. The nvram file shipped on the factory Android image contains the exact same settings as those used on the AcePC T8 mini PC, so point the new DMI nvram filename quirk to the acepc-t8 nvram file. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210928160633.96928-1-hdegoede@redhat.com
2021-10-05rtw88: refine fw_crash debugfs to show non-zero while triggeringZong-Zhe Yang3-1/+6
The usage of fw_crash debugfs is to write 1 to it to trigger fw crash simulation and to read from it to check the state. When zero is read, it is supposed to mean fw crash/restart process is done. Then, some test plans can be designed for crash/restart. e.g. step 1. trigger fw crash simulation step 2. poll the state until zero is read step 3. check connection by ping test However, in certain connection cases, triggering fw crash simulation will take a while. If the state is queried too early before restart begins processing, it may mistakenly think restart process has been done. If some tests are started at this time, something unexpected might happen due to the follow-up restart process. To avoid that, let fw_crash also show non-zero when a simulation is still triggering. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20211001082301.4805-1-pkshih@realtek.com
2021-10-05rtw88: fix RX clock gate setting while fifo dumpZong-Zhe Yang2-4/+4
When fw fifo dumps, RX clock gating should be disabled to avoid something unexpected. However, the register operation ran into a mistake. So, we fix it. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210927111830.5354-1-pkshih@realtek.com
2021-10-05net/mlx5: Enable single IRQ for PCI FunctionShay Drory2-8/+19
Prior to this patch the driver requires two IRQs to function properly, one required IRQ for control and at least one required IRQ for IO. This requirement can be relaxed to one as the driver now allows sharing of IRQs, so control and IO EQs can share the same irq. This is needed for high scale amount of VFs. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5: Shift control IRQ to the last indexShay Drory5-11/+13
Control IRQ is the first IRQ vector. This complicates handling of completion irqs as we need to offset them by one. in the next patch, there are scenarios where completion and control EQs will share the same irq. for example: functions with single IRQ. To ease such scenarios, we shift control IRQ to the end of the irq array. Signed-off-by: Shay Drory <shayd@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5: Bridge, pop VLAN on egress table missVlad Buslov1-2/+126
Create lowest priority flow group in egress table with single rule that matches on special reg_c1 value that is set on ingress VLAN push with single action that pops VLAN. The flow destination is skip table that is used to skip any further processing of packet in FDB bridge priority. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5: Bridge, mark reg_c1 when pushing VLANVlad Buslov3-1/+49
On ingress VLAN push also assign value 0x7FE to reg_c1 tunnel id+opts bits (tunnel id 0, which is not a valid tunnel id, and option 0x7FE which was reserved by one of previous patches in the series). In following patch the reg value is matched on egress miss to restore the packet to its original state by removing the VLAN before passing it to the software data path. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5: Bridge, extract VLAN pop code to dedicated functionsVlad Buslov1-12/+22
Following patches in series need to pop VLAN when packet misses on egress. To reuse existing bridge VLAN pop handling code, extract it to dedicated helpers mlx5_esw_bridge_pkt_reformat_vlan_pop_supported() and mlx5_esw_bridge_pkt_reformat_vlan_pop_create(). Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5: Bridge, refactor eswitch instance usageVlad Buslov1-11/+14
Several functions in bridge.c excessively obtain pointer to parent eswitch instance by dereferencing br_offloads->esw on every usage and following patches in this series add even more usages of eswitch. Introduce local variable 'esw' and use it instead. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Support accept actionVlad Buslov4-4/+17
Support TC generic 'accept' action in mlx5 by introducing MLX5_ESW_ATTR_FLAG_ACCEPT attribute flag. Flag has similar semantics to existing MLX5_ESW_ATTR_FLAG_SLOW_PATH flag, however, dedicated flag is required because existing 'slow path' flag can be flipped by tunneling subsystem when neighbor changes state. Introduce new helper function mlx5_esw_attr_flags_skip() to check whether attribute flags for 'slow path' or 'accept' action are set and use it in eswitch code instead of direct bit manipulation. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Specify out ifindex when looking up encap routeChris Mi3-0/+18
There is a use case that the local and remote VTEPs are in the same host. Currently, the out ifindex is not specified when looking up the encap route for offloads. So in this case, a local route is returned and the route dev is lo. Actual tunnel interface can be created with a parameter "dev" [1], which specifies the physical device to use for tunnel endpoint communication. Pass this parameter to driver when looking up encap route for offloads. So that a unicast route will be returned. [1] ip link add name vxlan1 type vxlan id 100 dev enp4s0f0 remote 1.1.1.1 dstport 4789 Signed-off-by: Chris Mi <cmi@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Reserve a value from TC tunnel options mappingVlad Buslov1-2/+4
Reserve one more value from TC tunnel options range to be used by bridge offload in following patches. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Move parse fdb check into actions_match_supported_fdb()Roi Dayan1-9/+11
The parse fdb/nic actions funcs parse the actions and then call actions_match_supported() for final check. Move related check in parse_tc_fdb_actions() into actions_match_supported_fdb() for more organized code. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Split actions_match_supported() into a sub functionRoi Dayan1-26/+39
There will probably be more checks, some for nic flows, some for fdb flows and some are shared checks. Split it for fdb and nic to avoid the function getting too big. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Move mod hdr allocation to a single placeRoi Dayan1-36/+51
Move mod hdr allocation chunk from parse_tc_fdb_actions() and parse_tc_nic_actions() to a shared function. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Reviewed-by: Oz Shlomo <ozsh@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: TC, Refactor sample offload error flowRoi Dayan1-16/+5
Refactor sample unoffload to be symmetric to sample offload. Use the existing del_post_rule() to release the post rule. Also mlx5e_tc_sample_unoffload() should not return post_rule which is NULL when post actions are supported. Sample offload works with this NULL because many places of the code use IS_ERR() instead of IS_ERR_OR_NULL() to check rule is valid and when rule is detected as sample offload the code is not using the rule. Let's be persistent and avoid returning NULL anyway and return the pre rule, like in CT case, which is not NULL. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Chris Mi <cmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Add TX max rate support for MQPRIO channel modeTariq Toukan4-6/+203
Add driver max_rate support for the MQPRIO bw_rlimit shaper in channel mode. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-05net/mlx5e: Specify SQ stats struct for mlx5e_open_txqsq()Tariq Toukan3-8/+9
Let the caller of mlx5e_open_txqsq() directly pass the SQ stats structure pointer. This replaces logic involving the qos_queue_group_id parameter, and helps generalizing its role in the next patch. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04Merge branch 'phy-10g-mode-helper'David S. Miller5-18/+15
Russell King says: ==================== Add phylink helper for 10G modes During the last cycle, there was discussion about adding a helper to set the 10G link modes for phylink, which resulted in these two patches introduce such a helper. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04net: ethernet: use phylink_set_10g_modes()Russell King (Oracle)3-18/+3
Update three drivers to use the new phylink_set_10g_modes() helper: Cadence macb, Freescale DPAA2 and Marvell PP2. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04net: phylink: add phylink_set_10g_modes() helperRussell King (Oracle)2-0/+12
Add a helper for setting 10Gigabit modes, so we have one central place that sets all appropriate 10G modes for a driver. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04net: ipv6: fix use after free of struct seg6_pernet_dataMichelleJin1-1/+1
sdata->tun_src should be freed before sdata is freed because sdata->tun_src is allocated after sdata allocation. So, kfree(sdata) and kfree(rcu_dereference_raw(sdata->tun_src)) are changed code order. Fixes: f04ed7d277e8 ("net: ipv6: check return value of rhashtable_init") Signed-off-by: MichelleJin <shjy180909@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04Merge branch 'qed-new-fw'David S. Miller66-10293/+13425
Prabhakar Kushwaha says: ==================== qed: new firmware version 8.59.1.0 support This series integrate new firmware version 8.59.1.0, along with updated HSI (hardware software interface) to use the FW, into the family of qed drivers (fastlinq devices). This FW does not reside in the NVRAM. It needs to be programmed to device during driver load as the part of initialization sequence. Similar to previous FW support series, this FW is tightly linked to software and pf function driver. This means FW release is not backward compatible, and driver should always run with the FW it was designed against. FW binary blob is already submitted & accepted in linux-firmware repo. Patches in the series include: patch 1 - qed: Fix kernel-doc warnings patch 2 - qed: Remove e4_ and _e4 from FW HSI patch 3 - qed: split huge qed_hsi.h header file patch 4-8 - HSI (hardware software interface) changes patch 9 - qed: Add '_GTT' suffix to the IRO RAM macros patch 10 - qed: Update debug related changes patch 11 - qed: rdma: Update TCP silly-window-syndrome timeout patch 12 - qed: Update the TCP active termination 2 MSL timer patch 13 - qed: fix ll2 establishment during load of RDMA driver In addition, this patch series also fixes existing checkpatch warnings and checks which are missing. Changes for v2: - Incorporated Jakub's comments. - New patch introduced to fix all kernel-doc issue in qed driver. - Fixed warning: ‘qed_mfw_ext_20g’ defined but not used. - Fixed warning related to kernel-doc wrt to this series. - Removed inline function declaration. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: fix ll2 establishment during load of RDMA driverManish Chopra1-5/+44
If stats ID of a LL2 (light l2) queue exceeds than the total amount of statistics counters, it may cause system crash upon enabling RDMA on all PFs. This patch makes sure that the stats ID of the LL2 queue doesn't exceed the max allowed value. Signed-off-by: Manish Chopra <manishc@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update the TCP active termination 2 MSL timer ("TIME_WAIT")Prabhakar Kushwaha3-1/+3
Initialize 2 MSL timeout value used for the TCP TIME_WAIT state to non-zero default. This patch also removes magic number from qedi/qedi_main.c. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Signed-off-by: Nikolay Assa <nassa@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update TCP silly-window-syndrome timeout for iwarp, scsiNikolay Assa3-0/+4
Update TCP silly-window-syndrome timeout, for the cases where initiator's small TCP window size prevents FW from transmitting packets on the connection. Timeout causes FW to retransmit window probes if needed, preventing I/O stall if initiator ignores first window probe. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Signed-off-by: Nikolay Assa <nassa@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update debug related changesPrabhakar Kushwaha8-505/+1031
qed_debug features are updated to support FW version 8.59.1.0 along with few enhancements. - Removal of _BB_K2 from register defines. - Add new condition cond14. - Add dump of new area sw-platform, epoch, iscsi_task_pages, fcoe_task_pages, roce_task_pages and eth_task_pages. - Introduced new functions qed_dbg_phy_size(). - Update in qed_mcp_nvm_rd_cmd() declaration. - Allow QED to control init/exit at pf level. - Dump partial "ILT-dump" if buffer size is not sufficient. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Add '_GTT' suffix to the IRO RAM macrosPrabhakar Kushwaha10-111/+143
GTT (Global translation table) is a fast-access window in the BAR into the register space, which only maps certain register addresses. This change helps enforce that only those addresses which are indeed mapped by the GTT are being accessed through it. Adding the '_GTT' suffix to the IRO FW memory (“RAM”) macros that access GTT-able region in FW memories (“RAM”) and use GTT macros to access RAM BAR from drivers. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update FW init functions to support FW 8.59.1.0Omkar Kulkarni6-200/+372
The qed_init_fw_func.c and qed_init_ops.c updated to support FW version 8.59.1.0. - Support 16-bit VPORT WFQ (weighted fair queueing) weights. - Support WFQ (weighted fair queueing) weight per VPORT + TC. - Support allocation of Tx PQs(physical queues) per PF,VF. - Modify Global RL (rate limiter) upper bound configuration. - Update FW operation functions. - Update iro_arr[] array. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Use enum as per FW 8.59.1.0 in qed_iro_hsi.hPrabhakar Kushwaha1-257/+390
qed_iro_hsi.h contains HSI changes related to storm memories access. Existing code is based on hard-coded index. Use enum as defined for FW HSI 8.59.1.0, instead of hard-coded index. This patch also removes unnecessary header file inclusion. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update qed_hsi.h for fw 8.59.1.0Prabhakar Kushwaha12-308/+1590
The qed_hsi.h has been updated to support new FW version 8.59.1.0 with changes. - Updates FW HSI (Hardware Software interface) structures. - Addition/update in function declaration and defines as per HSI. - Add generic infrastructure for FW error reporting as part of common event queue handling. - Move malicious VF error reporting to FW error reporting infrastructure. - Move consolidation queue initialization from FW context to ramrod message. qed_hsi.h header file changes lead to change in many files to ensure compilation. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update qed_mfw_hsi.h for FW ver 8.59.1.0Prabhakar Kushwaha3-263/+800
The qed_mfw_hsi.h contains HSI (Hardware Software Interface) changes related to management firmware. It has been updated to support new FW version 8.59.1.0 with below changes. - New defines for VF bitmap. - fec_mode and extended_speed defines updated in struct eth_phy_cfg. - Updated structutres lldp_system_tlvs_buffer_s, public_global, public_port, public_func, drv_union_data, public_drv_mb with all dependent new structures. - Updates in NVM related structures and defines. - Msg defines are added in enum drv_msg_code and fw_msg_code. - Updated/added new defines. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>