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2020-01-01drm/i915/gt: Restore coarse power gatingChris Wilson1-2/+4
The coarse power gating was disabled as part of commit 2248a28384fe ("drm/i915/gen8+: Add RC6 CTX corruption WA") as a prelude to recover from the context corruption; the power gating itself has no direct impact on the RC6 context corruption. However, that recovery scheme was never implemented due to difficult corner cases, and so we no longer need to keep the power gating disabled. Fixes: 2248a28384fe ("drm/i915/gen8+: Add RC6 CTX corruption WA") Closes: https://gitlab.freedesktop.org/drm/intel/issues/846 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Eero Tamminen <eero.t.tamminen@intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231122708.4025916-1-chris@chris-wilson.co.uk
2019-12-31drm/i915: Introduce remap_io_sg() to prefault discontiguous objectsAbdiel Janulgue3-20/+74
Provide a way to set the PTE within apply_page_range for discontiguous objects in addition to the existing method of just incrementing the pfn for a page range. Fixes: cc662126b413 ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET") Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191231200356.409475-1-chris@chris-wilson.co.uk
2019-12-31drm/i915/tgl: Assume future platforms will inherit TGL's SFC capabilityMatt Roper1-1/+1
Our usual i915 convention is to assume that future platforms will follow the same behavior as the latest platform of today. The VDBOX/SFC capabilities described here don't seem like something that should be specific to TGL, so let's future-proof by making the test apply to all gen12+ platforms. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224231521.3430660-1-matthew.d.roper@intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-31drm/i915/gt: Tweak flushes around ivb ppgttChris Wilson1-2/+2
A small tweak to flush then invalidate appears to improve the reliability of ppGTT switches on Ivybridge -- but does not improve hsw/vlv bcs reliability. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231120857.4014900-1-chris@chris-wilson.co.uk
2019-12-30drm/i915/gt: Leave RING_BB_STATE to default valueChris Wilson1-1/+0
Do not reset RING_BB_STATE, leaving it to the default state value. This prevents bdw/bsw from getting confused when executing batches from the GGTT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191230165821.3840449-2-chris@chris-wilson.co.uk
2019-12-30drm/i915/selftests: Flush the context workerChris Wilson2-2/+4
When cleaning up the mock device, remember to flush the context worker to free the residual GEM contexts before shutting down the device. Closes: https://gitlab.freedesktop.org/drm/intel/issues/802 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191230165821.3840449-1-chris@chris-wilson.co.uk
2019-12-30drm/i915/gt: Do not restore invalid RS stateChris Wilson1-13/+11
Only restore valid resource streamer state from the context image, i.e. avoid restoring if we know the image is invalid. Closes: https://gitlab.freedesktop.org/drm/intel/issues/446 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191229183153.3719869-4-chris@chris-wilson.co.uk Cc: stable@vger.kernel.org
2019-12-30drm/i915/gt: Avoid using the GPU before initialisationChris Wilson4-5/+13
Mark the GT as wedged so that we are not tempted to use it prior to initialisation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191229183153.3719869-3-chris@chris-wilson.co.uk
2019-12-30drm/i915/gt: Avoid using tag 0 for the very first submissionChris Wilson1-1/+3
Assume that the HW starts off with tag 0 "active" and so avoid using tag 0 for our own first ELSP submission. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191229183153.3719869-2-chris@chris-wilson.co.uk
2019-12-30drm/i915/gt: Ensure that all new contexts clear STOP_RINGChris Wilson1-3/+11
Set up the RING_MI_MODE in new contexts to clear the STOP_RING bit, just in case they find it still set after a reset (as they are the first contexts to be run). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191229183153.3719869-1-chris@chris-wilson.co.uk
2019-12-30pinctrl: Allow modules to use pinctrl_[un]register_mappingsHans de Goede5-32/+24
Currently only the drivers/pinctrl/devicetree.c code allows registering pinctrl-mappings which may later be unregistered, all other mappings are assumed to be permanent. Non-dt platforms may also want to register pinctrl mappings from code which is build as a module, which requires being able to unregister the mapping when the module is unloaded to avoid dangling pointers. To allow unregistering the mappings the devicetree code uses 2 internal functions: pinctrl_register_map and pinctrl_unregister_map. pinctrl_register_map allows the devicetree code to tell the core to not memdup the mappings as it retains ownership of them and pinctrl_unregister_map does the unregistering, note this only works when the mappings where not memdupped. The only code relying on the memdup/shallow-copy done by pinctrl_register_mappings is arch/arm/mach-u300/core.c this commit replaces the __initdata with const, so that the shallow-copy is no longer necessary. After that we can get rid of the internal pinctrl_unregister_map function and just use pinctrl_register_mappings directly everywhere. This commit also renames pinctrl_unregister_map to pinctrl_unregister_mappings so that its naming matches its pinctrl_register_mappings counter-part and exports it. Together these 2 changes will allow non-dt platform code to register pinctrl-mappings from modules without breaking things on module unload (as they can now unregister the mapping on unload). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20191216205122.1850923-2-hdegoede@redhat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-30drn/i915: Break up long i915_buddy_free_list() with a cond_resched()Chris Wilson1-1/+3
In the selftests, we may feed very long lists of blocks to be freed on culmination of the tests. This coupled with kasan and other malloc-tracing can make the kmem_cache_free() operation time consuming, and doing many of those trigger soft lockup warnings. Break the list up with a cond_resched(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191221144917.1040662-1-chris@chris-wilson.co.uk
2019-12-30drm/i915/dp: Disable Port sync mode correctly on teardownManasi Navare1-6/+1
While clearing the Ports ync mode enable and master select bits we need to clear the register completely instead of using disable masks v3: * Remove reg variable (Matt) v2: * Just write 0 to the reg (Ville) * Rebase Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Fixes: 51528afe7c5e ("drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence") Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191228031204.10189-3-manasi.d.navare@intel.com
2019-12-30drm/i915/dp: Make port sync mode assignments only if all tiles presentManasi Navare1-65/+117
Add an extra check before making master slave assignments for tiled displays to make sure we make these assignments only if all tiled connectors are present. If not then initialize the state to defaults so it does a normal non tiled modeset without transcoder port sync. v4: deafulat port sync values in prepare_cleared_state (Ville) v3: * Default master trans to INVALID to avoid pipe mismatch v2: * Rename icl_add_sync_mode_crtcs * Move this function just before .compute_config hook * Check if DP before master slave assignments (Ville) Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191228031204.10189-2-manasi.d.navare@intel.com
2019-12-30drm/i915/dp: Make sure all tiled connectors get added to the state with full ↵Manasi Navare1-0/+138
modeset In case of tiled displays, all the tiles are linke dto each other for transcoder port sync. So in intel_atomic_check() we need to make sure that we add all the tiles to the modeset and if one of the tiles needs a full modeset then mark all other tiles for a full modeset. We also need to force modeset for all synced crtcs after fastset check. v6: * Add comments about why we do not call drm_atomic_helper_check_modeset (Matt) * Add FIXME for a corner case where tile info might vanish (Matt) v5: * Rebase v4: * Fix logic for modeset_synced_crtcs (Ville) v3: * Add tile checks only for Gen >11 v2: * Change crtc_state scope, remove tile_grp_id (Ville) * Use intel_connector_needs_modeset() (Ville) * Add modeset_synced_crtcs (Ville) * Make sure synced crtcs are forced full modeset after fastset check (Ville) Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191228031204.10189-1-manasi.d.navare@intel.com
2019-12-30drm/fbdev: Fallback to non tiled mode if all tiles not presentManasi Navare1-0/+72
In case of tiled displays, if we hotplug just one connector, fbcon currently just selects the preferred mode and if it is tiled mode then that becomes a problem if rest of the tiles are not present. So in the fbdev driver on hotplug when we probe the client modeset, if we dont find all the connectors for all tiles, then on a connector with one tile, just fallback to the first available non tiled mode to display over a single connector. On the hotplug of the consecutive tiled connectors, if the tiled mode no longer exists because of fbcon size limitation, then return no modes for consecutive tiles but retain the non tiled mode on the 0th tile. Use the same logic in case of connected boot case as well. This has been tested with Dell UP328K tiled monitor. v3: * Check Num tiled conns that are connected (Manasi) v2: * Set the modes on consecutive hotplugged tiles to no mode if tiled mode is pruned (Dave) v1: * Just handle the 1st connector hotplug case * v1 Reviewed-by: Dave Airlie <airlied@redhat.com> Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Dave Airlie <airlied@redhat.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Dave Airlie <airlied@redhat.com> (v2) Link: https://patchwork.freedesktop.org/patch/msgid/20191211212433.18185-2-manasi.d.navare@intel.com
2019-12-30drm: Handle connector tile support only for modes that match tile sizeManasi Navare1-1/+3
DRM Fb driver expects multiple CRTCs if it sees connector->has_tile is set, but we need to handle tile support and look for multiple CRTCs only for the modes that match the tile size. The other modes should be able to be displayed without tile support or uisng single CRTC. This patch adds the check to match the tile size with requested mode to handle the tile support. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191211212433.18185-1-manasi.d.navare@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for tigerlakeLucas De Marchi1-3/+3
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts tigerlake to tgl where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-10-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for ivybridgeLucas De Marchi3-11/+11
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts ivybridge to ivb where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-9-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for broadwellLucas De Marchi5-13/+13
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts broadwell to bdw where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-8-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for ironlakeLucas De Marchi11-126/+125
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts ironlake to ilk where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-7-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for icelakeLucas De Marchi2-9/+8
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts icelake to icl where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-6-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for cannonlakeLucas De Marchi1-4/+3
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts cannonlake to cnl where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-5-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for skylakeLucas De Marchi7-23/+22
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts skylake to skl where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-4-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for haswellLucas De Marchi3-33/+32
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts haswell to hsw where appropriate. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-3-lucas.demarchi@intel.com
2019-12-29drm/i915: prefer 3-letter acronym for pineviewLucas De Marchi2-20/+29
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts pineview to pnv where appropriate. v2: Add missing conversions in intel_pm.c (Matt Roper). While at it, fix missing blank lines between structs that would otherwise trigger checkpatch errors (Lucas) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-2-lucas.demarchi@intel.com
2019-12-29drm/i915: simplify prefixes on device_infoLucas De Marchi1-115/+115
Drop the intel prefix since all these structs are static and prefer using the 3-letter prefix for each platform. v2: also remove gen from the device info (Ville) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-1-lucas.demarchi@intel.com
2019-12-28drm/i915/lmem: debugfs for LMEM detailsLukasz Fiedorowicz6-2/+36
Debugfs i915_gem_object is extended to enable the IGTs to detect the LMEM's availability and the total size of LMEM. v2: READ_ONCE is used [Chris] v3: %pa is used for printing the resource [Chris] v4: All regions' details added to debugfs [Chris] v5: Macro for_each_mem_region added name is initialized at region init [Chris] Signed-off-by: Lukasz Fiedorowicz <lukasz.fiedorowicz@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191227133748.4330-1-ramalingam.c@intel.com
2019-12-28drm/i915: Restore very early GPU resetChris Wilson1-0/+11
In commit d03b224f4252 ("drm/i915/gt: Apply sanitiization just before resume") the GT sanitization was pulled into the resume path as we need to know the backend in order to do a full reset prior to resume. However, it is still imperative that we scrub existing GPU state before clobbering in our early setup, so restore a minimal GPU reset at the start of our init sequence. Fixes: d03b224f4252 ("drm/i915/gt: Apply sanitiization just before resume") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191228111255.3086901-1-chris@chris-wilson.co.uk
2019-12-27drm/i915/tgl: Extend Wa_1408615072 to tglMatt Roper2-0/+7
Although the workaround number and description are the same, the vsunit clock gate disable bit has moved to a new register and location on gen12. Bspec: 52890 Bspec: 52758 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-4-matthew.d.roper@intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-27drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehlMatt Roper2-1/+11
Workaround database indicates we should disable clock gating of both the vsunit and hsunit. Bspec: 33450 Bspec: 33451 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-3-matthew.d.roper@intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-27drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tglMatt Roper1-2/+5
WaDisableDARBFClkGating, now known as Wa_14010480278, has been added to the workaround tables for ICL, EHL, and TGL so we need to extend our platform test accordingly. Bspec: 33450 Bspec: 33451 Bspec: 52890 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-2-matthew.d.roper@intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-27drm/i915/selftests: Err out on coherency if initialisation failedChris Wilson1-4/+8
If gt initialisation failed, we are left with no engines to use for coherency testing. Currently we bug out, which makes the actual error, so fail more gracefully instead. Closes: https://gitlab.freedesktop.org/drm/intel/issues/896 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191227103050.2715402-1-chris@chris-wilson.co.uk
2019-12-27drm/komeda: Add runtime_pm supportjames qian wang (Arm Technology China)4-53/+53
- Add pm_runtime_get/put to crtc_enable/disable along with the real display usage - Add runtime_get/put to register_show, since register_show() will access register, need to wakeup HW. - For the case that PM is not enabled or configured, manually wakeup HW Signed-off-by: james qian wang (Arm Technology China) <james.qian.wang@arm.com> Reviewed-by: Mihail Atanassov <mihail.atanassov@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191212074756.14678-1-james.qian.wang@arm.com
2019-12-27Merge tag 'drm-intel-next-2019-12-23' of ↵Dave Airlie240-7851/+12435
git://anongit.freedesktop.org/drm/drm-intel into drm-next i915 features for v5.6: - Separate hardware and uapi state (Maarten) - Expose a number of sprite and plane formats (Ville) - DDC symlink in HDMI connector sysfs directory (Andrzej Pietrasiewicz) - Improve obj->mm.lock nesting lock annotation (Daniel) (Includes lockdep changes) - Selftest improvements across the board (Chris) - ICL/TGL VDSC support on DSI (Jani, Vandita) - TGL DSB fixes (Animesh, Lucas, Tvrtko) - VBT parsing improvements and fixes (Lucas, Matt, José, Jani, Dan Carpenter) - Fix LPSS vs. PMIC PWM backlight use on BYT/CHT (Hans) (Includes ACPI+MFD changes) - Display state, crtc, plane code refactoring (Ville) - Set opregion chpd value to indicate the driver handles hotplug (Hans de Goede) - DSI updates and fixes, TGL pipe D support, port mapping (José, Jani, Vandita) - Make HDCP 2.2 support cover CFL (Juston Li) - Fix CML PCI IDs and ULT (Shawn Lee) - CMP-V PCH fix (Imre) - TGL: Add another TGL PCH ID (James) - EHL/JSL: Add new PCI IDs (James) - Rename pipe update tracepoints (Ville) - Fix FBC on GLK+ (Ville) - GuC fixes and improvements (Daniele, Don Hiatt, Stuart Summers, Matthew Brost) - Display debugfs improvements (Ville) - Hotplug/irq fixes (Matt) - PSR fixes and improvements (José) - DRM_I915_GEM_MMAP_OFFSET ioctl (Abdiel) - Static analysis fixes (Colin Ian King) - Register sysctl path globally (Venkata Sandeep Dhanalakota) - Introduce new macros for tracing (Venkata Sandeep Dhanalakota) - Migrate gt towards intel_uncore_read/write (Andi) - Add rps frequency translation helpers (Andi) - Fix TGL transcoder clock off sequence (José) - Fix TGL port A audio (Kai Vehmanen) - TGL render decompression (DK) - GEM/GT improvements and fixes across the board (Chris) - Couple of backmerges (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Tue 24 Dec 2019 03:20:48 AM AEST # gpg: using RSA key D398079D26ABEE6F # gpg: Good signature from "Jani Nikula <jani.nikula@intel.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 1565 A65B 77B0 632E 1124 E59C D398 079D 26AB EE6F # Conflicts: # drivers/gpu/drm/i915/display/intel_fbc.c # drivers/gpu/drm/i915/gt/intel_lrc.c # drivers/gpu/drm/i915/i915_gem.c From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87lfr3rkry.fsf@intel.com
2019-12-27drm/komeda: Add event handling for EMPTY/FULLjames qian wang (Arm Technology China)4-2/+21
EMPTY/FULL are HW input/output FIFO condition identifer, which are useful information for addressing the problem, so expose them. Signed-off-by: james qian wang (Arm Technology China) <james.qian.wang@arm.com> Reviewed-by: Mihail Atanassov <mihail.atanassov@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191212072737.30116-1-james.qian.wang@arm.com
2019-12-26drm/i915/gt: Ignore incomplete engines after init failureChris Wilson3-3/+12
Do not expose incomplete engines to the user after we fail to setup the GT. Fixes: e6ba76480299 ("drm/i915: Remove i915->kernel_context") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Acked-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191226191237.2654510-1-chris@chris-wilson.co.uk
2019-12-26drm/i915/gt: Apply sanitiization just before resumeChris Wilson5-29/+14
Bring sanitization completely underneath the umbrella of intel_gt, and perform it exclusively after suspend and before the next resume. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191226111834.2545953-1-chris@chris-wilson.co.uk
2019-12-26drm/sun4i: dsi: Add Allwinner A64 MIPI DSI supportJagan Teki1-0/+1
The MIPI DSI controller in Allwinner A64 is similar to A33. But unlike A33, A64 doesn't have DSI_SCLK gating so add compatible for Allwinner A64 with uninitialized has_mod_clk driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Merlijn Wajer <merlijn@wizzup.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20191222132229.30276-6-jagan@amarulasolutions.com
2019-12-26drm/sun4i: dsi: Handle bus clock via regmap_mmio_attach_clkJagan Teki1-8/+29
regmap has special API to enable the controller bus clock while initializing register space, and current driver is using devm_regmap_init_mmio_clk which require to specify bus clk_id argument as "bus" But, the usage of clocks are varies between different Allwinner DSI controllers. Clocking in A33 would need bus and mod clocks where as A64 would need only bus clock. Since A64 support only single bus clock, it is optional to specify the clock-names on the controller device tree node. So using NULL on clk_id would get the attached clock. To support clk_id as "bus" and "NULL" during clock enablement between controllers, this patch add generic code to handle the bus clock using regmap_mmio_attach_clk with associated regmap APIs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20191222132229.30276-5-jagan@amarulasolutions.com
2019-12-26drm/sun4i: dsi: Get the mod clock for A31Jagan Teki1-4/+7
As per the user manual, look like mod clock is not mandatory for all Allwinner MIPI DSI controllers, it is connected to CLK_DSI_SCLK for A31 and not available in A64. So, add compatible check for A31 and get mod clock accordingly. Tested-by: Merlijn Wajer <merlijn@wizzup.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20191222132229.30276-4-jagan@amarulasolutions.com
2019-12-26dt-bindings: sun6i-dsi: Add A64 DPHY compatible (w/ A31 fallback)Jagan Teki1-1/+5
The MIPI DSI PHY controller on Allwinner A64 is similar on the one on A31. Add A64 compatible and append A31 compatible as fallback. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20191222132229.30276-3-jagan@amarulasolutions.com
2019-12-26dt-bindings: sun6i-dsi: Document A64 MIPI-DSI controllerJagan Teki1-2/+31
The MIPI DSI controller in Allwinner A64 is similar to A33. But unlike A33, A64 doesn't have DSI_SCLK gating so it is valid to have separate compatible for A64 on the same driver. DSI_SCLK uses mod clock-names on dt-bindings, so the same is not required for A64. On that note - A64 require minimum of 1 clock like the bus clock - A33 require minimum of 2 clocks like both bus, mod clocks So, update dt-bindings so-that it can document both A33, A64 bindings requirements. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20191222132229.30276-2-jagan@amarulasolutions.com
2019-12-26drm: sun4i: Add support for suspending the display driverOndrej Jirman1-0/+22
Shut down the display engine during suspend. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20191029112846.3604925-1-megous@megous.com
2019-12-26drm/i915/gt: Stop poking at engine->serial at a high levelChris Wilson1-4/+3
In record defaults, if we emit a request we expect a context switck on parking. We need take no further action, so don't even mess with the low level engine->serial where it is not warranted. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Acked-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191225230703.2498794-1-chris@chris-wilson.co.uk
2019-12-25drm/i915: Add spaces before compound GEM_TRACEChris Wilson2-2/+2
Add a space between the prefixed format and the users format so that the join are not mistakenly combined into one long word. Fixes: 639f2f24895f ("drm/i915: Introduce new macros for tracing") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191223204411.2355304-1-chris@chris-wilson.co.uk
2019-12-24drm/i915: Switch context id allocation directly to xarrayTvrtko Ursulin3-36/+25
IDR internally uses xarray so we can use it directly which simplifies our code by removing the need to do external locking. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191224095920.2386297-1-chris@chris-wilson.co.uk
2019-12-24drm/i915/gt: Flush other retirees inside intel_gt_retire_requests()Chris Wilson3-17/+7
Our goal in wait_for_idle (intel_gt_retire_requests) is to the current workload *and* their idle barriers. This requires us to notice the late arrival of those, which is done by inspecting the list of active timelines. However, if a concurrent retirer is running that new timeline may not be added until after we drop the lock -- so flush concurrent retirers before we take the lock and inspect the list. Closes: https://gitlab.freedesktop.org/drm/intel/issues/878 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191223211008.2371613-1-chris@chris-wilson.co.uk
2019-12-24drm/i915/display: cleanup intel_bw_state on i915 module removalPankaj Bharadiya3-0/+8
intel_bw_state allocated memory is not getting freed even after module removal. kmemleak reported backtrace: [<0000000079019739>] kmemdup+0x17/0x40 [<00000000d58c1b9d>] intel_bw_duplicate_state+0x1b/0x40 [i915] [<000000007423ed0c>] drm_atomic_get_private_obj_state+0xca/0x140 [<00000000100e3533>] intel_bw_atomic_check+0x133/0x350 [i915] [<00000000126d0e0c>] intel_atomic_check+0x1ab7/0x20d0 [i915] [<00000000d5dfc004>] drm_atomic_check_only+0x563/0x810 [<00000000c9379611>] drm_atomic_commit+0xe/0x50 [<00000000ec82b765>] drm_atomic_helper_disable_all+0x133/0x160 [<000000003c44760c>] drm_atomic_helper_shutdown+0x65/0xc0 [<00000000414e3e5c>] i915_driver_remove+0xcb/0x130 [i915] [<00000000f8544c2a>] i915_pci_remove+0x19/0x40 [i915] [<000000002dcbd148>] pci_device_remove+0x36/0xb0 [<000000003c8c6b0a>] device_release_driver_internal+0xe0/0x1c0 [<00000000580e9566>] unbind_store+0xc3/0x120 [<00000000869d0df5>] kernfs_fop_write+0x104/0x190 [<000000004dc1a355>] vfs_write+0xb9/0x1d0 Call the drm_atomic_private_obj_fini(), which inturn calls the intel_bw_destroy_state() to make sure the intel_bw_state memory is freed properly. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191209143921.9240-1-pankaj.laxminarayan.bharadiya@intel.com
2019-12-23drm/amdgpu: use true, false for bool variable in amdgpu_psp.czhengbin1-6/+6
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:674:2-26: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:794:1-25: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:897:2-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1016:1-35: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1087:2-34: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1177:1-33: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 22:50:15 +0300