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2022-02-18drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine wa listSrinivasan Shanmugam1-27/+35
Registers that belong to the shared render/compute reset domain need to be placed on an engine workaround list to ensure that they are properly re-applied whenever any RCS or CCS engine is reset, even if the registers do not belong to a specific engine's MMIO range. We have a number of workarounds today that are incorrectly implemented on the 'gt' workaround list and need to be moved accordingly. We also have one workaround (Wa_22012532006) that is incorrectly implemented on the context workaround list, even though the register it is adjusting is not part of the RCS engine's context image; it must also be moved. We'll have some workaround refactoring coming in the near future that deals with registers in the reset domain in a more clear way. But in the meantime, we should just move these workarounds to rcs_engine_wa_init() to place them on the RCS engine's workaround list. All production DG2 platforms will have an RCS engine (it's never fused off) so these registers will be properly restored after a domain reset triggered via an RCS engine _or_ a CCS engine. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.s@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220215235531.2236399-1-matthew.d.roper@intel.com
2022-02-17drm/amdkfd: Use proper enum in pm_unmap_queues_v9()Nathan Chancellor1-1/+1
Clang warns: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.c:267:3: error: implicit conversion from enumeration type 'enum mes_map_queues_extended_engine_sel_enum' to different enumeration type 'enum mes_unmap_queues_extended_engine_sel_enum' [-Werror,-Wenum-conversion] extended_engine_sel__mes_map_queues__sdma0_to_7_sel : ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Use 'extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel' to eliminate the warning, which is the same numeric value of the proper type. Fixes: 009e9a158505 ("drm/amdkfd: navi2x requires extended engines to map and unmap sdma queues") Link: https://github.com/ClangBuiltLinux/linux/issues/1596 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: add gc 10.3.6 supportYifan Zhang3-3/+91
this patch adds gc 10.3.6 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: add support for gmc10 for gc 10.3.6Yifan Zhang3-0/+5
this patch adds support for gmc10. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: add Clock and Power Gating support for gc 10.3.6Yifan Zhang1-2/+18
Add below supports: GFX Coarse Grain Clock Gating(CGCG) GFX Coarse grain light sleep/deep sleep(CGLS) GFX Medium Grain Clock Gating(MGCG) GFX Medium Grain light sleep/deep sleep(MGLS) GFX Fine Grain Clock Gating(FGCG) RLC MGLS CP MGLS MMHUB Clock Gating SDMA Clock Gating HDP Clock Gating ATHUB Clock Gating IH Clock Gating GFX Power Gating Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: add nv common init for gc 10.3.6Yifan Zhang2-0/+6
This patch adds add nv common init for gc 10.3.6. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/smu11.5: restore cclks in vangogh_set_performance_levelAlex Deucher1-1/+19
When we disable manual clock setting, we need to restore the cclks as well as the gfxclk. Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: fix amdgpu_ras_block_late_init error handlerTom Rix1-6/+5
Clang build fails with amdgpu_ras.c:2416:7: error: variable 'ras_obj' is used uninitialized whenever 'if' condition is true if (adev->in_suspend || amdgpu_in_reset(adev)) { ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ amdgpu_ras.c:2453:6: note: uninitialized use occurs here if (ras_obj->ras_cb) ^~~~~~~ There is a logic error in the error handler's labels. ex/ The sysfs: is the last goto label in the normal code but is the middle of error handler. Rework the error handler. cleanup: is the first error, so it's handler should be last. interrupt: is the second error, it's handler is next. interrupt: handles the failure of amdgpu_ras_interrupt_add_hander() by calling amdgpu_ras_interrupt_remove_handler(). This is wrong, remove() assumes the interrupt has been setup, not torn down by add(). Change the goto label to cleanup. sysfs is the last error, it's handler should be first. sysfs: handles the failure of amdgpu_ras_sysfs_create() by calling amdgpu_ras_sysfs_remove(). But when the create() fails there is nothing added so there is nothing to remove. This error handler is not needed. Remove the error handler and change goto label to interrupt. Fixes: b293e891b057 ("drm/amdgpu: add helper function to do common ras_late_init/fini (v3)") Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Dynamically initialize IP instance attributesLuben Tuikov1-11/+6
Dynamically initialize IP instance attributes. This eliminates bugs stemming from adding new attributes to an IP instance. Cc: Alex Deucher <Alexander.Deucher@amd.com> Reported-by: Tom StDenis <tom.stdenis@amd.com> Fixes: 4d7ba312dd1f ("drm/amdgpu: Add "harvest" to IP discovery sysfs") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/amdgpu: Add APU flag to gca_config debugfs data (v3)Tom St Denis1-1/+4
Needed by umr to detect if ip discovered ASIC is an APU or not. (v2): Remove asic type from packet it's not strictly needed (v3): Correct comment Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd: Use amdgpu_device_should_use_aspm on navi umd pstate switchingMario Limonciello1-1/+2
The `program_aspm` callback is already guarded for aspm, but the `enable_aspm` callback doesn't follow the module parameter. Update it to use the helper `amdgpu_device_should_use_aspm`. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd: Refactor `amdgpu_aspm` to be evaluated per deviceMario Limonciello9-9/+32
Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Fix ARM compilation warningLuben Tuikov1-1/+1
Fix this ARM warning: drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:664:35: warning: format '%ld' expects argument of type 'long int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Wformat=] Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: kbuild-all@lists.01.org Cc: linux-kernel@vger.kernel.org Reported-by: kernel test robot <lkp@intel.com> Fixes: a6c40b178092 ("drm/amdgpu: Show IP discovery in sysfs") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd: Check if ASPM is enabled from PCIe subsystemMario Limonciello1-0/+3
commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") enabled ASPM by default but a variety of hardware configurations it turns out that this caused a regression. * PPC64LE hardware does not support ASPM at a hardware level. CONFIG_PCIEASPM is often disabled on these architectures. * Some dGPUs on ALD platforms don't work with ASPM enabled and PCIe subsystem disables it Check with the PCIe subsystem to see that ASPM has been enabled or not. Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") Link: https://wiki.raptorcs.com/w/images/a/ad/P9_PHB_version1.0_27July2018_pub.pdf Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1723 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1739 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1885 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1907 Tested-by: koba.ko@canonical.com Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Remove redundant .ras_late_init initialization in some ras blocksyipechai4-9/+9
1. Define amdgpu_ras_block_late_init_default in amdgpu_ras.c as .ras_late_init common function, which is called when .ras_late_init of ras block isn't initialized. 2. Remove the code of using amdgpu_ras_block_late_init to initialize .ras_late_init in ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: define amdgpu_ras_late_init to call all ras blocks' .ras_late_inityipechai7-59/+34
Define amdgpu_ras_late_init to call all ras blocks' .ras_late_init. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Optimize xxx_ras_late_init function of each ras blockyipechai9-18/+18
1. Move calling ras block instance members from module internal function to the top calling xxx_ras_late_init. 2. Module internal function calls can only use parameter variables of xxx_ras_late_init instead of ras block instance members. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Remove redundant calls of ras_late_init in mca ras blockyipechai4-30/+6
Remove redundant calls of ras_late_init in mca ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Remove redundant calls of ras_late_init in mmhub ras blockyipechai4-8/+2
Remove redundant calls of ras_late_init in mmhub ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Remove redundant calls of ras_late_init in hdp ras blockyipechai3-7/+2
Remove redundant calls of ras_late_init in hdp ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: Modify .ras_late_init function pointer parameteryipechai15-17/+17
Modify .ras_late_init function pointer parameter so that it can remove redundant intermediate calls in some ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/discovery: Add sw DM function for 3.1.6 DCEPrike Liang1-0/+1
Add 3.1.6 DCE IP and assign relevant sw DM function for the new DCE. Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/display: Add DCN316 resource and SMU clock managerHansen Dsouza11-3/+3647
Add core DC implementation for DCN316. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/display: Add DMUB support for DCN316Leo Li6-1/+103
Initialize DMUB for DCN316. Use same funcs as DCN31 for DCN316. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/display: configure dc hw resource for DCN 3.1.6Prike Liang9-4/+31
- set DC version - add construct/destroy dc clock management function - register dcn interrupt handler Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/include: Add MP 13.0.8 register headersLeo Li2-0/+1013
Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/include: Add register headers for DCN 3.1.6Leo Li4-0/+226509
Add register headers for the following IPs: - DCN 3.1.6 - DPCS 4.2.3 Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/i915/lrc: replace include with forward declarationsJani Nikula2-2/+5
Prefer forward declarations over includes if possible. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220214173810.2108975-2-jani.nikula@intel.com
2022-02-17drm/i915/lrc: move lrc_get_runtime() to intel_lrc.cJani Nikula4-11/+13
Move the static inline next to the only caller. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220214173810.2108975-1-jani.nikula@intel.com
2022-02-17drm/i915/perf: Skip the i915_perf_init for dg2Ramalingam C1-0/+4
i915_perf is not enabled for dg2 yet, hence skip the feature initialization. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220215053115.6023-1-ramalingam.c@intel.com
2022-02-17drm/i915/fbdev: hide struct intel_fbdev in intel_fbdev.cJani Nikula2-21/+17
As all access to struct intel_fbdev guts is nicely stowed away in intel_fbdev.c, we can hide the struct definition there too. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220215122957.2755529-2-jani.nikula@intel.com
2022-02-17drm/i915/fbdev: add intel_fbdev_framebuffer() helperJani Nikula3-3/+18
Wrap accessing struct intel_fbdev guts in a helper. v2: s/intel_fbdev_to_framebuffer/intel_fbdev_framebuffer/g (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220215122957.2755529-1-jani.nikula@intel.com
2022-02-17drm/i915: fix build issue when using clangTong Zhang1-0/+1
drm/i915 adds some extra cflags, namely -Wall, which causes instances of -Wformat-security to appear when building with clang, even though this warning is turned off kernel-wide in the main Makefile: drivers/gpu/drm/i915/gt/intel_gt.c:983:2: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] GEM_TRACE("ERROR\n"); ^~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/i915/i915_gem.h:76:24: note: expanded from macro 'GEM_TRACE' #define GEM_TRACE(...) trace_printk(__VA_ARGS__) ^~~~~~~~~~~~~~~~~~~~~~~~~ ./include/linux/kernel.h:369:3: note: expanded from macro 'trace_printk' do_trace_printk(fmt, ##__VA_ARGS__); \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ./include/linux/kernel.h:383:30: note: expanded from macro 'do_trace_printk' __trace_bprintk(_THIS_IP_, trace_printk_fmt, ##args); \ ^~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_gt.c:983:2: note: treat the string as an argument to avoid this This does not happen with GCC because it does not enable -Wformat-security with -Wall. Disable -Wformat-security within the i915 Makefile so that these warnings do not show up with clang. Signed-off-by: Tong Zhang <ztong0001@gmail.com> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220214195821.29809-1-ztong0001@gmail.com
2022-02-17drm/i915/gvt: #include drm_edid.h for drm_edid_block_valid()Jani Nikula1-0/+2
As the excessive #includes from i915_drv.h were axed, kvmgt.c build started failing. Add the necessary #include where needed. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 14da21cc4671 ("drm/i915: axe lots of unnecessary includes from i915_drv.h") Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Cc: intel-gvt-dev@lists.freedesktop.org Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Zhi Wang <zhi.a.wang@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220215122030.2741656-1-jani.nikula@intel.com
2022-02-17drm/amdgpu/gfx10: Add GC 10.3.7 SupportPrike Liang3-1/+58
Needed to properly initialize GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdkfd: Replace zero-length array with flexible-array memberFelix Kuehling1-1/+1
Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays CC: Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/sdma5.2: add support for SDMA 5.2.7Prike Liang2-0/+6
Initialize SDMA engine firmware loading. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/pm: Add support for MP1 13.0.8Prike Liang4-0/+4
Set smu sw function and enable swSMU support for MP1. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/psp: Add support for MP0 13.0.8Prike Liang3-0/+9
Set psp sw funcs callback and firmware loading for MP0. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/gmc10: add support for GC 10.3.7Prike Liang2-0/+3
Set gfxhub function and configure VM for GC block. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: update vcn/jpeg PG flags for VCN 3.1.1Sathishkumar S1-1/+3
update vcn and jpeg power gating flags for VCN 3.1.1 Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: set new revision id for 10.3.7 GCPrike Liang1-0/+5
Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/discovery: set sw common init for GC 10.3.7Prike Liang1-0/+1
Set nv_common_ip_block for GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/discovery: Add 13.0.9 SMUIO blockPrike Liang1-0/+1
Add SMUIO sw function for the new SMUIO block. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd: smu7: downgrade voltage error to infoMario Limonciello1-2/+2
The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu/discovery: add nbio sw func for 7.5.1 nbioPrike Liang1-0/+1
add nbio sw func for the new 7.5.1 nbio block. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdgpu: make cyan skillfish support code more consistentAlex Deucher5-8/+6
Since this is an existing asic, adjust the code to follow the same logic as previously so the driver state is consistent. No functional change intended. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/display: For vblank_disable_immediate, check PSR is really usedMichel Dänzer1-8/+9
Even if PSR is allowed for a present GPU, there might be no eDP link which supports PSR. Fixes: 708978487304 ("drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdkfd: add return value check for queue evictionTao Zhou1-1/+1
Otherwise gpu reset will be triggered unconditionally in poison consumption. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amdkfd: Replace zero-length array with flexible-array memberChangcheng Deng1-1/+1
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members" for these cases. The older style of one-element or zero-length arrays should no longer be used. Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 18:10:37 +0300