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2014-07-18ARM: i.MX1 clk: Add devicetree supportAlexander Shiyan3-71/+148
This patch adds devicetree support CCM module for i.MX1 (MC9328MX1) CPUs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18ARM: imx: remove unused definesPaul Bolle1-33/+0
None of the defines "for modules using static and dynamic DMA channels" are used. Remove these. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18ARM: i.MX: Select HAVE_IMX_SRC for i.MX5 globallyAlexander Shiyan1-3/+1
No reason to choose a symbol HAVE_IMX_SRC separately for each supported i.MX5 CPU, this patch selects this symbol globally for i.MX5. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18Merge tag 'imx-fixes-3.16-2' into imx/socShawn Guo1-2/+2
The i.MX fixes for 3.16, 2nd take: It fixes a hard machine hang regression for boards where only pcie is active but no sata, as the latest imx6-pcie driver is no longer enabling the upstream clock directly but only lvds clk out.
2014-07-18ARM: clk-imx6q: parent lvds_sel input from upstream clock gatesLucas Stach1-2/+2
The i.MX6 reference manual doesn't make a clear distinction between the fixed clock divider and the enable gate for the pcie and sata reference clocks. This lead to the lvds mux inputs in the imx6q clk driver to be parented from the ref clock (which is the divider) instead of the actual gate, which in turn prevents the upstream clock to actually be enabled when lvds clk out is active. This fixes a hard machine hang regression in kernel 3.16 for boards where only pcie is active but no sata, as with this kernel version the imx6-pcie driver is no longer enabling the upstream clock directly but only lvds clk out. Reported-by: Arne Ruhnau <arne.ruhnau@target-sg.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Arne Ruhnau <arne.ruhnau@target-sg.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-17ARM: dts: keystone-evm: add 1g ethernet phys nodesGrygorii Strashko1-0/+12
Keystone EVMK2HX has two 1G Marvell 88E1111 Ethernet PHYs installed, so add corresponding child nodes for 1G MDIO bus and enable it. For more information see schematics: http://wfcache.advantech.com/www/support/TI-EVM/download/Schematics/PDF/K2H_K2EVM-HK_SCH_A102_Rev1_0.pdf Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-07-17ARM: dts: keystone: add mdio devices entriesGrygorii Strashko1-0/+11
The Keystone 2 has MDIO HW block which are compatible to Davinci SoCs: See "Gigabit Ethernet (GbE) Switch Subsystem" See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf Hence, add corresponding DT entry for Keystone 2. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-07-17ARM: tegra: roth: add display DT nodeAlexandre Courbot1-3/+19
Tegra DSI support has been fixed to support continuous clock behavior that the panel used on SHIELD requires, so finally add its device tree node since it is functional. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: Fix typoed ams,ext-control propertiesTuomas Tynkkynen2-6/+6
The property for enabling external rail control on the AS3722 is ams,ext-control, not ams,external-control. Since the external rail control property was previously being ignored, LP1 suspend on these boards wasn't actually turning the CPU rail off at all. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: jetson-tk1: Add XUSB pad controllerThierry Reding1-0/+26
Assign lanes to the XUSB pads as used on the Jetson TK1. Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: tegra124: Add XUSB pad controllerThierry Reding1-0/+10
The device tree node in the SoC file contains only the resources (such as registers, resets, ...) but none of the lane assignment information since that's board specific and belongs in the board file. Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: add GK20A GPU to Tegra124 DTThierry Reding1-0/+15
Add the GK20A device node to Tegra124's device tree. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: of: add GK20A device tree bindingAlexandre Courbot1-0/+43
Add the device tree binding documentation for the GK20A GPU used in Tegra K1 SoCs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: roth: enable input on mmc clock pinsAlexandre Courbot1-3/+3
Input had been disabled by mistake on these pins, leading to issues with SDIO devices like the Wifi module not being probed or random errors occuring on the SD card. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: roth: fix unsupported pinmux propertiesAlexandre Courbot1-4/+0
The pinmux subsystem complained that the nvidia,low-power-mode property is not supported by the sdio1, sdio3 and gma drive groups. In addition gma also does not support nvidia,drive-type. Remove these properties so the pinmux configuration can properly be applied. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: Migrate Apalis T30 PCIe power supply schemeMarcel Ziswiler1-3/+8
This migration is required for continued PCIe operation after commit d3c7e24b84fc "PCI: tegra: Implement accurate power supply scheme". Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [swarren: added commit subject and shortened hash] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: tamonten: add the display to the Medcom WideAlban Bedel1-1/+19
Enable the RGB output and add the panel definition to the Medcom Wide DTS. Also add a label to the backlight defintion to reference it in the panel definition. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: tamonten: add the base board regulatorsAlban Bedel4-9/+124
Currently the Tamonten DTS define a fixed regulator for the 5V supply. However this regulator is in fact on the base board. Fix this by properly defining the regulators found on the base boards. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: initial support for apalis t30Marcel Ziswiler4-0/+936
This patch adds the device tree to support Toradex Apalis T30, a computer on module which can be used on different carrier boards. The module consists of a Tegra 3 SoC, two PMICs, 1 or 2 GB of DDR3L RAM, eMMC, an LM95245 temperature sensor chip, an i210 resp. i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller as well as two MCP2515 CAN controllers. Furthermore, there is an SGTL5000 audio codec which is not yet supported. Anything that is not self contained on the module is disabled by default. The device tree for the Evaluation Board includes the modules device tree and enables the supported peripherals of the carrier board (the Evaluation Board supports almost all of them). While at it also add the device tree binding documentation for Apalis T30. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [swarren: fixed some node sort orders] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: jetson-tk1: mark eMMC as non-removableLucas Stach1-0/+1
The eMMC is soldered to the board, reflect this in the DT. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: venice2 - Enable HDADylan Reid1-0/+4
Turn on the HDA controller in Venice2, it is used for HDMI audio. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: Add Tegra124 HDA supportDylan Reid1-0/+15
Add a device node for the HDA controller found on Tegra124. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17ARM: tegra: Add the EC i2c tunnel to tegra124-venice2Doug Anderson1-0/+26
This adds the EC i2c tunnel (and devices under it) to the tegra124-venice2 device tree. Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-17Merge branch 'for-3.17/xusb-padctl' into for-3.17/dtThierry Reding5-0/+1114
2014-07-17Merge branch 'for-3.17/dt-cros-ec-kbd' into for-3.17/dtThierry Reding3-183/+111
2014-07-17Merge branch 'for-3.17/fuse-move' into for-3.17/dtThierry Reding57-848/+1436
2014-07-17soc/tegra: fuse: fix dummy functionsStephen Warren1-5/+5
The Tegra fuse header's dummy functions for the case where Tegra20 is disabled are inconsistent with the correct prototypes, and have some syntax errors. Fix these. While at it, fix the indentation level of the dummy function bodies. Fixes: 783c8f4c8445 ("soc/tegra: Add efuse driver for Tegra") Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17soc/tegra: fuse: move APB DMA into Tegra20 fuse driverPeter De Schrijver6-259/+76
The Tegra20 fuse driver is the only user of tegra_apb_readl_using_dma(). Therefore we can simply the code by incorporating the APB DMA handling into the driver directly. tegra_apb_writel_using_dma() is dropped because there are no users. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17soc/tegra: Add efuse and apbmisc bindingsPeter De Schrijver6-0/+113
Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17soc/tegra: Add efuse driver for TegraPeter De Schrijver20-461/+1047
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: move fuse exports to soc/tegra/fuse.hPeter De Schrijver6-14/+22
All fuse related functionality will move to a driver in the following patches. To prepare for this, export all the required functionality in a global header file and move all users of fuse.h to soc/tegra/fuse.h. While we're at it, remove tegra_bct_strapping, as its only user was removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling driver"). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: export apb dma readl/writelPeter De Schrijver2-20/+45
Export APB DMA readl and writel. These are needed because we can't access the fuses directly on Tegra20 without potentially causing a system hang. Also have the APB DMA readl and writel return an error in case of a read failure instead of just returning zero or ignore write failures. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: Use a function to get the chip IDThierry Reding14-43/+65
Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: Sort includes alphabeticallyThierry Reding23-85/+89
If these aren't sorted alphabetically, then the logical choice is to append new ones, however that creates a lot of potential for conflicts because every change will then add new includes in the same location. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: Move includes to include/soc/tegraThierry Reding15-24/+37
In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-16ARM: mvebu: update Armada XP DT for dynamic frequency scalingThomas Petazzoni4-1/+9
In order to support dynamic frequency scaling: * the cpuclk Device Tree node needs to be updated to describe a second set of registers describing the PMU DFS registers. * the clock-latency property of the CPUs must be filled, otherwise the ondemand and conservative cpufreq governors refuse to work. The latency is high because the cost of a frequency transition is quite high on those CPUs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-16ARM: mvebu: add CA9 MPcore SoC Controller nodeGregory CLEMENT2-0/+19
The CA9 MPcore SoC Control block is a set of registers that allows to configure certain internal aspects of the core blocks of the SoC (Cortex-A9, L2 cache controller, etc.). In most cases, the default values are fine so they aren't many reasons to touch those registers, but there is one exception: to support cpuidle on Armada 38x, we need to modify the value of the CA9 MPcore Reset Control register. Therefore, this commit adds a new Device Tree binding for this hardware block, and uses this new binding for the Armada 38x Device Tree file. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: devicetree@vger.kernel.org Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-16ARM: dts: remove display power domain for exynos5420Rahul Sharma1-6/+0
Display domain is removed due to instability issues. Explaining the problem below: exynos_init_late triggers the pm_genpd_poweroff_unused which powers off the unused power domains. This call hits before the trigger to deferred probes. DRM DP Panel defers the probe due to supply get failure. By the time, deferred probe is scheduled again, Display Power Domain is powered off by pm_genpd_poweroff_unused. FIMD and DP drivers are accessing registers during Probe and Bind callbacks. If display domain is enabled/disabled around register accesses, display domain gets unstable and we are getting Power Domain Disable fail notification. Increasing the Timeout also didn't help. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: Add sound nodes for Odroid-X2/U3 boardsSylwester Nawrocki3-0/+48
Add MAX98090 audio codec, I2S interface and the sound complex nodes to enable audio on Odroid-X2/U3 boards. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: fix T-FLASH hotplug detection for exynos4412-odroid-commonMarek Szyprowski1-0/+2
TFLASH (SDHCI2 controller) uses internal card detect line, but it looks that the driver fails to operate it properly. Use GPIO interrupt on SD_CDn line for detecting SD card state. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: add support for GPIO buttons for exynos4412-odroidMarek Szyprowski2-0/+45
This patch adds support for simple GPIO-based button availabled on Exynos4 based Odroid boards. All supported boards have POWER button, which has been defined in exynos4412-odroid-common.dtsi. X/X2 boards also have additional user-configurable button which has been mapped to KEY_HOME. All defined keys have been marked as possible wakeup source. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: disable 'always on' for BUCK8 regulator for exynos4412-odroid-commonKamil Debski1-1/+0
On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3 source, which is also connected to LAN9730 chip's nRESET signal. To reset lan chip on system reboot, the BUCK8 output should not be used in 'always on' mode. This change has no impact on X/X2 boards. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: refactor Odroid DTS file and add support for Odroid X2 and U2/U3Marek Szyprowski5-315/+404
This patch moves some parts of exynos4412-odroidx.dts to common exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz instead of 1.4GHz), while U2/U3 differs from X2 by different way of routing signals to host USB hub. It also lacks some hw modules not yet supported by those dts files (i.e. LCD & touch panel). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: correct memory size for exynos4412-odroidxMarek Szyprowski1-1/+1
Last megabyte of RAM is used by secure firmware and should not be accessed by Linux kernel, so correct available memory size in DTS file. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: add support for USB phy, host and device for exynos4412-odroidxKamil Debski1-0/+27
This patch adds basic support for USB modules (host and device) on OdroidX board. Signed-off-by: Kamil Debski <k.debski@samsung.com> [removed incorrect port@2 node] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: enable common hardware blocks for exynos4412-odroidxMarek Szyprowski1-0/+35
This patch adds support for common hardware modules available on all Exynos4412-based Odroid boards, which already have complete support in mainline kernel. This includes secure firmware calls, watchdog, g2d and fimc (mem2mem) multimedia accelerators. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: add port sub-nodes to exynos usb host modules for exynos4Marek Szyprowski1-0/+24
This patch adds port sub-nodes to exynos4 ehci and ohci modules, which are required by recently merged new exynos4 usb2 phy support. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: Add mask-tpm-reset node in exynos5800-peach-piVikas Sajjan1-0/+12
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from being reset across sleep/wake. If we don't set it to anything then the TPM will be reset. U-Boot will detect this as invalid and will reset the system on resume time. This GPIO can always be low and not hurt anything. It will get pulled back high again during a normal warm reset when it will default back to an input. To properly preserve the TPM state across suspend/resume and to make the chrome U-Boot happy, properly set the GPIO to mask the reset to the TPM. Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: dts: Add mask-tpm-reset node in exynos5420-peach-pitDoug Anderson1-0/+12
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from being reset across sleep/wake. If we don't set it to anything then the TPM will be reset. U-Boot will detect this as invalid and will reset the system on resume time. This GPIO can always be low and not hurt anything. It will get pulled back high again during a normal warm reset when it will default back to an input. To properly preserve the TPM state across suspend/resume and to make the chrome U-Boot happy, properly set the GPIO to mask the reset to the TPM. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-15ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040)Peter Ujfalusi1-5/+38
The board uses twl6040 codec connected via McPDM link. McBSP1 and McBSP2 can be used for FM/BT. At the same time move the pinctrl handling to the correct place - under the corresponding nodes. Audio connectors on the board: Headset in/out Stereo Line out Stereo Line in. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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