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2016-03-14drm/nouveau/clk/gk20a: fix VCO bit maskAlexandre Courbot1-1/+2
Fix the mask specified to switch to VCO mode was given as an (incorrect) immediate value. Although the side-effect happens to be the same, this is clearly incorrect. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/clk/gk20a: rename enable/disable functionsAlexandre Courbot1-28/+24
gk20a_pllg_disable() is only used in the context of gk20a_clk_fini(). Move its body there and rename _gk20a_pllg_enable() and _gk20a_pllg_disable() to non-underscored versions. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/clk/gk20a: reorganize variables in gk20a_pllg_calc_mnp()Alexandre Courbot1-4/+8
Move some variables declarations to the scope where they are actually used to make the code easier to follow. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/clk/gk20a: convert parameters to KhzAlexandre Courbot1-15/+17
Perform computations in Khz instead of Mhz for better precision. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/volt: add GM20B driverAlexandre Courbot4-0/+59
Add basic GM20B volt driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/volt/gk20a: split constructorAlexandre Courbot2-12/+25
Split the constructor function so we can reuse the same logic in other chips. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/volt/gk20a: share reusable members & functionsVince Hsu2-18/+51
The CVB calculation and voltage setting functions can be reused for the future chips. So move the declaration to gk20a.h. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/ce/gm107: expose MaxwellDmaCopyABen Skeggs4-2/+59
The HW accepts KeplerDmaCopyA and MaxwellDmaCopyA classes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gm107: KeplerChannelGpfifoB, and 2048 channelsBen Skeggs4-1/+49
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk110: expose KeplerChannelGpfifoBBen Skeggs9-2/+89
This class supports a WFI method (0x0078) that's not present on the KeplerChannelGpfifoA class. The binary driver exposes both classes on these GPUs for some reason, though there doesn't appear to be any difference in the setup that's done for each (ie. even if you allocate GpfifoA, the WFI method will still work). We shall just expose GpfifoB, as I don't see a good reason to report the presence of both. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: submit NOP after all PBDMA_INTR_0, not just DEVICEBen Skeggs1-1/+2
Prevents the same interrupt from re-triggering forever. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add vic plumbingBen Skeggs2-0/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add sec plumbingBen Skeggs2-0/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add nvdec plumbingBen Skeggs3-0/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add nvenc plumbingBen Skeggs3-7/+25
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add msenc plumbingBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add vic plumbingBen Skeggs4-0/+7
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add nvdec plumbingBen Skeggs7-0/+13
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add nvenc plumbingBen Skeggs7-21/+41
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add msenc plumbingBen Skeggs3-0/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: sort engine indices alphabeticallyBen Skeggs1-14/+17
Unlike subdevs, these aren't initialised in a defined order. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: make use of topology info during gpfifo constructionBen Skeggs5-64/+127
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: make use of topology info during fault recoveryBen Skeggs2-34/+26
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: make use of topology info when handling ctxsw timeoutBen Skeggs1-20/+9
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: read device topology information from hwBen Skeggs3-5/+103
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: cosmetic engine->runlist changesBen Skeggs4-48/+50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: don't attempt recovery of unknown mmu enginesBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: identify fault-recovery members more clearlyBen Skeggs2-10/+12
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: rename spoon to pbdma, and move detection to oneinitBen Skeggs2-10/+14
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: fix certain engines not being recovered after a faultBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: don't attempt recovery of unknown mmu enginesBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: identify fault-recovery members more clearlyBen Skeggs2-10/+12
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: rename spooon to pbdma, and move detection to oneinitBen Skeggs2-12/+17
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/fuc: Store $r0 in interrupt handlerRoy Spliet14-932/+936
It's supposed to always be 0, but at least nv_iowr() temporarily violates this. Since the ih touches $r0, it should be stored. Signed-off-by: Roy Spliet <rs855@cam.ac.uk> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: use imm32 in ld/st macrosKarol Herbst1-2/+2
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: use the call macro instead of using the call ↵Karol Herbst2-9/+9
instruction directly the macro deals with target specific differences and so we should always use this Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: replace mov+sethi with imm32Karol Herbst7-3148/+3140
on gk208+ we can simply mov 32bits, so we should have a single mov there v2: use or operator instead of add Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: fix imm32 for gk208+Karol Herbst2-442/+442
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: use vzalloc for allocating ramhtIlia Mirkin1-3/+3
Most calls to nvkm_ramht_new use 0x8000 as the size. This results in a fairly sizeable chunk of memory to be allocated, which may not be available with kzalloc. Since this is done fairly rarely (once per channel), use vzalloc instead. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: kick channel upon removalAlexandre Courbot1-0/+1
A channel may still be processed by the PBDMA even after removal, unless it is properly kicked. Some chips are more sensible to this than others, with GM20B triggering the issue very easily (the PBDMA will try to fetch methods from the previously-removed channel after a new one is added). Make sure this cannot happen by kicking the channel right after it is disabled, and before the new runlist is submitted. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/instmem/gk20a: add write barrier when releasing DMA objectAlexandre Courbot1-0/+2
When using the DMA-API for instmem, we may obtain a write-combined mapping. For such cases, add a write barrier in gk20a_instobj_release_dma() to make sure that all writes have reached memory at this time. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/device/pci: set as non-CPU-coherent on ARM64Alexandre Courbot1-1/+1
Without this buffer inconsistencies may appear between the CPU and GPU when using a PCI GPU on an ARM64 board. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/hwmon: fix crash on non-PCI platformsAlexandre Courbot1-1/+1
Registration of the hwmon device will fail on non-PCI systems since dev->pdev is NULL in that case. Use the more generic drm_device::dev member that points to the same and is always set no matter the platform. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau: silence unimportant HDMI status messageAlexandre Courbot1-1/+1
On non-PCI devices, nobody should really care if the device does not provide HDMI... Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/bo: consider DMA buffers on x86 onlyAlexandre Courbot1-2/+2
The DMA API has different semantics on different architectures. Currently on arm64, it can only provide memory from a small pool which dries up quickly if we attempt to allocate big buffers from it. Do not consider that option when running on non-x86, since regular TTM buffers are the (current) best-fit for ARM platforms. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/ltc/gf100: use more reasonable timeout valueAlexandre Courbot1-6/+2
LTC operations timeout was set to 2ms, which may be too low for devices that run at very low clocks (e.g. GM20B) and trigger timeout messages. Set the timeout to the default 2s. Also remove the redundant error messages since nvkm_wait_msec() will already display a warning. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: take runlist target into accountAlexandre Courbot1-1/+5
Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: take runlist target into accountAlexandre Courbot1-1/+5
Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: fix chid bit maskXia Yang1-2/+2
Fix the channel id bit mask in FIFO schedule timeout error handling. FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff. Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/instmem/gk20a: set DMA mask earlyAlexandre Courbot1-0/+9
DMA mask is typically set in nouveau_ttm_init(), but this function is called late during initialization and GK20A's instmem will have called DMA functions before this happens. Having a wrongly set DMA mask can result in the use of unneeded bounce buffers. Set it early to avoid this. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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