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2021-02-22drm/i915/display: Remove some redundancy around CAN_PSR()José Roberto de Souza3-6/+5
2021-02-22drm/i915/display: Only write to register in intel_psr2_program_trans_man_trk_...José Roberto de Souza1-12/+2
2021-02-22drm/i915/display: Rename for_each_intel_encoder.*_can_psr to for_each_intel_e...José Roberto de Souza4-13/+13
2021-02-22drm/i915/display: Allow PSR2 selective fetch to be enabled at run-timeJosé Roberto de Souza2-3/+6
2021-02-20drm/i915/vbt: update DP max link rate tableLee Shawn C2-21/+60
2021-02-18drm/i915: Wait for scanout to stop when sanitizing planesVille Syrjälä1-0/+1
2021-02-18drm/i915: Nuke INTEL_OUTPUT_FORMAT_INVALIDVille Syrjälä3-4/+1
2021-02-17drm/i915: Remove dead code from skl_pipe_wm_get_hw_state()José Roberto de Souza1-3/+0
2021-02-17drm/i915: Enable -WuninitializedNathan Chancellor1-1/+0
2021-02-16drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routingVille Syrjälä1-19/+19
2021-02-16drm/i915: Relocate icl_sanitize_encoder_pll_mapping()Ville Syrjälä1-56/+56
2021-02-16drm/i915: Use .disable_clock() for pll sanitationVille Syrjälä2-90/+3
2021-02-16drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,disable}_clock()Ville Syrjälä1-29/+62
2021-02-16drm/i915: Extract _cnl_ddi_{enable,disable}_clock()Ville Syrjälä1-64/+44
2021-02-16drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()Ville Syrjälä1-0/+6
2021-02-16drm/i915: Sprinkle a few missing locks around shared DDI clock registersVille Syrjälä1-0/+8
2021-02-16drm/i915: Use intel_de_rmw() for DDI clock routingVille Syrjälä1-49/+28
2021-02-16drm/i915: Extract icl+ .{enable,disable}_clock() vfuncsVille Syrjälä1-58/+99
2021-02-16drm/i915: Convert DG1 over to .{enable,disable}_clock()Ville Syrjälä1-22/+21
2021-02-16drm/i195: Extract cnl_ddi_{enable,disable}_clock()Ville Syrjälä1-20/+42
2021-02-16drm/i915: Extract skl_ddi_{enable,disable}_clock()Ville Syrjälä1-15/+38
2021-02-16drm/i915: Extract hsw_ddi_{enable,disable}_clock()Ville Syrjälä3-6/+31
2021-02-16drm/i915: Introduce .{enable,disable}_clock() encoder vfuncsVille Syrjälä4-9/+32
2021-02-16drm/i915: Use intel_ddi_clk_select() for FDIVille Syrjälä3-8/+8
2021-02-13drm/i915: move intel_init_audio_hooks inside displayLucas De Marchi2-2/+1
2021-02-13drm/i915/display: move register functions to display/Lucas De Marchi3-43/+58
2021-02-13drm/i915: group display-related register callsLucas De Marchi1-30/+34
2021-02-13drm/i915: stop registering if drm_dev_register() failsLucas De Marchi1-9/+11
2021-02-13drm/i915: Try to detect sudden loss of MMIO accessMatt Roper1-0/+16
2021-02-13drm/i915: FPGA_DBG is display-specificMatt Roper3-4/+4
2021-02-13drm/i915/gen9_bc: Add W/A for missing STRAP config on TGP PCH + CML combosLyude Paul1-1/+8
2021-02-13drm/i915/gen9_bc: Introduce HPD pin mappings for TGP PCH + CML combosLyude Paul1-0/+10
2021-02-12i915/perf: Drop the check for report reason in OAUmesh Nerlige Ramappa1-5/+0
2021-02-12drm/i915/debugfs: HDCP capability enc NULL checkAnshuman Gupta1-3/+14
2021-02-12drm/i915/display: fix comment on skl strapsLucas De Marchi1-2/+3
2021-02-12drm/i915/gen9_bc: Introduce TGP PCH DDC pin mappingsLyude Paul2-0/+29
2021-02-12drm/i915/gen9_bc: Recognize TGP PCH + CML combosLyude Paul1-1/+2
2021-02-11drm/i915/display: Handle lane polarity for DDI portUma Shankar3-0/+22
2021-02-10drm/i915/display: Add DDR5 and LPDDR5 BW buddy page entriesJosé Roberto de Souza1-0/+8
2021-02-10drm/i915: Warn when releasing a frontbuffer while in useVille Syrjälä1-0/+2
2021-02-10drm/i915: Fix overlay frontbuffer trackingVille Syrjälä1-9/+8
2021-02-10drm/i915: Disallow plane x+w>stride on ilk+ with X-tilingVille Syrjälä1-0/+27
2021-02-09drm/i915/tgl+: Make sure TypeC FIA is powered up when initializing itImre Deak1-30/+37
2021-02-09i915/perf: Add additional OA formats for gen12Umesh Nerlige Ramappa1-6/+3
2021-02-09i915/perf: Move OA formats to single arrayUmesh Nerlige Ramappa1-17/+2
2021-02-09i915/perf: Store a mask of valid OA formats for a platformUmesh Nerlige Ramappa2-1/+70
2021-02-09drm/i915/rkl: Remove require_force_probe protectionTejas Upadhyay1-1/+0
2021-02-08drm/i915: Fix HAS_LSPCON macro for platforms between GEN9 and GEN10Ankit Nautiyal1-1/+1
2021-02-08drm/i915: refactor skylake scaler code into new file.Dave Airlie14-564/+598
2021-02-08drm/i915: migrate i9xx plane get configDave Airlie3-119/+123
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