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2017-10-12ARM: dts: gr-peach: Add ETHER pin groupJacopo Mondi1-0/+39
Add pin configuration subnode for ETHER pin group. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7743: Enable DMA for HSUSBBiju Das1-0/+3
This patch adds DMA properties to the HSUSB node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7743: Add USB-DMAC device nodesBiju Das1-0/+28
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: iwg20d-q7: Enable HS-USBBiju Das1-1/+6
Enable HS-USB device for the iWave G20D-Q7 carrier board based on RZ/G1M. Also disable the host mode support on usb otg port by default to avoid pin conflicts. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7743: Add HS-USB device nodeBiju Das1-0/+14
Define the R8A7743 generic part of the HS-USB device node. It is up to the board file to enable the device. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: iwg22d-sodimm: Enable USB PHYBiju Das1-0/+4
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: iwg22d-sodimm: Enable internal PCIBiju Das1-0/+11
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7745: Link PCI USB devices to USB PHYBiju Das1-0/+24
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7745: Add USB PHY DT supportBiju Das1-0/+22
Define the r8a7745 generic part of the USB PHY device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7745: Add internal PCI bridge nodesBiju Das1-0/+46
Add device nodes for the r8a7745 internal PCI bridge devices. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7790: add cpu capacity-dmips-mhz informationDietmar Eggemann1-0/+8
The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12arm64: dts: msm8916: Mark rmtfs node as qcom, rmtfs-mem compatibleBjorn Andersson1-0/+3
Now that we have a binding defined for the shared file system memory use this to describe the rmtfs memory region. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12arm64: dts: msm8996: Add the rpm clock controller nodeRajendra Nayak1-0/+6
Add the rpm clock controller node for msm8996 devices Cc: Andy Gross <andy.gross@linaro.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12arm64: dts: qcom: sbc: Name GPIO linesLinus Walleij1-0/+169
This names the GPIO lines on the APQ8016 "SBC" also known as the DragonBoard 410c, according to the schematic. This is necessary for a conforming userspace looking across all GPIO chips for the GPIO lines named "GPIO-A" thru "GPIO-L". Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12arm64: dts: qcom: msm8916: Shrink mdp address length for msm8916Craig Tatlor1-1/+1
This shrinks the address size down to 89000 from its previous 90000 which was mistakenly pulled from downstream. Signed-off-by: Craig Tatlor <ctatlor97@gmail.com> Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12arm64: dts: apq8016-sbc: add mbhc buttons supportSrinivas Kandagatla1-0/+2
This patch adds voltage thresholds configuration required for getting audio headsets button support. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12arm64: dts: qcom: Specify dload address for msm8916 and msm8996Bjorn Andersson2-0/+9
On msm8916 and msm8996 boards a secure io-write is used to write the magic for selecting "download mode", specify this address in the DeviceTree. Note that qcom_scm.download_mode=1 must be specified on the kernel command line for the kernel to attempt selecting download mode. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12arm64: dts: apq8096-db820c: never disable regulator on LS expansionSrinivas Kandagatla1-0/+6
1.8v regulator on LS expansion should not be disabled anytime to comply with 96boards spec. So make this explicit with always-on flag. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12ARM64: dts: meson-gx: remove unnecessary uart compatibleNeil Armstrong1-5/+5
Since the switch to documented uart bindings, the old undocumented compatible binding was left for simplicity. This patch removes these unneeded compatible strings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gx: remove unnecessary clocks propertiesNeil Armstrong1-3/+0
Since the switch to documented uart bindings, the clocks are redefined in the SoC family dtsi file. This patch removes these unneeded properties. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxl: Add alternate ARM Trusted Firmware reserved memory zoneNeil Armstrong1-0/+8
This year, Amlogic updated the ARM Trusted Firmware reserved memory mapping for Meson GXL SoCs and products sold since May 2017 uses this alternate reserved memory mapping. But products had been sold using the previous mapping. This issue has been explained in [1] and a dynamic solution is yet to be found to avoid loosing another 3Mbytes of reservable memory. In the meantime, this patch adds this alternate memory zone only for the GXL and GXM SoCs since GXBB based new products stopped earlier. [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html Fixes: bba8e3f42736 ("ARM64: dts: meson-gx: Add firmware reserved memory zones") Reported-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxm: enable HS400 on the vim2Jerome Brunet1-0/+1
Enable HS400 high speed eMMC mode on the khadas vim2 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM: dts: meson: add the SDIO MMC controllerMartin Blumenstingl3-0/+21
Meson6, Meson8 and Meson8b are using the same MMC controller IP. This adds the MMC controller node to meson.dtsi so it can be used by all SoCs. The controller itself is a bit special, because it has multiple slots. Each slot is accessed through a sub-node of the controller. However, currently the driver for this hardware only supports one slot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxbb-nexbox-a95x: Enable USB NodesPeter Korsgaard1-0/+29
Enable both gxbb USB controllers and add a 5V regulator for the OTG port VBUS, similar to p20x. Signed-off-by: Peter Korsgaard <peter@korsgaard.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12dt-bindings: arm: amlogic: Add Tronsmart Vega S96 bindingNeil Armstrong1-0/+1
Cc: support@tronsmart.com Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Oleg Ivanov <balbes-150@yandex.ru> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxm: Add Vega S96 boardNeil Armstrong2-0/+39
The Tronsmart Vega S96 is a TV box derived from Amlogic q200 reference design. Cc: support@tronsmart.com Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Oleg Ivanov <balbes-150@yandex.ru> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxm: Add support for Khadas VIM2Neil Armstrong3-0/+401
The Khadas VIM2 is a Single Board Computer, respin of the origin Khadas VIM board, using an Amlogic S912 SoC and more server oriented. It provides the same external connectors and header pinout, plus a SPI NOR Flash, a reprogrammable STM8S003 MCU, FPC Connector, Cooling FAN header and Pogo Pads Arrays. Cc: Gouwa <gouwa@szwesion.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pinsNeil Armstrong14-16/+28
Since the Data Strobe pin is optional, take it out of the default eMMC pins and add a separate entry. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxl: adjust libretech-cc gpio-line-namesJerome Brunet1-4/+4
TEST_N gpio has been moved so the gpio-line-names of the cc must be adjusted accordingly Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxl: adjust kvim gpio-line-namesJerome Brunet1-4/+4
TEST_N gpio has been moved so the gpio-line-names of the kvim must be adjusted accordingly Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxbb: adjust odroid-c2 gpio-line-namesJerome Brunet1-5/+5
GPIOX22 is now declared properly and TEST_N has been moved so the gpio-line-names of the odroid-c2 must be adjusted accordingly Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxbb: adjust nanopi-k2 gpio-line-namesJerome Brunet1-5/+5
GPIOX22 is now declared properly and TEST_N has been moved so the gpio-line-names of the nanopi-k2 must be adjusted accordingly Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gx: adjust gpio-ranges for TEST_NJerome Brunet2-2/+2
TEST_N has moved from the EE controller to the AO controller so the gpio-ranges need to adjusted for it Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gx: remove gpio offsetJerome Brunet2-2/+2
Remove pin offset on the EE controller. Meson pinctrl no longer has this quirk Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM: dts: meson8: remove gpio offsetJerome Brunet2-2/+2
Remove pin offset on the AO controller. meson pinctrl no longer has this quirk Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxl-libretech-cc: enable internal phy ledsJerome Brunet1-0/+5
Enable the internal phy ACT and LINK leds pinmux Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12ARM64: dts: meson-gxl-libretech-cc: enable saradcJerome Brunet1-0/+12
Enable saradc and add the reference 1.8v regulator required. The libretech-cc has saradc channel 0 and 2 available on the 2 first pins of 2J3 header Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-12arm64: dts: apq8096-db820c: Enable on board 3 pcie root complexSrinivas Kandagatla1-0/+16
This patch adds enables 3 instances of root complexes which are exposed on DB820c board. 3 Instances are terminted as below PCIE0 => QCA6174 PCIE1 => MINI PCIE CARD PCIE2 => GBE ETHERNET Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-12arm64: dts: qcom: msm8996: add support to pcieSrinivas Kandagatla2-0/+361
This patch adds support to 3 pcie root complexes found on MSM8996. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: msm8974-FP2: Add USB nodeLuca Weiss1-0/+25
This introduces the usb node which can be used e.g. for USB_ETH Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: msm8974-FP2: Add sdhci1 nodeLuca Weiss1-0/+29
This introduces the eMMC sdhci node and its pinctrl state Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: msm8974-FP2: Add regulator nodes for FP2Luca Weiss1-0/+195
The voltages are pulled from the vendor source tree. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: msm8974-FP2: Introduce gpio-keys nodesLuca Weiss1-0/+50
This introduces the gpio-keys nodes for keys of the FP2 and the associated pinctrl state. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: qcom: Add initial DTS file for Fairphone 2 phoneLuca Weiss3-0/+24
This DTS has support for the Fairphone 2 (codenamed FP2). This first version of the DTS supports just the serial console via the MSM UART pins. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: qcom: add MSM8660 GSBI6 and GSBI7Linus Walleij1-0/+67
This adds the GSBI6 and GSBI7 IO blocks to the MSM8660 DTSI file. On the APQ8060 DragonBoard, GSBI6 DM is used for Bluetooth UART, and GSBI7 I2C is used for FM radio I2C. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: qcom: msm8974: Add Sony Xperia Z2 TabletBjorn Andersson4-0/+674
This adds a basic DTS file for the Sony Xperia Z2 Tablet, containing definitions for regulators, eMMC/SD-card, USB, WiFi, Touchscreen, charger, backlight, coincell and buttons. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: qcom-apq8064: disable gsbi6 i2c by default at soc dtsiSrinivas Kandagatla1-0/+1
This patch marks gsbi i2c node at soc level dtsi, so that kernel would not assume that its enabled and result in pin conflicts on some boards like IFC6410 which do use these pins for uart. Without this patch we see below pin conflict: apq8064-pinctrl 800000.pinctrl: pin GPIO_16 already requested by 16540000.serial; cannot claim for 16580000.i2c apq8064-pinctrl 800000.pinctrl: pin-16 (16580000.i2c) status -22 apq8064-pinctrl 800000.pinctrl: could not request pin 16 (GPIO_16) from group gpio16 on device 800000.pinctrl i2c_qup 16580000.i2c: Error applying setting, reverse things back i2c_qup: probe of 16580000.i2c failed with error -22 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-11ARM: dts: qcom-apq8064: Fix dsi and hdmi phy cellsAndy Gross1-1/+3
This patch adds the necessary #phy-cells property to the DSI and HDMI phys. Signed-off-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Archit Taneja <architt@codeaurora.org>
2017-10-11ARM: dts: omap3: Replace deprecated mcp prefixLars Poeschel1-1/+1
The devicetree prefix mcp is deprecated in favour of microchip. Thus this replaces mcp with microchip for the mcp23017 gpio expander chip. Signed-off-by: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-10-11ARM: dts: dra7-evm: Move pcie RC node to common fileRavikumar Kattekola2-4/+4
Move the pcie_rc node to common file so that it can be used by dra76-evm as well. Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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