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2022-07-13drm/amd/display: Add NBIO reg offsets to DCAurabindo Pillai4-0/+6
[Why&How] Add a field to store the NBIO IP offset for use with runtime offset calculation Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN reg offsets to DCHarry Wentland4-1/+16
[Why&How] Add a field to store the DCN IP offset for use with runtime offset calculation This offset is indexed using reg*_BASE_IDX for the corresponding group of registers. For example, address of DIG_BE_CNTL instance 0 is calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] + regDIG0_DIG_BE_CNTL. {dcn,nbio}_reg_offsets are used only for the ASICs for which runtime initializaion of offsets are enabled through the modified SR* macros that contain an additional REG_STRUCT element in the macro definition. DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They are applicable starting with DCN32/321 and are not used for ASICs upstreamed before them. ASICs before DCN32/321 will not contain any computation that involves {dcn,nbio}_reg_offsets. For them, the address/offset computation is done during compile time. This is evident from the BASE_INNER definition for compile time vs run time initialization: Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg Run time init: #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] BASE_INNER macro is local to each dcnxx_resource.c and hence different ASICs can have either runtime or compile time initialization of offsets. The computation of offset is done for registers all at once during driver load and hence it does not introduce any performance overhead during normal operation. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: add system info table logCharlene Liu1-0/+30
[why] insert log for debug use. v2: squash in fix (Alex) Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Grab dc_lock before detecting linkWayne Lin2-33/+63
[Why & How] There is chance we change dc state while calling dc_link_detect(). As the result of that, grab the dm.dc_lock before detecting link. Reviewed-by: Hersen Wu <hersen.wu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Re-implementing ARGB16161616 pixel format as 22Ethan Wellenreiter5-0/+12
[Why] ABGR16161616 colour format was added to dcn10/20/30, and set any ARGB16161616 to the same value as it (26). As such, the HDR10 Green Point y value was too far off of the EDID stated value for DisplayPort. [How] Added back the pixel format as 22 for ARGB16161616 for dcn10/20/30. Reviewed-by: Reza Amini <reza.amini@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: 3.2.193Aric Cyr1-1/+1
Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: update DML1 logic for unbounded req handlingJun Lei2-0/+18
[why] Unbounded request logic in resource/DML has some issues where unbounded request is being enabled incorrectly. SW today enables unbounded request unconditionally in hardware, on the assumption that HW can always support it in single pipe scenarios. This worked until now because the same assumption is made in DML. A new DML update is needed to fix a bug, where there are single pipe scenarios where unbounded cannot be enabled, and this change in DML needs to be ported in, and dcn32 resource logic fixed. [how] First, dcn32_resource should program unbounded req in HW according to unbounded req enablement output from DML, as opposed to DML input Second, port in DML1 update which disables unbounded req in some scenarios to fix an issue with poor stutter performance Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Jun Lei <jun.lei@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu/gfx11: add aggregated doorbell supportJack Xiao1-11/+71
Port aggregated doorbell support to gfx11. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu/sdma6: add aggregated doorbell supportJack Xiao1-23/+57
Port aggregated doorbell support to sdma6. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu/mes: ring aggregatged doorbell when mes queue is unmappedLe Ma4-34/+137
Ring aggregated doorbel to make unmapped queue scheduled in mes firmware. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu/mes11: initialize aggregated doorbellJack Xiao1-1/+57
Allocate and enable aggregated doorbell. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu/mes: init aggregated doorbellLe Ma3-6/+70
Allocate and enable aggregated doorbell. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu: support reset flag set for gpu resetLikun Gao9-27/+74
Move reset_context out of gpu recover function to make it configurable for different reset purpose. For the reset way of call gpu_recovery sysfs, force to use full reset method. Otherwise, try soft reset by default if the related ASIC supportted, if soft reset failed, will use full reset. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu: support SDMA soft recovery for sdma v6Likun Gao1-14/+37
Support SDMA soft reset for SDMA v6. V3: use ib test to check soft reset. V4: squash in unused variable fix (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu: enable soft reset for gfx 11Likun Gao1-1/+7
Enable soft reset for gfx 11. V2: enable both gfx v11.0.0 and gfx v11.0.2. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdgpu: support gfx soft reset for gfx v11Likun Gao1-49/+132
Support GFX soft reset for gfx v11. V3: use ib test check soft reset. V4: squash in unused variable fix (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Reduce SCDC Status Flags DefinitionChris Park1-5/+2
[Why] Status flags definition is reduced to read less bytes in SCDC transaction for status update. [How] Reduce definition of reserved bytes from 3 to 1 for status update. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amdkfd: correct the MEC atomic support firmware checking for GC 10.3.7Prike Liang1-0/+2
On the GC 10.3.7 platform the initial MEC release version #3 can support atomic operation,so need correct and set its MEC atomic support version to #3. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: make enable link independent from verified link capsWenjing Liu7-53/+44
[why] Ideally link capability should be independent from the link configuration that we decide to use in enable link. Otherwise if link capability is changed after validation has completed, we could end up enabling a link configuration with invalid configuration. This would lead to over link bandwidth subscription or in the extreme case causes us to enable HPO link to a DIO stream. [how] Add a new struct in pipe ctx called link config. This structure will contain link configuration to enable a link. It will be populated during map pool resources after we validate link bandwidth. Remove the reference of verified link cap during enable link process and use link config in pipe ctx instead. Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Ignore First MST Sideband Message Return ErrorFangzhi Zuo3-0/+64
[why] First MST sideband message returns AUX_RET_ERROR_HPD_DISCON on certain intel platform. Aux transaction considered failure if HPD unexpected pulled low. The actual aux transaction success in such case, hence do not return error. [how] Not returning error when AUX_RET_ERROR_HPD_DISCON detected on the first sideband message. v2: squash in additional DMI entries v3: squash in static fix Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amdkfd: bump KFD version for unified ctx save/restore memoryEric Huang1-1/+2
To expose unified memory for ctx save/resotre area feature availablity to libhsakmt. Proposed userspace: https://patchwork.freedesktop.org/series/106218/ Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: fix unnecessary pipe split playing NV12 1080p MPO videoSamson Tam1-28/+3
[Why] When playing NV12 1080p MPO video, it is pipe splitting so we see two pipes in fullscreen and four pipes in windowed mode. Pipe split is happening because we are setting MaximumMPCCombine = 1 [How] Algorithm for MaximumMPCCombine has extra conditions we do not need. Use DCN31 algorithm instead Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Fix black screen when disabling Freesync in OSDIlya Bakoulin1-0/+10
[Why] Black screen encountered when disabling Freesync through OSD on some displays. [How] Set the should_disable flag when new top pipe has no plane state to ensure that pipes get cleaned up. Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Disable PSRSU when DSC enabled on the specific sinkRobin Chen1-16/+17
[Why] Some specific sink is not able to support PSRSU when DSC is turned on. For this case, fall-back to use PSR1. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Robin Chen <po-tchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Clear edid when unplug mst connectorWayne Lin1-0/+2
[Why] When unplug one sst monitor from a mst hub and plug in the same port with another sst monitor, we don't read the corresponding edid. That's because we detect there is already an edid stored in aconnector->edid which is a stale one. [How] Clean up aconnector->edid when unplug mst connector. Reviewed-by: Hersen Wu <hersen.wu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Fix windowed MPO video with ODM combine for DCN32Samson Tam2-21/+188
[Why] In single display configuration, windowed MPO does not work with ODM combine. [How] For ODM + MPO window on one half of ODM, only 3 pipes should be allocated and scaling parameters adjusted to handle this case. Otherwise, we use 4 pipes. Move copy_surface_update_to_plane() before dc_add_plane_to_context() so that it gets the updated rect information when setting up the pipes. Add dc_check_boundary_crossing_for_windowed_mpo_with_odm() to force a full update when we cross a boundary requiring us to reconfigure the number of pipes between 3 and 4 pipes. Set config.enable_windowed_mpo_odm to true when we have the debug.enable_single_display_2to1_odm_policy set to true. Don't fail validating ODM with windowed MPO if config.enable_windowed_mpo_odm is true. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Removing assert statements for LinuxSaaem Rizvi5-9/+30
[WHY] Assert statements causing several bugs on Linux DM [HOW] Removing assert statement for Linux DM (ASSERT(result == VBIOSSMC_Result_OK)). Also adding logging statements for setting dcfclk. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=216092 Fixes: c1b972a18d05 ("drm/amd/display: Insert pulling smu busy status before sending another request") Reviewed-by: Gabe Teeger <Gabe.Teeger@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Helper function for ALPM initializationMuhammad Ansari2-10/+19
[WHY] Needed a helper function for ALPM DPCD initialization [HOW] Refactoring to put ALPM initialization in a helper function Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Muhammad Ansari <muansari@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Check for DP2.0 when checking ODM combineWesley Chalmers1-0/+1
[WHY] Certain DP 2.0 modes may fail validation if DP 2.0 is not considered for ODM combine. Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Exit SubVP if MPO in useAlvin Lee4-13/+92
[Description] Exit SubVP if MPO is in use since SubVP + MPO together is not supported. - Don't add SubVP at validation time if we see MPO is in use Issues fixed in the SubVP / MPO transition: 1. Enable phantom pipes in post unlock function to prevent underflow when an active pipe is being transitioned to be a phantom pipe (VTG updates take place right away). Also must wait for VUPDATE of the main pipe to complete first 2. Don't wait for MPCC idle when transitioning a phantom pipe to an actual pipe. MPCC_STATUS is never asserted due to OTG being off for phantom pipes 3. When transitioning an active pipe to phantom, program DET right away (same as disabling the pipe) or the DET update will only take when the phantom pipe is enabled which can cause DET allocation errors. 4. For K1/K2 programming of phantom pipes, use same settings as the main pipe. Also don't program K1 / K2 = 0xF ever since the field is only 1 / 2 bits wide. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amdgpu/mes: set correct mes ring ready flagJack Xiao2-0/+6
Set corresponding ready flag for mes ring when enable or disable mes ring. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amdgpu: Remove one duplicated ef removalxinhui pan1-6/+0
That has been done in BO release notify. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amdgpu/gmc10: adjust gart size for parts that support S/G displayAlex Deucher1-3/+14
For GMC 10 parts which support scatter/gather display (display from system memory), we should allocate a larger gart size to better handler larger displays. This mirrors what we already do for GMC 9 parts. v2: fix typo (Alex) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amdgpu/mes: fix bo va unmap issue in mesJack Xiao2-3/+60
Need reserve buffers before unmap mes ctx bo va. v2: fix removal of dma_resv_excl_fence() (Alex) v3: fix dma_resv_usage (Alex) Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-09drm/amdgpu/mes: fix mes submission in atomic contextJack Xiao4-85/+50
For some cases (accessing registers, unmap legacy queue), it needs access mes in atomic context. Use spinlock to protect agaist mes ring buffer race condition. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-09drm/amd/pm: drop the thermal_controller_type checkKenneth Feng1-5/+3
drop the thermal_controller_type check since it's not relevant. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-09drm/amd/pm: ac/dc change for smu_v13_0Kenneth Feng4-3/+37
fixed the issue: gpu runs in dc mode but it is expected to be in ac mode. this causes the lower performance on smu_v13_0 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-09drm/amd/display: Enable ODM combine default policyAurabindo Pillai2-2/+6
[Why&How] Output Data Mapping is a power saving feature that allows us to run at reduced DPP and DISP clocks compared to what could be achieved with a single pipe. Set the default policy for single display use case to use 2 to 1 ODM combine. The options are queried by DC and appropriate register programming sequence is initiated to enable this feature. Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-09drm/amd/display: Add callback to set dig modeAurabindo Pillai1-0/+12
[Why&How] Add a missing callback to set DIG FIFO output pixel mode. This is used when ODM combine is activated. Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-08drm/amd/display: fix 32 bit compilation errors in dc_dmub_srv.cAlex Deucher2-59/+34
There are several things wrong here. First, none of these numbers are FP, so there is no need to cast to double. Next make sure to use proper 64 bit division helpers. Fixes: 85f4bc0c333c ("drm/amd/display: Add SubVP required code") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amd/display: clean up some inconsistent indentingYang Li1-8/+8
Eliminate the follow smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:405 get_bios_object_from_path_v3() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:611 bios_parser_get_hpd_info() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:818 bios_parser_get_device_tag() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1599 bios_parser_is_device_id_supported() warn: inconsistent indenting Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amd/display: fix non-x86/PPC64 compilationAlex Deucher2-1/+2
Need to protect FP DMCUB code with CONFIG_DRM_AMD_DC_DCN. Fixes build failures like the following on arm64: ERROR: modpost: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__divdf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "fma" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__adddf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__fixdfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__floatsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__fixunsdfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Fixes: 85f4bc0c333c ("drm/amd/display: Add SubVP required code") Reported-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amd/display: Fix new dmub notification enabling in DMStylon Wang1-8/+19
[Why] Changes from "Fix for dmub outbox notification enable" need to land in DM or DMUB outbox notification would be disabled. [How] Enable outbox notification only after interrupt are enabled and IRQ handlers registered. Any pending notification will be sent by DMUB once outbox notification is enabled. Fixes: ed7208706448 ("drm/amd/display: Fix for dmub outbox notification enable") Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amdgpu: Fix one list corruption when create queue failsxinhui pan1-6/+5
Queue would be freed when create_queue_cpsch fails So lets do queue cleanup otherwise various list and memory issues happen. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/radeon: avoid bogus "vram limit (0) must be a power of 2" warningMateusz Jończyk1-1/+1
I was getting the following message on boot on Linux 5.19-rc5: radeon 0000:01:05.0: vram limit (0) must be a power of 2 (I didn't use any radeon.vramlimit commandline parameter). This is caused by commit 8c2d34eb53b9 ("drm/radeon: use kernel is_power_of_2 rather than local version") which removed radeon_check_pot_argument() and converted its users to is_power_of_2(). The two functions differ in its handling of 0, which is the default value of radeon_vram_limit: radeon_check_pot_argument() "incorrectly" considered it a power of 2, while is_power_of_2() does not. An appropriate conditional silences the warning message. It is not necessary to add a similar test to other callers of is_power_of_2() in radeon_device.c. The matching commit in amdgpu: commit 761175078466 ("drm/amdgpu: use kernel is_power_of_2 rather than local version") is unaffected by this bug. Tested on Radeon HD 3200. Not ccing stable, this is not serious enough. Fixes: 8c2d34eb53b9 ("drm/radeon: use kernel is_power_of_2 rather than local version") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Mateusz Jończyk <mat.jonczyk@o2.pl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amd/display: remove repeated includesGuo Zhengkui1-2/+0
Remove a repeated "#include <drm/drm_print.h>" Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amdgpu/display: Remove duplicated argument to ||Zhongjun Tan1-1/+1
Remove duplicated argument to || Signed-off-by: Zhongjun Tan <tanzhongjun@coolpad.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amd/display: make get_refresh_rate() staticAlex Deucher1-1/+1
It's not used outside of dcn30_resource.c. Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amd/display: remove set but unused variableAlex Deucher1-2/+1
Fixes the following: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:428:33: warning: variable 'old_pipe' set but not used Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-07drm/amdkfd: optimize svm range evictEric Huang1-1/+9
It is to avoid unnecessary queue eviction when range is not mapped to gpu. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-24 08:45:32 +0300