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2021-10-05fscache: Fix some kerneldoc warnings shown up by W=1David Howells2-0/+4
Fix some kerneldoc warnings in the fscache driver that are shown up by W=1. Signed-off-by: David Howells <dhowells@redhat.com> Reviewed-by: Jeff Layton <jlayton@kernel.org> cc: Mauro Carvalho Chehab <mchehab@kernel.org> cc: linux-fsdevel@vger.kernel.org cc: linux-doc@vger.kernel.org Link: https://lore.kernel.org/r/163214005516.2945267.7000234432243167892.stgit@warthog.procyon.org.uk/ # rfc v1 Link: https://lore.kernel.org/r/163281899704.2790286.9177774252843775348.stgit@warthog.procyon.org.uk/ # rfc v2
2021-10-059p: Fix a bunch of kerneldoc warnings shown up by W=1David Howells7-52/+60
Fix a bunch of kerneldoc warnings shown up by W=1 in the 9p filesystem: (1) Add/remove/fix kerneldoc parameters descriptions. (2) Move __add_fid() from between v9fs_fid_add() and its comment. (3) 9p's caches_show() doesn't really make sense as an API function, so remove the kerneldoc annotation. It's also not prefixed with 'v9fs_'. Also remove the kerneldoc markers from the 9p fscache wrappers. Signed-off-by: David Howells <dhowells@redhat.com> Reviewed-by: Dominique Martinet <asmadeus@codewreck.org> Reviewed-by: Jeff Layton <jlayton@kernel.org> cc: Mauro Carvalho Chehab <mchehab@kernel.org> cc: v9fs-developer@lists.sourceforge.net cc: linux-fsdevel@vger.kernel.org cc: linux-doc@vger.kernel.org Link: https://lore.kernel.org/r/163214005516.2945267.7000234432243167892.stgit@warthog.procyon.org.uk/ # rfc v1 Link: https://lore.kernel.org/r/163281899704.2790286.9177774252843775348.stgit@warthog.procyon.org.uk/ # rfc v2
2021-10-05afs: Fix kerneldoc warning shown up by W=1David Howells1-2/+2
Fix a kerneldoc warning in afs due to a partially documented internal function by removing the kerneldoc marker. Signed-off-by: David Howells <dhowells@redhat.com> Reviewed-by: Jeff Layton <jlayton@kernel.org> cc: Marc Dionne <marc.dionne@auristor.com> cc: linux-afs@lists.infradead.org cc: linux-fsdevel@vger.kernel.org cc: linux-doc@vger.kernel.org Link: https://lore.kernel.org/r/163214005516.2945267.7000234432243167892.stgit@warthog.procyon.org.uk/ # rfc v1 Link: https://lore.kernel.org/r/163281899704.2790286.9177774252843775348.stgit@warthog.procyon.org.uk/ # rfc v2
2021-10-05nfs: Fix kerneldoc warning shown up by W=1David Howells1-1/+0
Fix a kerneldoc warning in nfs due to documentation for a parameter that isn't present. Signed-off-by: David Howells <dhowells@redhat.com> Reviewed-by: Jeff Layton <jlayton@kernel.org> cc: Trond Myklebust <trond.myklebust@hammerspace.com> cc: Anna Schumaker <anna.schumaker@netapp.com> cc: Mauro Carvalho Chehab <mchehab@kernel.org> cc: linux-nfs@vger.kernel.org cc: linux-fsdevel@vger.kernel.org cc: linux-doc@vger.kernel.org Link: https://lore.kernel.org/r/163214005516.2945267.7000234432243167892.stgit@warthog.procyon.org.uk/ # rfc v1 Link: https://lore.kernel.org/r/163281899704.2790286.9177774252843775348.stgit@warthog.procyon.org.uk/ # rfc v2
2021-10-04i2c: mlxcpld: Modify register setting for 400KHz frequencyVadim Pasternak1-1/+1
Change setting for 400KHz frequency support by more accurate value. Fixes: 66b0c2846ba8 ("i2c: mlxcpld: Add support for I2C bus frequency setting") Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-10-04i2c: mlxcpld: Fix criteria for frequency settingVadim Pasternak1-1/+1
Value for getting frequency capability wrongly has been taken from register offset instead of register value. Fixes: 66b0c2846ba8 ("i2c: mlxcpld: Add support for I2C bus frequency setting") Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-10-04dt-bindings: drm/bridge: ti-sn65dsi86: Fix reg valueGeert Uytterhoeven1-1/+1
make dtbs_check: arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml: bridge@2c: reg:0:0: 45 was expected According to the datasheet, the I2C address can be either 0x2c or 0x2d, depending on the ADDR control input. Fixes: e3896e6dddf0b821 ("dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com> Link: https://lore.kernel.org/r/08f73c2aa0d4e580303357dfae107d084d962835.1632486753.git.geert+renesas@glider.be Signed-off-by: Rob Herring <robh@kernel.org>
2021-10-04Merge tag 'media/v5.15-3' of ↵Linus Torvalds1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media fix from Mauro Carvalho Chehab: "There's just one patch here, fixing a -Werror issue at staging/atomisp" * tag 'media/v5.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: media: atomisp: restore missing 'return' statement
2021-10-04Merge tag 'ovl-fixes-5.15-rc5' of ↵Linus Torvalds2-4/+21
git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs Pull overlayfs fixes from Miklos Szeredi: "Fix two bugs, both of them corner cases not affecting most users" * tag 'ovl-fixes-5.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs: ovl: fix IOCB_DIRECT if underlying fs doesn't support direct IO ovl: fix missing negative dentry check in ovl_rename()
2021-10-04Merge tag 'mips-fixes_5.15_1' of ↵Linus Torvalds1-22/+1
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fix from Thomas Bogendoerfer: "Revert workaround for buggy cpu detection because regressions" * tag 'mips-fixes_5.15_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: Revert "add support for buggy MT7621S core detection"
2021-10-04media: atomisp: restore missing 'return' statementArnd Bergmann1-0/+2
The input_system_configure_channel_sensor() function lost its final return code in a previous patch: drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c: In function 'input_system_configure_channel_sensor': drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c:1649:1: error: control reaches end of non-void function [-Werror=return-type] Restore what was there originally. Link: https://lore.kernel.org/linux-media/20210802143820.1150099-1-arnd@kernel.org Fixes: 728a5c64ae5f ("media: atomisp: remove dublicate code") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-10-04block: decode QUEUE_FLAG_HCTX_ACTIVE in debugfs outputJohannes Thumshirn1-0/+1
While debugging an issue we've found that $DEBUGFS/block/$disk/state doesn't decode QUEUE_FLAG_HCTX_ACTIVE but only displays its numerical value. Add QUEUE_FLAG(HCTX_ACTIVE) to the blk_queue_flag_name array so it'll get decoded properly. Signed-off-by: Johannes Thumshirn <johannes.thumshirn@wdc.com> Link: https://lore.kernel.org/r/4351076388918075bd80ef07756f9d2ce63be12c.1633332053.git.johannes.thumshirn@wdc.com Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-10-04Merge branch 'phy-10g-mode-helper'David S. Miller5-18/+15
Russell King says: ==================== Add phylink helper for 10G modes During the last cycle, there was discussion about adding a helper to set the 10G link modes for phylink, which resulted in these two patches introduce such a helper. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04net: ethernet: use phylink_set_10g_modes()Russell King (Oracle)3-18/+3
Update three drivers to use the new phylink_set_10g_modes() helper: Cadence macb, Freescale DPAA2 and Marvell PP2. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04net: phylink: add phylink_set_10g_modes() helperRussell King (Oracle)2-0/+12
Add a helper for setting 10Gigabit modes, so we have one central place that sets all appropriate 10G modes for a driver. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04dsa: tag_dsa: Fix mask for trunked packetsAndrew Lunn1-1/+1
A packet received on a trunk will have bit 2 set in Forward DSA tagged frame. Bit 1 can be either 0 or 1 and is otherwise undefined and bit 0 indicates the frame CFI. Masking with 7 thus results in frames as being identified as being from a trunk when in fact they are not. Fix the mask to just look at bit 2. Fixes: 5b60dadb71db ("net: dsa: tag_dsa: Support reception of packets from LAG devices") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04arm64: dts: ls1028a: fix eSDHC2 nodeMichael Walle1-2/+2
On the LS1028A this instance of the eSDHC controller is intended for either an eMMC or eSDIO card. It doesn't provide a card detect pin and its IO voltage is fixed at 1.8V. Remove the bogus broken-cd property, instead add the non-removable property. Fix the voltage-ranges property and set it to 1.8V only. Fixes: 491d3a3fc113 ("arm64: dts: ls1028a: Add esdhc node in dts") Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-04net: ipv6: fix use after free of struct seg6_pernet_dataMichelleJin1-1/+1
sdata->tun_src should be freed before sdata is freed because sdata->tun_src is allocated after sdata allocation. So, kfree(sdata) and kfree(rcu_dereference_raw(sdata->tun_src)) are changed code order. Fixes: f04ed7d277e8 ("net: ipv6: check return value of rhashtable_init") Signed-off-by: MichelleJin <shjy180909@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04arm64: dts: imx8mm-kontron-n801x-som: do not allow to switch off buck2Heiko Thiery1-0/+1
The buck2 output of the PMIC is the VDD core voltage of the cpu. Switching off this will poweroff the CPU. Add the 'regulator-always-on' property to avoid this. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-04Merge branch 'qed-new-fw'David S. Miller66-10293/+13425
Prabhakar Kushwaha says: ==================== qed: new firmware version 8.59.1.0 support This series integrate new firmware version 8.59.1.0, along with updated HSI (hardware software interface) to use the FW, into the family of qed drivers (fastlinq devices). This FW does not reside in the NVRAM. It needs to be programmed to device during driver load as the part of initialization sequence. Similar to previous FW support series, this FW is tightly linked to software and pf function driver. This means FW release is not backward compatible, and driver should always run with the FW it was designed against. FW binary blob is already submitted & accepted in linux-firmware repo. Patches in the series include: patch 1 - qed: Fix kernel-doc warnings patch 2 - qed: Remove e4_ and _e4 from FW HSI patch 3 - qed: split huge qed_hsi.h header file patch 4-8 - HSI (hardware software interface) changes patch 9 - qed: Add '_GTT' suffix to the IRO RAM macros patch 10 - qed: Update debug related changes patch 11 - qed: rdma: Update TCP silly-window-syndrome timeout patch 12 - qed: Update the TCP active termination 2 MSL timer patch 13 - qed: fix ll2 establishment during load of RDMA driver In addition, this patch series also fixes existing checkpatch warnings and checks which are missing. Changes for v2: - Incorporated Jakub's comments. - New patch introduced to fix all kernel-doc issue in qed driver. - Fixed warning: ‘qed_mfw_ext_20g’ defined but not used. - Fixed warning related to kernel-doc wrt to this series. - Removed inline function declaration. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: fix ll2 establishment during load of RDMA driverManish Chopra1-5/+44
If stats ID of a LL2 (light l2) queue exceeds than the total amount of statistics counters, it may cause system crash upon enabling RDMA on all PFs. This patch makes sure that the stats ID of the LL2 queue doesn't exceed the max allowed value. Signed-off-by: Manish Chopra <manishc@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update the TCP active termination 2 MSL timer ("TIME_WAIT")Prabhakar Kushwaha3-1/+3
Initialize 2 MSL timeout value used for the TCP TIME_WAIT state to non-zero default. This patch also removes magic number from qedi/qedi_main.c. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Signed-off-by: Nikolay Assa <nassa@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update TCP silly-window-syndrome timeout for iwarp, scsiNikolay Assa3-0/+4
Update TCP silly-window-syndrome timeout, for the cases where initiator's small TCP window size prevents FW from transmitting packets on the connection. Timeout causes FW to retransmit window probes if needed, preventing I/O stall if initiator ignores first window probe. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Signed-off-by: Nikolay Assa <nassa@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update debug related changesPrabhakar Kushwaha8-505/+1031
qed_debug features are updated to support FW version 8.59.1.0 along with few enhancements. - Removal of _BB_K2 from register defines. - Add new condition cond14. - Add dump of new area sw-platform, epoch, iscsi_task_pages, fcoe_task_pages, roce_task_pages and eth_task_pages. - Introduced new functions qed_dbg_phy_size(). - Update in qed_mcp_nvm_rd_cmd() declaration. - Allow QED to control init/exit at pf level. - Dump partial "ILT-dump" if buffer size is not sufficient. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Add '_GTT' suffix to the IRO RAM macrosPrabhakar Kushwaha10-111/+143
GTT (Global translation table) is a fast-access window in the BAR into the register space, which only maps certain register addresses. This change helps enforce that only those addresses which are indeed mapped by the GTT are being accessed through it. Adding the '_GTT' suffix to the IRO FW memory (“RAM”) macros that access GTT-able region in FW memories (“RAM”) and use GTT macros to access RAM BAR from drivers. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update FW init functions to support FW 8.59.1.0Omkar Kulkarni6-200/+372
The qed_init_fw_func.c and qed_init_ops.c updated to support FW version 8.59.1.0. - Support 16-bit VPORT WFQ (weighted fair queueing) weights. - Support WFQ (weighted fair queueing) weight per VPORT + TC. - Support allocation of Tx PQs(physical queues) per PF,VF. - Modify Global RL (rate limiter) upper bound configuration. - Update FW operation functions. - Update iro_arr[] array. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Use enum as per FW 8.59.1.0 in qed_iro_hsi.hPrabhakar Kushwaha1-257/+390
qed_iro_hsi.h contains HSI changes related to storm memories access. Existing code is based on hard-coded index. Use enum as defined for FW HSI 8.59.1.0, instead of hard-coded index. This patch also removes unnecessary header file inclusion. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update qed_hsi.h for fw 8.59.1.0Prabhakar Kushwaha12-308/+1590
The qed_hsi.h has been updated to support new FW version 8.59.1.0 with changes. - Updates FW HSI (Hardware Software interface) structures. - Addition/update in function declaration and defines as per HSI. - Add generic infrastructure for FW error reporting as part of common event queue handling. - Move malicious VF error reporting to FW error reporting infrastructure. - Move consolidation queue initialization from FW context to ramrod message. qed_hsi.h header file changes lead to change in many files to ensure compilation. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update qed_mfw_hsi.h for FW ver 8.59.1.0Prabhakar Kushwaha3-263/+800
The qed_mfw_hsi.h contains HSI (Hardware Software Interface) changes related to management firmware. It has been updated to support new FW version 8.59.1.0 with below changes. - New defines for VF bitmap. - fec_mode and extended_speed defines updated in struct eth_phy_cfg. - Updated structutres lldp_system_tlvs_buffer_s, public_global, public_port, public_func, drv_union_data, public_drv_mb with all dependent new structures. - Updates in NVM related structures and defines. - Msg defines are added in enum drv_msg_code and fw_msg_code. - Updated/added new defines. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update common_hsi for FW ver 8.59.1.0Prabhakar Kushwaha2-9/+106
The common_hsi.h has been updated for FW version 8.59.1.0 with below changes. - FW and Tools version. - New structures related to search table, packet duplication. - Structure for doorbell address for legacy mode without DEM. - Enhanced union rdma_eqe_data for RoCE Suspend Event Data. - New defines. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Split huge qed_hsi.h header fileOmkar Kulkarni23-3747/+3794
The qed_hsi.h is a huge header file containing HSI (Hardware Software Interface) definitions of storm memory access, debug related, general and management firmware specific. In order to have a better code-organization HSI definition, this patch split the code across multiple files, i.e. - storm memory access HSI : qed_iro_hsi.h - debug related HSI : qed_dbg_hsi.h - Management firmware HSI : qed_mfg_hsi.h - General HSI : qed_hsi.h In addition, this patch also fixes existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Remove e4_ and _e4 from FW HSIShai Malin32-3896/+3888
The existing qed/qede/qedr/qedi/qedf code uses chip-specific naming in structures, functions, variables and defines in FW HSI (Hardware Software Interface). The new FW version introduced a generic naming convention in HSI in-which the same code will be used across different versions for simpler maintainability. It also eases in providing support for new features. With this patch every "_e4" or "e4_" prefix or suffix is not needed anymore and it will be removed. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Reviewed-by: Javed Hasan <jhasan@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Fix kernel-doc warningsPrabhakar Kushwaha21-1917/+2186
This patch fixes all the qed and qede kernel-doc warnings according to the guidelines that are described in Documentation/doc-guide/kernel-doc.rst. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04Merge branch 'ipv6-ioam-encap'David S. Miller7-138/+422
Justin Iurman says: ==================== Support for the ip6ip6 encapsulation of IOAM v2: - add prerequisite patches - keep uapi backwards compatible by adding two new attributes - add more comments to document the ioam6_iptunnel uapi In the current implementation, IOAM can only be inserted directly (i.e., only inside packets generated locally) by default, to be compliant with RFC8200. This patch adds support for in-transit packets and provides the ip6ip6 encapsulation of IOAM (RFC8200 compliant). Therefore, three ioam6 encap modes are defined: - inline: directly inserts IOAM inside packets (by default). - encap: ip6ip6 encapsulation of IOAM inside packets. - auto: either inline mode for packets generated locally or encap mode for in-transit packets. With current iproute2 implementation, it is configured this way: $ ip -6 r [...] encap ioam6 trace prealloc [...] The old syntax does not change (for backwards compatibility) and implicitly uses the inline mode. With the new syntax, an encap mode can be specified: (inline mode) $ ip -6 r [...] encap ioam6 mode inline trace prealloc [...] (encap mode) $ ip -6 r [...] encap ioam6 mode encap tundst fc00::2 trace prealloc [...] (auto mode) $ ip -6 r [...] encap ioam6 mode auto tundst fc00::2 trace prealloc [...] A tunnel destination address must be configured when using the encap mode or the auto mode. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04selftests: net: Test for the IOAM encapsulation with IPv6Justin Iurman1-50/+159
This patch adds support for testing the encap (ip6ip6) mode of IOAM. Signed-off-by: Justin Iurman <justin.iurman@uliege.be> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04ipv6: ioam: Add support for the ip6ip6 encapsulationJustin Iurman3-54/+242
This patch adds support for the ip6ip6 encapsulation by providing three encap modes: inline, encap and auto. Signed-off-by: Justin Iurman <justin.iurman@uliege.be> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04ipv6: ioam: Prerequisite patch for ioam6_iptunnelJustin Iurman1-35/+20
This prerequisite patch provides some minor edits (alignments, renames) and a minor modification inside a function to facilitate the next patch by using existing nla_* functions. Signed-off-by: Justin Iurman <justin.iurman@uliege.be> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04ipv6: ioam: Distinguish input and output for hop-limitJustin Iurman3-7/+9
This patch anticipates the support for the IOAM insertion inside in-transit packets, by making a difference between input and output in order to determine the right value for its hop-limit (inherited from the IPv6 hop-limit). Input case: happens before ip6_forward, the IPv6 hop-limit is not decremented yet -> decrement the IOAM hop-limit to reflect the new hop inside the trace. Output case: happens after ip6_forward, the IPv6 hop-limit has already been decremented -> keep the same value for the IOAM hop-limit. Signed-off-by: Justin Iurman <justin.iurman@uliege.be> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04net/mlx4_en: avoid one cache line miss to ring doorbellEric Dumazet2-2/+3
This patch caches doorbell address directly in struct mlx4_en_tx_ring. This removes the need to bring in cpu caches whole struct mlx4_uar in fast path. Note that mlx4_uar is not guaranteed to be on a local node, because mlx4_bf_alloc() uses a single free list (priv->bf_list) regardless of its node parameter. This kind of change does matter in presence of light/moderate traffic. In high stress, this read-only line would be kept hot in caches. Signed-off-by: Eric Dumazet <edumazet@google.com> Cc: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pinsClaudiu Beznea1-0/+6
With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement") the slew-rate is enabled by default for each configured pin. The datasheet specifies at chapter "Output Driver AC Characteristics" that HSIO drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate setting but are rather calibrated against an external 1% resistor mounted on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal frequency and the external load, it is possible to adjust their target output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled at the moment in device tree). Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210915074836.6574-3-claudiu.beznea@microchip.com
2021-10-04ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACsClaudiu Beznea1-6/+22
Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain GMAC's MDIO pins should be configured with slew-rate enabled, while the data + signaling pins should be configured with slew-rate disabled when GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets the slew-rate as enabled for all pins. Adapt the device tree to comply with these. Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com
2021-10-04ARM: at91: pm: preload base address of controllers in tlbClaudiu Beznea1-1/+24
In suspend/resume procedure for AT91 architecture different controllers (PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") introduced the access to RAMC PHY controller for SAMA7G5. The access to this controller is done after RAMC ports are closed, thus any TLB walk necessary for RAMC PHY virtual address will fail. In the development branch this was not encountered. However, on current kernel the issue is reproducible. To solve the issue the previous mechanism of pre-loading the TLB with the RAMC PHY virtual address has been used. However, only the addition of this new pre-load breaks the functionality for ARMv5 based devices (SAM9X60). This behavior has been encountered previously while debugging this code and using the same mechanism for pre-loading address for different controllers (e.g. pin controller, the assumption being that other requested translations are replaced from TLB). To solve this new issue the TLB flush + the extension of pre-loading the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The rest of the controllers should have been pre-loaded previously, anyway. Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com
2021-10-04ARM: at91: pm: group constants and addresses loadingClaudiu Beznea1-8/+9
Group constants and addresses loading. This commit prepares the field for the next one. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210930154219.2214051-3-claudiu.beznea@microchip.com
2021-10-04ARM: dts: at91: sama7g5ek: add suspend voltage for ddr3l railClaudiu Beznea1-0/+2
SAMA7G5-EK board has DDR3L type of memory soldered. This needs 1.35V. The 1.35V for DDR3L rail at run-time is selected by the proper configuration on SELV2 pin (for 1.35V it needs to be in high-z state). When suspended the MCP16502 PMIC soldered on SAMA7G5-EK will use different sets of configuration registers to provide proper voltages on its rail. Run-time configuration registers could be configured differently than suspend configuration register for MCP16502 (VSEL2 affects only run-time configuration). In suspend states the DDR3L memory soldered on SAMA7G5-EK switches to self-refresh. Even on self-refresh it needs to be powered by a 1.35V rail. Thus, make sure the PMIC is configured properly when system is suspended. Fixes: 7540629e2fc7 (ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210930154219.2214051-2-claudiu.beznea@microchip.com
2021-10-04s390/pci: fix zpci_zdev_put() on reserveNiklas Schnelle4-15/+45
Since commit 2a671f77ee49 ("s390/pci: fix use after free of zpci_dev") the reference count of a zpci_dev is incremented between pcibios_add_device() and pcibios_release_device() which was supposed to prevent the zpci_dev from being freed while the common PCI code has access to it. It was missed however that the handling of zPCI availability events assumed that once zpci_zdev_put() was called no later availability event would still see the device. With the previously mentioned commit however this assumption no longer holds and we must make sure that we only drop the initial long-lived reference the zPCI subsystem holds exactly once. Do so by introducing a zpci_device_reserved() function that handles when a device is reserved. Here we make sure the zpci_dev will not be considered for further events by removing it from the zpci_list. This also means that the device actually stays in the ZPCI_FN_STATE_RESERVED state between the time we know it has been reserved and the final reference going away. We thus need to consider it a real state instead of just a conceptual state after the removal. The final cleanup of PCI resources, removal from zbus, and destruction of the IOMMU stays in zpci_release_device() to make sure holders of the reference do see valid data until the release. Fixes: 2a671f77ee49 ("s390/pci: fix use after free of zpci_dev") Cc: stable@vger.kernel.org Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2021-10-04bpf, s390: Fix potential memory leak about jit_dataTiezhu Yang1-1/+1
Make sure to free jit_data through kfree() in the error path. Fixes: 1c8f9b91c456 ("bpf: s390: add JIT support for multi-function programs") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2021-10-04ALSA: hda/realtek: Add quirk for Clevo X170KM-GWerner Sembach1-0/+1
This applies a SND_PCI_QUIRK(...) to the Clevo X170KM-G barebone. This fixes the issue of the devices internal Speaker not working. Signed-off-by: Werner Sembach <wse@tuxedocomputers.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20211001133111.428249-3-wse@tuxedocomputers.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
2021-10-04ALSA: hda/realtek: Complete partial device name to avoid ambiguityWerner Sembach1-1/+1
The string "Clevo X170" is not enough to unambiguously identify the correct device. Fixing it so another Clevo barebone name starting with "X170" can be added without causing confusion. Signed-off-by: Werner Sembach <wse@tuxedocomputers.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20211001133111.428249-2-wse@tuxedocomputers.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
2021-10-04arm64: dts: imx8: change the spi-nor txHaibo Chen6-5/+7
Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"), for all PP command, it only support 1-1-1 mode, no matter the tx setting in dts. But after the upper commit, the logic change. It will choose the best mode(fastest mode) which flash device and spi-nor host controller both support. qspi and fspi host controller do not support read 1-4-4 mode. so need to set the tx to 1, let the common code finally select read 1-1-4 mode. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-04ARM: dts: imx: change the spi-nor txHaibo Chen2-3/+3
Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"), for all PP command, it only support 1-1-1 mode, no matter the tx setting in dts. But after the upper commit, the logic change. It will choose the best mode(fastest mode) which flash device and spi-nor host controller both support. Though the spi-nor device on imx6sx-sdb/imx6ul(l/z)-14x14-evk board do not support PP-1-4-4/PP-1-1-4, but if tx is 4 in dts file, it will also impact the read mode selection. For the spi-nor device on the upper mentioned boards, they support read 1-4-4 mode and read 1-1-4 mode according to the device internal sfdp register. But qspi host controller do not support read 1-4-4 mode. so need to set the tx to 1, let the common code finally select read 1-1-4 mode, PP-1-1-1 mode. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 02:10:00 +0300