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2019-08-10pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ↵Nathan Chancellor1-1/+1
ctx parameter clang errors: drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' with an expression of type 'int (const struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' [-Werror,-Wincompatible-pointer-types] .set = aspeed_g6_sig_expr_set, ^~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") changed the set function pointer declaration and the g6 one wasn't updated (I assume because it wasn't merged yet). Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Link: https://github.com/ClangBuiltLinux/linux/issues/632 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20190807003037.48457-1-natechancellor@gmail.com Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-07pinctrl: qcom: Add SC7180 pinctrl driverJitendra Sharma3-0/+1156
Add initial pinctrl driver to support pin configuration with pinctrl framework for SC7180 Signed-off-by: Jitendra Sharma <shajit@codeaurora.org> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> [rnayak: modify to use upstream tile support sort and squash some functions] Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20190806060536.18094-2-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-07dt-bindings: pinctrl: qcom: Add SC7180 pinctrl bindingJitendra Sharma1-0/+186
Add the binding for the TLMM pinctrl block found in the SC7180 platform Signed-off-by: Jitendra Sharma <shajit@codeaurora.org> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> [rnayak: Fix some copy-paste issues, sort and fix functions] Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20190806060536.18094-1-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06pinctrl: spear: spear: Add of_node_put() before returnNishka Dasgupta1-2/+6
Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return in two places. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20190804154948.4584-1-nishkadg.linux@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06pinctrl: freescale: mxs: Add of_node_put() before returnNishka Dasgupta1-3/+9
Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return in three places. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Link: https://lore.kernel.org/r/20190804160420.5309-1-nishkadg.linux@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06pinctrl: nomadik: abx500: Add of_node_put() before returnNishka Dasgupta1-0/+1
Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Link: https://lore.kernel.org/r/20190804155154.4916-1-nishkadg.linux@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06pinctrl: nomadik: nomadik: Add of_node_put() before returnNishka Dasgupta1-0/+1
Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Link: https://lore.kernel.org/r/20190804155117.4753-1-nishkadg.linux@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06pinctrl: falcon: Add of_node_put() before returnNishka Dasgupta1-1/+4
Each iteration of for_each_compatible_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return in two places. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Link: https://lore.kernel.org/r/20190804152745.2231-1-nishkadg.linux@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: xway: Use devm_kasprintf() instead of fixed buffer formattingGeert Uytterhoeven1-3/+1
Improve readability and maintainability by replacing a hardcoded string allocation and formatting by the use of the devm_kasprintf() helper. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190731132917.17607-4-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: lantiq: Use kasprintf() instead of fixed buffer formattingGeert Uytterhoeven1-5/+1
Improve readability and maintainability by replacing a hardcoded string allocation and formatting by the use of the kasprintf() helper. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190731132917.17607-3-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: devicetree: Use strlen() instead of hardcoded numberGeert Uytterhoeven1-4/+2
Improve readability by replacing a hardcoded number requiring a comment by strlen(). Gcc is smart enough to evaluate the length of a constant string at compile-time. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190731132917.17607-2-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: Remove dev_err() usage after platform_get_irq()Stephen Boyd6-19/+6
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-34-swboyd@chromium.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: uniphier: Fix Pro5 SD pin-mux settingKunihiko Hayashi1-1/+1
SD uses the following pins starting from 247: SDCD, SDWP, SDVOLC, SDCLK, SDCMD, SDDAT{0,1,2,3} Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Link: https://lore.kernel.org/r/1564465410-9165-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: uniphier: Add Pro5 PCIe pin-mux settingsKunihiko Hayashi1-0/+5
Pro5 PCIe interface uses the following pins: XPERST, XPEWAKE, XPECLKRQ Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1564465410-9165-5-git-send-email-hayashi.kunihiko@socionext.com Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: uniphier: Add 5th LD20 MPEG2-TS input pin-mux settingKunihiko Hayashi1-0/+5
The 5th serial TS interface uses the following pins: hscin4_s: PCA[11-14] Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Link: https://lore.kernel.org/r/1564465410-9165-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: uniphier: Add another audio I/O pin-mux settings for LD20Kunihiko Hayashi1-1/+4
This adds support for pinmux settings of aout1b group. This group includes audio I/O signals derived from xirq pins, and it is equivalent to "aout1" in functionality. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1564465410-9165-3-git-send-email-hayashi.kunihiko@socionext.com Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: uniphier: Separate modem group from UART ctsrts groupKunihiko Hayashi9-27/+63
It depends on the board implementation whether to have each pins of CTS/RTS, and others for modem. So it is necessary to divide current uart_ctsrts group into uart_ctsrts and uart_modem groups. Since the number of implemented pins for modem differs depending on SoC, each uart_modem group also has a different number of pins. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1564465410-9165-2-git-send-email-hayashi.kunihiko@socionext.com Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: meson-g12a: add pwm_a on GPIOE_2 pinmuxNeil Armstrong1-0/+9
Add the missing pinmux for the pwm_a function on the GPIOE_2 pin. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20190729125838.6498-1-narmstrong@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05dt-bindings: aspeed: Remove mention of deprecated compatiblesAndrew Jeffery4-11/+2
Guide readers away from using the aspeed,g[45].* compatible patterns. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724081313.12934-4-andrew@aj.id.au Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: aspeed: Document existence of deprecated compatiblesAndrew Jeffery2-0/+8
Otherwise they look odd in the face of not being listed in the bindings documents. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724081313.12934-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: aspeed: Add AST2600 pinmux supportAndrew Jeffery3-0/+2404
The AST2600 pinmux is fairly similar to the previous generations of ASPEED BMC SoCs in terms of architecture, though differ in some of the design details. The complexity of the pin expressions is largely reduced (e.g. there are no-longer signals with multiple expressions muxing them to the associated pin), and there are now signals and buses with multiple pin groups. The driver implements pinmux support for all 244 GPIO-capable pins plus a further four pins that are not GPIO capable but which expose multiple signals. pinconf will be implemented in a follow-up patch. The implementation has been smoke-tested under qemu, and run on hardware by ASPEED. Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: aspeed: Add SIG_DESC_CLEAR() helperAndrew Jeffery1-0/+1
The complement of SIG_DESC_SET(). Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: aspeed: Add multiple pin group support for functionsAndrew Jeffery3-1489/+1789
The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: aspeed: Add PIN_DECL_3() helperAndrew Jeffery1-32/+40
This case is common in the AST2600, so add to the collection. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-4-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: aspeed: Rename pin declaration macrosAndrew Jeffery3-405/+405
Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05dt-bindings: pinctrl: aspeed: Document AST2600 pinmuxAndrew Jeffery1-0/+115
The AST260 differs from the 2400 and 2500 in that it supports multiple groups for a subset of functions. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-2-andrew@aj.id.au Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: sunxi: v3s: introduce support for V3Icenowy Zheng2-5/+262
Introduce the GPIO pins that is only available on V3 (not on V3s) to the V3s pinctrl driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://lore.kernel.org/r/20190728031227.49140-2-icenowy@aosc.io Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: qcom: spmi-gpio: Mark expected switch fall-throughAnders Roxell1-0/+2
When fall-through warnings was enabled by default the following warnings was starting to show up: ../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c: In function ‘pmic_gpio_populate’: ../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:815:20: warning: this statement may fall through [-Wimplicit-fallthrough=] pad->have_buffer = true; ~~~~~~~~~~~~~~~~~^~~~~~ ../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:816:2: note: here case PMIC_GPIO_SUBTYPE_GPIOC_4CH: ^~~~ ../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:820:20: warning: this statement may fall through [-Wimplicit-fallthrough=] pad->have_buffer = true; ~~~~~~~~~~~~~~~~~^~~~~~ ../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:821:2: note: here case PMIC_GPIO_SUBTYPE_GPIOC_8CH: ^~~~ Rework so that the compiler doesn't warn about fall-through. Fixes: d93512ef0f0e ("Makefile: Globally enable fall-through warning") Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Link: https://lore.kernel.org/r/20190726112816.19723-1-anders.roxell@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: rockchip: Mark expected switch fall-throughAnders Roxell1-0/+1
When fall-through warnings was enabled by default the following warning was starting to show up: ../drivers/pinctrl/pinctrl-rockchip.c: In function ‘rockchip_gpio_set_config’: ../drivers/pinctrl/pinctrl-rockchip.c:2783:3: warning: this statement may fall through [-Wimplicit-fallthrough=] rockchip_gpio_set_debounce(gc, offset, true); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/pinctrl/pinctrl-rockchip.c:2795:2: note: here default: ^~~~~~~ Rework so that the compiler doesn't warn about fall-through. Add 'return -ENOTSUPP;' to match the comment. Fixes: d93512ef0f0e ("Makefile: Globally enable fall-through warning") Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Link: https://lore.kernel.org/r/20190726112812.19665-1-anders.roxell@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: oxnas: remove set but not used variable 'arg'YueHaibing1-4/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/pinctrl/pinctrl-oxnas.c: In function oxnas_ox810se_pinconf_set: drivers/pinctrl/pinctrl-oxnas.c:905:6: warning: variable arg set but not used [-Wunused-but-set-variable] drivers/pinctrl/pinctrl-oxnas.c: In function oxnas_ox820_pinconf_set: drivers/pinctrl/pinctrl-oxnas.c:944:6: warning: variable arg set but not used [-Wunused-but-set-variable] It is never used since commit 4b0c0c25fa79 ("pinctrl: oxnas: Add support for OX820"), so can be removed. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190725142419.29892-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: stmfx: update pinconf settingsAlexandre Torgue1-12/+12
According to the following tab (coming from STMFX datasheet), updates have to done in stmfx_pinconf_set function: -"type" has to be set when "bias" is configured as "pull-up or pull-down" -PIN_CONFIG_DRIVE_PUSH_PULL should only be used when gpio is configured as output. There is so no need to check direction. DIR | TYPE | PUPD | MFX GPIO configuration ----|------|------|--------------------------------------------------- 1 | 1 | 1 | OUTPUT open drain with internal pull-up resistor ----|------|------|--------------------------------------------------- 1 | 1 | 0 | OUTPUT open drain with internal pull-down resistor ----|------|------|--------------------------------------------------- 1 | 0 | 0/1 | OUTPUT push pull no pull ----|------|------|--------------------------------------------------- 0 | 1 | 1 | INPUT with internal pull-up resistor ----|------|------|--------------------------------------------------- 0 | 1 | 0 | INPUT with internal pull-down resistor ----|------|------|--------------------------------------------------- 0 | 0 | 1 | INPUT floating ----|------|------|--------------------------------------------------- 0 | 0 | 0 | analog (GPIO not used, default setting) Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/1564053416-32192-1-git-send-email-amelie.delaunay@st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: sprd: Combine the condition of MISC_PIN and COMMON_PINBaolin Wang1-17/+2
Since the follow-up pin design on Spreadtrum platform has some changes, some configuration of MISC_PIN moved to COMMON_PIN. To support current pin design and keep backward compatibility, we should combine the condition of MISC_PIN and COMMON_PIN to configure an individual pin. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/17af5e761e0515d288a7ea4078ac9aa4a82a7a4e.1564048446.git.baolin.wang@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: sprd: Change to use devm_platform_ioremap_resource()Baolin Wang1-3/+1
The devm_platform_ioremap_resource() function wraps platform_get_resource() and devm_ioremap_resource() in a single helper, thus use it to simplify the code. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/ff410d312ed0047b5a36e5113daf7df78bcf1aa8.1564048446.git.baolin.wang@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: qdf2xxx: Switch to use device_property_count_uXX()Andy Shevchenko1-1/+1
Use use device_property_count_uXX() directly, that makes code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190723192738.68486-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: msm: Switch to use device_property_count_uXX()Andy Shevchenko1-3/+2
Use use device_property_count_uXX() directly, that makes code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190723192738.68486-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: madera: Add configuration for Cirrus Logic CS47L92Charles Keepax5-0/+63
This adds the pinctrl configuration for the CS47L92 codec to the madera pinctrl driver. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20190722091015.20884-3-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: madera: Add configuration for Cirrus Logic CS47L15Richard Fitzgerald5-0/+51
This adds the pinctrl configuration for the CS47L15 codec to the madera pinctrl driver. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20190722091015.20884-2-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: madera: Use local copy of pdataCharles Keepax1-2/+2
A local copy of the pdata exists and it should be used rather than pulling a fresh copy. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20190722091015.20884-1-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: bcm2835: Add support for BCM2711 pull-up functionalityStefan Wahren1-5/+100
The BCM2711 has a new way of selecting the pull-up/pull-down setting for a GPIO pin. The registers used for the BCM2835, GP_PUD and GP_PUDCLKn0, are no longer connected. A new set of registers, GP_GPIO_PUP_PDN_CNTRL_REGx must be used. This commit will add a new compatible string "brcm,bcm2711-gpio" and the kernel driver will use it to select which method is used to select pull-up/pull-down. This patch based on a patch by Al Cooper which was intended for the BCM7211. This is a bugfixed and improved version. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/1563776607-8368-3-git-send-email-wahrenst@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: bcm2835: Add brcm,bcm2711 compatibleStefan Wahren1-0/+1
Add a new compatible for the BCM2711. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/1563776607-8368-2-git-send-email-wahrenst@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: tegra210: Add Tegra210 pinctrl pm opsSowjanya Komatineni1-0/+1
This patch adds suspend and resume functionality to Tegra210 pinctrl. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1564607463-28802-3-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: tegra: Add suspend and resume supportSowjanya Komatineni2-0/+62
This patch adds support for Tegra pinctrl driver suspend and resume. During suspend, context of all pinctrl registers are stored and on resume they are all restored to have all the pinmux and pad configuration for normal operation. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1564607463-28802-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05pinctrl: pinctrl-single: add header include guardMasahiro Yamada1-0/+6
Add a header include guard just in case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Link: https://lore.kernel.org/r/20190720115858.7015-1-yamada.masahiro@socionext.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-03pinctrl: sprd: Fix platform_no_drv_owner.cocci warningsYueHaibing1-1/+0
Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190719032414.85369-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-30pinctrl: Ingenic: Add pinctrl driver for X1500.Zhou Yanjie1-1/+117
Add support for probing the pinctrl-ingenic driver on the X1500 Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-7-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-30dt-bindings: pinctrl: Add X1500 bindings.Zhou Yanjie1-0/+1
Add the pinctrl bindings for the X1500 Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-6-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-30pinctrl: Ingenic: Add pinctrl driver for X1000 and X1000E.Zhou Yanjie1-11/+296
Add support for probing the pinctrl-ingenic driver on the X1000 Soc and the X1000E Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-5-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-30dt-bindings: pinctrl: Add X1000 and X1000E bindings.Zhou Yanjie1-5/+8
Add the pinctrl bindings for the X1000 Soc and the X1000E Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-4-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-30pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B.Zhou Yanjie1-31/+305
Add support for probing the pinctrl-ingenic driver on the JZ4760 Soc and the JZ4760B Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-3-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-30dt-bindings: pinctrl: Add JZ4760 and JZ4760B bindings.Zhou Yanjie1-2/+5
Add the pinctrl bindings for the JZ4760 Soc and the JZ4760B Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-2-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 16:04:42 +0300