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2025-01-21Merge branches 'clk-airoha', 'clk-rockchip', 'clk-stm', 'clk-thead' and ↵Stephen Boyd18-241/+739
'clk-bcm' into clk-next * clk-airoha: clk: en7523: Add clock for eMMC for EN7581 dt-bindings: clock: add ID for eMMC for EN7581 dt-bindings: clock: drop NUM_CLOCKS define for EN7581 clk: en7523: Rework clock handling for different clock numbers clk: en7523: Initialize num before accessing hws in en7523_register_clocks() clk: en7523: Fix wrong BUS clock for EN7581 clk: amlogic: axg-audio: revert reset implementation Revert "clk: Fix invalid execution of clk_set_rate" * clk-rockchip: clk: rockchip: rk3588: make refclko25m_ethX critical clk: rockchip: rk3588: drop RK3588_LINKED_CLK clk: rockchip: implement linked gate clock support clk: rockchip: expose rockchip_clk_set_lookup clk: rockchip: rk3588: register GATE_LINK later clk: rockchip: support clocks registered late * clk-stm: clk: stm32f4: support spread spectrum clock generation clk: stm32f4: use FIELD helpers to access the PLLCFGR fields dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking dt-bindings: clock: convert stm32 rcc bindings to json-schema * clk-thead: clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot clk: thead: Fix clk gate registration to pass flags * clk-bcm: clk: bcm: rpi: Add disp clock clk: bcm: rpi: Create helper to retrieve private data clk: bcm: rpi: Enable minimize for all firmware clocks clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks clk: bcm: rpi: Add ISP to exported clocks
2025-01-21Merge branches 'clk-microchip', 'clk-xilinx', 'clk-allwinner', 'clk-imx' and ↵Stephen Boyd78-267/+12841
'clk-qcom' into clk-next * clk-microchip: clk: at91: sama7d65: add sama7d65 pmc driver dt-bindings: clock: Add SAMA7D65 PMC compatible string dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65 clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks dt-bindings: clk: at91: Add clock IDs for the slow clock controller * clk-xilinx: clk: clocking-wizard: calculate dividers fractional parts dt-bindings: clock: xilinx: Add reset GPIO for VCU dt-bindings: clock: xilinx: Convert VCU bindings to dtschema * clk-allwinner: clk: sunxi-ng: h616: Reparent CPU clock during frequency changes clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI * clk-imx: clk: imx: Apply some clks only for i.MX93 arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock clk: imx93: Add IMX93_CLK_SPDIF_IPG clock dt-bindings: clock: imx93: Add SPDIF IPG clk clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x clk: imx8mp: Fix clkout1/2 support * clk-qcom: (63 commits) clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC dt-bindings: clock: move qcom,x1e80100-camcc to its own file clk: qcom: smd-rpm: Add clocks for MSM8940 dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible clk: qcom: smd-rpm: Add clocks for MSM8937 dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks dt-bindings: interconnect: Add Qualcomm IPQ5424 support clk: qcom: Add SM6115 LPASSCC dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs clk: qcom: gcc-sdm845: Add general purpose clock ops clk: qcom: clk-rcg2: split __clk_rcg2_configure function clk: qcom: clk-rcg2: document calc_rate function clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC clk: qcom: ipq5424: add gcc_xo_clk dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro clk: qcom: ipq5424: remove apss_dbg clock dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible ...
2025-01-21Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' ↵Stephen Boyd30-103/+2419
and 'clk-socfpga' into clk-next - Support for 5L35023 variant of Versa 3 clock generator * clk-cleanup: clk: analogbits: Fix incorrect calculation of vco rate delta clk: Use str_enable_disable-like helpers clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data() clk: starfive: Make _clk_get become a common helper function clk: ep93xx: make const read-only arrays static clk: lmk04832: make read-only const arrays static clk: ti: use kcalloc() instead of kzalloc() dt-bindings: clock: st,stm32mp1-rcc: complete the reference path dt-bindings: clock: st,stm32mp1-rcc: fix reference paths dt-bindings: clock: ti: Convert composite.txt to json-schema dt-bindings: clock: ti: Convert gate.txt to json-schema clk: Drop obsolete devm_clk_bulk_get_all_enable() helper PCI: exynos: Switch to devm_clk_bulk_get_all_enabled() soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled() clk: davinci: remove platform data struct clk: fix an OF node reference leak in of_clk_get_parent_name() clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check * clk-renesas: (24 commits) dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard clk: renesas: r9a09g057: Add clock and reset entries for GIC clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r8a779g0: Add VSPX clocks clk: renesas: r8a779g0: Add FCPVX clocks clk: renesas: r9a09g047: Add I2C clocks/resets clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: rzv2h: Add MSTOP support dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants clk: versaclock3: Add support for the 5L35023 variant dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator clk: versaclock3: Prepare for the addition of 5L35023 device clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP clk: renesas: r8a779h0: Add display clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a06g032: Use BIT macro consistently ... * clk-mediatek: clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883 clk: mediatek: mt2701-img: add missing dummy clk clk: mediatek: mt2701-mm: add missing dummy clk clk: mediatek: mt2701-bdp: add missing dummy clk clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe * clk-samsung: clk: samsung: Introduce Exynos990 clock controller driver clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x} dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings * clk-socfpga: clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
2025-01-17clk: analogbits: Fix incorrect calculation of vco rate deltaBo Gan1-1/+1
In wrpll_configure_for_rate() we try to determine the best PLL configuration for a target rate. However, in the loop where we try values of R, we should compare the derived `vco` with `target_vco_rate`. However, we were in fact comparing it with `target_rate`, which is actually after Q shift. This is incorrect, and sometimes can result in suboptimal clock rates. Fix it. Fixes: 7b9487a9a5c4 ("clk: analogbits: add Wide-Range PLL library") Signed-off-by: Bo Gan <ganboing@gmail.com> Link: https://lore.kernel.org/r/20240830061639.2316-1-ganboing@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-17clk: bcm: rpi: Add disp clockMaxime Ripard2-0/+6
BCM2712 has an extra clock exposed by the firmware called DISP, and used by (at least) the HVS. Let's add it to the list of clocks to register in Linux. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-5-10bc92ffbf41@raspberrypi.com Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-17clk: bcm: rpi: Create helper to retrieve private dataMaxime Ripard1-8/+10
The RaspberryPi firmware clocks driver uses in several instances a container_of to retrieve the struct raspberrypi_clk_data from a pointer to struct clk_hw. Let's create a small function to avoid duplicating it all over the place. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-4-10bc92ffbf41@raspberrypi.com Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-17clk: bcm: rpi: Enable minimize for all firmware clocksDom Cobley1-0/+6
There isn't a reason not to minimise the clocks, and it saves some power. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dom Cobley <popcornmix@gmail.com> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-3-10bc92ffbf41@raspberrypi.com Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-17clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocksDom Cobley1-1/+0
For performance/power it is beneficial to adjust gpu clocks with arm clock. This is how the downstream cpufreq driver works Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dom Cobley <popcornmix@gmail.com> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-2-10bc92ffbf41@raspberrypi.com Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-17clk: bcm: rpi: Add ISP to exported clocksDom Cobley1-0/+3
The ISP clock can be controlled by the driver, so register it with the clock subsystem. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dom Cobley <popcornmix@gmail.com> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-1-10bc92ffbf41@raspberrypi.com Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-16clk: stm32f4: support spread spectrum clock generationDario Binacchi1-3/+140
Support spread spectrum clock generation for the main PLL, the only one for which this functionality is available. Tested on the STM32F469I-DISCO board. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250114182021.670435-5-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-16clk: stm32f4: use FIELD helpers to access the PLLCFGR fieldsDario Binacchi1-3/+9
Use GENMASK() along with FIELD_GET() and FIELD_PREP() helpers to access the PLLCFGR fields instead of manually masking and shifting. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250114182021.670435-4-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-16dt-bindings: clock: st,stm32-rcc: support spread spectrum clockingDario Binacchi1-0/+36
The addition of DT bindings for enabling and tuning spread spectrum clocking generation is available only for the main PLL of stm32f{4,7} platforms. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250114182021.670435-3-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-16dt-bindings: clock: convert stm32 rcc bindings to json-schemaDario Binacchi4-140/+110
The patch converts st,stm32-rcc.txt to the JSON schema, but it does more than that. The old bindings, in fact, only covered the stm32f{4,7} platforms and not the stm32h7. Therefore, to avoid patch submission tests failing, it was necessary to add the corresponding compatible (i. e. st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead of the 2 required for the stm32f{4,7} platforms. Additionally, the old bindings made no mention of the st,syscfg property, which is used by both the stm32f{4,7} and the stm32h7 platforms. The patch also fixes the files referencing to the old st,stm32-rcc.txt. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-15clk: Use str_enable_disable-like helpersKrzysztof Kozlowski4-6/+9
Replace ternary (condition ? "enable" : "disable") syntax with helpers from string_choices.h because: 1. Simple function call with one argument is easier to read. Ternary operator has three arguments and with wrapping might lead to quite long code. 2. Is slightly shorter thus also easier to read. 3. It brings uniformity in the text - same string. 4. Allows deduping by the linker, which results in a smaller binary file. Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250114190612.846696-1-krzysztof.kozlowski@linaro.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data()Binbin Zhou1-2/+2
Since commit 706ae6446494 ("clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data()"), we can use the devm_clk_hw_register_fixed_rate_parent_data() helper and from then on there is no need to manually unregister the fixed rate hw. Since clk_hw_unregister_fixed_rate() was not called before, we also fix the memory leak that was present. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/8733a7485619bdb791de25201a3d7984d1849c9f.1736856470.git.zhoubinbin@loongson.cn Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: starfive: Make _clk_get become a common helper functionChanghuang Liang8-73/+27
Introduce num_reg to store the number of clocks, this helps to make _clk_get become a common helper function which called jh71x0_clk_get(). With this, it helps to simplify the code and extend the code in the future. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20250114081300.36600-1-changhuang.liang@starfivetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14Merge tag 'v6.14-rockchip-clk1' of ↵Stephen Boyd5-60/+288
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Real handling of the linked clocks (clocks of the interconnect port a peripheral is connected to) on rk3588 using pm-clocks, allowing us to stop marking them as critical and one more rk3588 critical clock, that the kernel cannot handle otherwise right now. * tag 'v6.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3588: make refclko25m_ethX critical clk: rockchip: rk3588: drop RK3588_LINKED_CLK clk: rockchip: implement linked gate clock support clk: rockchip: expose rockchip_clk_set_lookup clk: rockchip: rk3588: register GATE_LINK later clk: rockchip: support clocks registered late
2025-01-14clk: en7523: Add clock for eMMC for EN7581Christian Marangi1-0/+10
Add clock for eMMC for EN7581. This is used to give info of the current eMMC source clock and to switch it from 200MHz or 150MHz. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20250113231030.6735-5-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14dt-bindings: clock: add ID for eMMC for EN7581Christian Marangi1-0/+2
Add ID for eMMC for EN7581. This is to control clock selection of eMMC between 200MHz and 150MHz. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250113231030.6735-4-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14dt-bindings: clock: drop NUM_CLOCKS define for EN7581Christian Marangi1-2/+0
Drop NUM_CLOCKS define for EN7581 include. This is not a binding and should not be placed here. Value is derived internally in the user driver. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250113231030.6735-3-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: en7523: Rework clock handling for different clock numbersChristian Marangi1-6/+8
Airoha EN7581 SoC have additional clock compared to EN7523 but current driver permits to only support up to EN7523 clock numbers. To handle this, rework the clock handling and permit to declare the clocks number in match_data and alloca clk_data based on the compatible match_data. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20250113231030.6735-2-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocksDrew Fustini1-1/+1
cpu2vp_clk is a gate but was mistakenly in th1520_div_clks[] instead of th1520_gate_clks[]. Fixes: ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks") Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> Link: https://lore.kernel.org/r/20241228034802.1573554-1-dfustini@tenstorrent.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 bootDrew Fustini1-4/+4
Add the CLK_IGNORE_UNUSED flag to apb_pclk, cpu2peri_x2h_clk, perisys_apb2_hclk and perisys_apb3_hclk. Without this flag, the boot hangs after "clk: Disabling unused clocks" unless clk_ignore_unused is in the kernel cmdline. Fixes: ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks") Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> Link: https://lore.kernel.org/r/20250113-th1520-clk_ignore_unused-v1-2-0b08fb813438@tenstorrent.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: thead: Fix clk gate registration to pass flagsDrew Fustini1-1/+2
Modify the call to devm_clk_hw_register_gate_parent_data() to actually pass the clk flags from hw.init instead of just 0. This is necessary to allow individual clk gates to specify their own clk flags. Fixes: ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks") Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> Link: https://lore.kernel.org/r/20250113-th1520-clk_ignore_unused-v1-1-0b08fb813438@tenstorrent.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883Sergio Paracuellos1-1/+0
Ralink SoC RT3883 has already 'xtal' defined as a base clock so there is no need to redefine it again in fixed clocks section. Hence, remove the duplicate one from there. Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20250108093636.265033-1-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: ep93xx: make const read-only arrays staticColin Ian King1-3/+3
Don't populate the const read-only arrays on the stack at run time, instead make them static. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20250112213947.8524-1-colin.i.king@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-14clk: lmk04832: make read-only const arrays staticColin Ian King1-2/+2
Don't populate the read-only const arrays pll2_p and dclk_div_adj on the stack at run time, instead make them static. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20240912134707.590224-1-colin.i.king@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-13clk: sunxi-ng: h616: Reparent CPU clock during frequency changesAndre Przywara1-2/+26
The H616 user manual recommends to re-parent the CPU clock during frequency changes of the PLL, and recommends PLL_PERI0(1X), which runs at 600 MHz. Also it asks to disable and then re-enable the PLL lock bit, after the factor changes have been applied. Add clock notifiers for the PLL and the CPU mux clock, using the existing notifier callbacks, and tell them to use mux 4 (the PLL_PERI0(1X) source), and bit 29 (the LOCK_ENABLE) bit. The existing code already follows the correct algorithms. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20241025105620.1891596-1-andre.przywara@arm.com Tested-by: Evgeny Boger <boger@wirenboard.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-13Merge tag 'qcom-clk-for-6.14' of ↵Stephen Boyd57-145/+11254
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - Support for various Qualcomm clk controllers: IPQ CMN PLL, SM6115 LPASS, SM750 global, tcsr, rpmh, and display. X Plus GPU and global. QCS615 rpmh and MSM8937 and MSM8940 RPM. - Support for Qualcomm Pongo and Taycan Alpha PLLs - Describe Qualcomm X Elite Titan GDSC relationships - Mark Qualcomm SM8550 and SM8650 PCIe GDSCs and X Elite USB GDSC as retention/on - Allow Qualcomm SDM845 general purpose clk to have arbitrary frequencies - Add Qualcomm IPQ5424 NoC-related interconnect clks * tag 'qcom-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (63 commits) clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC dt-bindings: clock: move qcom,x1e80100-camcc to its own file clk: qcom: smd-rpm: Add clocks for MSM8940 dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible clk: qcom: smd-rpm: Add clocks for MSM8937 dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks dt-bindings: interconnect: Add Qualcomm IPQ5424 support clk: qcom: Add SM6115 LPASSCC dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs clk: qcom: gcc-sdm845: Add general purpose clock ops clk: qcom: clk-rcg2: split __clk_rcg2_configure function clk: qcom: clk-rcg2: document calc_rate function clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC clk: qcom: ipq5424: add gcc_xo_clk dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro clk: qcom: ipq5424: remove apss_dbg clock dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible ...
2025-01-09clk: rockchip: rk3588: make refclko25m_ethX criticalHeiko Stuebner1-2/+2
Ethernet phys normally need a 25MHz refclk input. On a lot of boards this is done with a dedicated 25MHz crystal. But the rk3588 CRU also provides a means for that via the refclko25m_ethX clock outputs that can be used for that function. The mdio bus normally probes devices on the bus at runtime, by reading specific phy registers. This requires the phy to be running and thus also being supplied by its reference clock. While there exist the possibility and dt-binding to declare these input clocks for each phy in the phy-dt-node, this is only relevant _after_ the phy has been detected and during the drivers probe-run. This results in a chicken-and-egg-problem. The refclks in the CRU are running on boot of course, but phy-probing can very well happen after clk_disable_unused has run. In the past I tried to make clock-handling part of the mdio bus code [0] but that wasn't very well received, due to it being specific to OF and clocks with the consensus being that resources needed for detection need to be enabled before. So to make probing ethernet phys using the internal refclks possible, make those 2 clocks critical. [0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/ Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: rk3588: drop RK3588_LINKED_CLKSebastian Reichel1-15/+12
With the proper GATE_LINK support, we no longer need to keep the linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL flag for them. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: implement linked gate clock supportSebastian Reichel5-21/+165
Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These clock gates will only have a running output clock when all of the following conditions are met: 1. the parent clock is enabled 2. the enable bit is set correctly 3. the linked clock is enabled To handle them this code registers them as a normal gate type clock, which takes care of condition 1 + 2. The linked clock is handled by using runtime PM clocks. Handling it via runtime PM requires setting up a struct device for each of these clocks with a driver attached to use the correct runtime PM operations. Thus the complete handling of these clocks has been moved into its own driver. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: expose rockchip_clk_set_lookupSebastian Reichel2-10/+16
Move rockchip_clk_add_lookup to clk.h, so that it can be used by sub-devices with their own driver. These might also have to do a lookup, so rename the function to rockchip_clk_set_lookup and add a matching rockchip_clk_get_lookup. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-4-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: rk3588: register GATE_LINK laterSebastian Reichel1-8/+58
The proper GATE_LINK implementation will use runtime PM to handle the linked gate clocks, which requires device context. Currently all clocks are registered early via CLK_OF_DECLARE, which is before the kernel knows about devices. Moving the full clocks registration to the probe routine does not work, since the clocks needed for timers must be registered early. To work around this issue, most of the clock tree is registered early, but GATE_LINK clocks are handled in the probe routine. Since the resets are not needed early either, they have also been moved to the probe routine. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: support clocks registered lateSebastian Reichel2-4/+35
When some clocks are registered late and some clocks are registered early we need to make sure the late registered clocks report probe defer until the final registration has happened. But we do not want to keep reporting probe defer after the late registration has happened. Also not all Rockchip SoCs have late registered clocks and may not need to report probe defer at all. This restructures code a bit, so that there is a new function rockchip_clk_init_early(), which should be used for initializing the CRU structure on SoCs making use of late initialization in addition to the early init. These platforms should call rockchip_clk_finalize() once all clocks have been registered. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> [added EXPORT_SYMBOL_GPL(rockchip_clk_finalize) to match the early function] Link: https://lore.kernel.org/r/20241211165957.94922-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08Merge tag 'clk-imx-6.14' of ↵Stephen Boyd5-18/+24
git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Fix the i.MX8MP clkout1/2 support by using sys_plln_out instead of sys_plln as parents - Add 208 MHz and 416 MHz entries to the PLL1416x - Fix the i.MX93 provider by adding the SPDIF IPG clock - Fix the i.MX93 xcvr DT node clocks by using SPDIF IRP clock instead of BUS_WAKEUP - Filter out LVDS, MIPI DSI, PXP, FLEXIO and MU clocks to i.MX93 only * tag 'clk-imx-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx: Apply some clks only for i.MX93 arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock clk: imx93: Add IMX93_CLK_SPDIF_IPG clock dt-bindings: clock: imx93: Add SPDIF IPG clk clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x clk: imx8mp: Fix clkout1/2 support
2025-01-08Merge tag 'sunxi-clk-for-6.14' of ↵Stephen Boyd3-11/+6
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Chen-Yu Tsai: Instead of forcing a particular clock parent for TCON0 on the A64, the decision is left to the device tree. Which clock parent gets assigned depends on which display output is used. If the wrong parent is assigned, the display doesn't work. Patches include adding the clock parents to the DT binding (which is shared with the DT tree), removing the now redundant macros from the clock driver, and stop forcing a particular clock parent in the driver. * tag 'sunxi-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
2025-01-08clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCCLukas Bulwahn1-1/+1
Commit 99c21c7ca642 ("clk: qcom: Add X1P42100 GPUCC driver") adds the config definition CLK_X1P42100_GPUCC. This config definition selects the non-existing config CLK_X1E8010_GCC. Note that the config for the X1E80100 Global Clock Controller is CLK_X1E80100_GCC. Assuming this was just a minor typo in the number, i.e., 8010 instead of 80100, change the definition to select the existing config CLK_X1E80100_GCC, similarly to the definitions for three configs CLK_X1E80100_{CAMCC,DISPCC,GPUCC}. Fixes: 99c21c7ca642 ("clk: qcom: Add X1P42100 GPUCC driver") Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com> Link: https://lore.kernel.org/r/20250107104728.23098-1-lukas.bulwahn@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08dt-bindings: clock: move qcom,x1e80100-camcc to its own fileBryan O'Donoghue2-2/+74
Add an x1e80100 camcc binding. x1e80100 has two power-domain parents unlike other similar camcc controllers. Differentiate the new structure into a unique camcc definition. Other similar camcc controller setups can then be easily added to this one. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-2-cb66d55d20cc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08clk: qcom: smd-rpm: Add clocks for MSM8940Daniil Titov1-0/+29
MSM8940 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20241231-rpmcc-v1-4-1212df9b2042@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatibleDaniil Titov1-0/+2
Document the qcom,rpmcc-msm8940 compatible. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20241231-rpmcc-v1-3-1212df9b2042@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08clk: qcom: smd-rpm: Add clocks for MSM8937Daniil Titov1-0/+27
MSM8937 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3 and IPA_CLK. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20241231-rpmcc-v1-2-1212df9b2042@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatibleDaniil Titov1-0/+2
Document the qcom,rpmcc-msm8937 compatible. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20241231-rpmcc-v1-1-1212df9b2042@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocksVaradarajan Narayanan1-0/+19
Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241213105808.674620-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08dt-bindings: interconnect: Add Qualcomm IPQ5424 supportVaradarajan Narayanan1-0/+24
Add master/slave ids for Qualcomm IPQ5424 Network-On-Chip interfaces. This will be used by the gcc-ipq5424 driver for providing interconnect services using the icc-clk framework. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213105808.674620-1-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08clk: qcom: Add SM6115 LPASSCCKonrad Dybcio3-0/+95
SM6115 (and its derivatives or similar SoCs) has an LPASS clock controller block which provides audio-related resets. Add the required code to support them. [alexey.klimov] fixed compilation errors after rebase, slightly changed the commit message Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241212002551.2902954-3-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controllerKonrad Dybcio2-0/+61
SM6115 (and its derivatives or similar SoCs) has an LPASS clock controller block which provides audio-related resets. Add bindings for it. Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [alexey.klimov slightly changed the commit message] Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241212002551.2902954-2-alexey.klimov@linaro.org [bjorn: Adjusted Konrad's address] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPsAmit Pundir1-16/+16
Similar to the earlier fixes meant for sm8x50 and x1e platforms, we have to stop using the shared clk ops for sdm845 QUPs as well. As Stephen Boyd pointed out in earlier fixes, there wasn't a problem to mark QUP clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes and we see garbage on the serial console until the driver can probe and actually set a proper frequency. This patch reverts the QUP clk sharing ops part of commit 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845"), so that the QUPs on sdm845 don't get parked during clk registration and break UART operations. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Link: https://lore.kernel.org/r/20241209174912.2526928-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07clk: clocking-wizard: calculate dividers fractional partsShubhrajyoti Datta1-52/+69
Calculate dividers fractional parts to optimally modulate output frequency. Clocking wizard supports having multiplier m and divisors d and o. Currently the fractional parts of m and o are not utilised. For the pixel clock usecases a higher accuracy is needed.. Adding support for m and o to have fractional values. Co-developed-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Signed-off-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Tested-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Link: https://lore.kernel.org/r/20250106082937.29555-1-shubhrajyoti.datta@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-07dt-bindings: clock: xilinx: Add reset GPIO for VCURohit Visavalia1-0/+4
It is marked as optional as some of the ZynqMP designs are having vcu_reset (reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by axi_gpio or PS GPIO so there will be no GPIO entry. Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com> Link: https://lore.kernel.org/r/20250107044038.100945-3-rohit.visavalia@amd.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-04 01:47:55 +0300