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2022-04-04ARM: dts: ux500: Add Codina TMO device treeLinus Walleij3-2/+788
This adds a device tree for "Codina TMO" also known as Samsung Galaxy Exhibit or Samsung SGH-T599. It is quite different from the vanilla Codina despite sharing the same board file in the vendor tree. Fix up some comments in the Codina DTS while we're at it. Cc: phone-devel@vger.kernel.org Cc: Markuss Broks <markuss.broks@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220222233313.1774416-2-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-04dt-bindings: arm: ux500: Document Codina-TMOLinus Walleij1-0/+5
This is a U8500-based phone named Samsung Galaxy Exhibit or Samsung SGH-T599, codenamed "Codina TMO" as it was made for T-Mobile. Cc: phone-devel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220222233313.1774416-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-04ARM: dts: ste-dbx: Update spi clock-names propertyKuldeep Singh1-6/+6
Now that spi pl022 binding only accept "sspclk" as clock name, ST ericsson platform with "SSPCLK" clock name start raising dtbs_check warnings. Make necessary changes to update this property in order to make it compliant with binding. clock-names:0: 'sspclk' was expected Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Link: https://lore.kernel.org/r/20220312113853.63446-5-singh.kuldeep87k@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-04dt-bindings: arm: bcm: add bindings for Asus RT-AC88UArınç ÜNAL1-0/+1
Add Asus RT-AC88U under BCM47094 based boards. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: BCM5301X: Fix compatible strings for BCM53012 and BCM53016 SoCArınç ÜNAL4-4/+4
Fix compatible strings for devicetrees using the BCM53012 and BCM53016 SoC. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04dt-bindings: arm: bcm: create new description for BCM53016Arınç ÜNAL1-1/+6
Create a new description for BCM53016 and move Meraki MR32 under it. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04dt-bindings: arm: bcm: fix BCM53012 and BCM53016 SoC stringsArınç ÜNAL1-2/+2
Fix inaccurate SoC strings brcm,brcm53012 and brcm,brcm53016 to respectively brcm,bcm53012 and brcm,bcm53016. Fixes: 4cb5201fcb5d ("dt-bindings: arm: bcm: Convert BCM4708 to YAML") Fixes: a2e385f5374d ("dt-bindings: ARM: add bindings for the Meraki MR32") Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: BCM5301X: Retrieve gmac1 MAC address from NVRAM on Asus RT-AC88UArınç ÜNAL1-0/+8
The et1macaddr NVRAM variable contains a MAC address for gmac1 on Asus RT-AC88U. Add NVMEM cell for it and reference it in the gmac1 node. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: BCM5301X: Add rgmii to port@5 of Broadcom switch on Asus RT-AC88UArınç ÜNAL1-0/+1
Define phy-mode of the Broadcom switch's port@5 as rgmii. This doesn't seem to matter but let's explicitly define it since phy-mode as rgmii is defined on the other side which is port@6 of the Realtek switch. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: BCM5301X: Remove cell properties from srab ports on Asus RT-AC88UArınç ÜNAL1-4/+1
Remove #address-cells and #size-cells properties from the ports node of &srab. They are already defined on bcm5301x.dtsi, there's no need to define them again. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: BCM5301X: Fix DTC warning for NAND nodeArınç ÜNAL1-2/+0
Remove the unnecessary #address-cells and #size-cells properties on the nand@0 node to fix the warning below. Warning (avoid_unnecessary_addr_size): /nand-controller@18028000/nand@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: BCM5301X: Update pin controller node nameRafał Miłecki1-1/+1
This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: cru-bus@100: 'pin-controller@1c0' does not match any of the regexes: '^clock-controller@[a-f0-9]+$', '^phy@[a-f0-9]+$', '^pinctrl@[a-f0-9]+$', '^syscon@[a-f0-9]+$', '^thermal@[a-f0-9]+$' From schema: Documentation/devicetree/bindings/mfd/brcm,cru.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pin-controller@1c0: $nodename:0: 'pin-controller@1c0' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' From schema: Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml Ref: e7391b021e3f ("dt-bindings: mfd: brcm,cru: Rename pinctrl node") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: bcm-cygnus: Update spi clock propertiesKuldeep Singh1-6/+6
PL022 binding require two clocks to be defined but broadcom cygnus platform doesn't comply with bindings and define only one clock. Update spi clocks and clocks-names property by adding appropriate clock reference to make it compliant with bindings. CC: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: s5pv210: Use standard arrays of generic PHYs for EHCI/OHCI deviceKrzysztof Kozlowski1-14/+4
Move USB PHYs to a standard arrays for S5PV210 EHCI/OHCI devices. This resolves the conflict between S5PV210 EHCI/OHCI sub-nodes and generic USB device bindings. Suggested-by: Måns Rullgård <mans@mansr.com> Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220314181948.246434-3-krzysztof.kozlowski@canonical.com
2022-04-04ARM: dts: s5pv210: align EHCI/OHCI nodes with dtschemaKrzysztof Kozlowski1-2/+2
The node names should be generic and USB DT schema expects "usb" names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220314181948.246434-2-krzysztof.kozlowski@canonical.com
2022-04-04ARM: dts: exynos: align EHCI/OHCI nodes with dtschema on Exynos4Krzysztof Kozlowski1-2/+2
The node names should be generic and USB DT schema expects "usb" names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220314181948.246434-1-krzysztof.kozlowski@canonical.com
2022-04-04ARM: dts: exynos: drop deprecated SFR region from MIPI phyKrzysztof Kozlowski1-3/+2
Commit e4b3d38088df ("phy: exynos-video-mipi: Fix regression by adding support for PMU regmap") deprecated the usage of unit address in MIPI phy node, in favor of a syscon phandle. Deprecating was a correct approach because that unit address was actually coming from Power Management Unit SFR range so its usage here caused overlapped memory mapping. In 2016 commit 26dbadba495f ("phy: exynos-mipi-video: Drop support for direct access to PMU") fully removed support for parsing that MIPI phy unit address (SFR range) but the address stayed in Exynos5250 DTSI for compatibility reasons. Remove that deprecated unit address from Exynos5250 MIPI phy, because it has been almost 6 years since it was deprecated and it causes now DT schema validation warnings: video-phy@10040710: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Any out-of-tree users of Exynos5250 DTSI, should update their code to use newer syscon property. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar<alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220314184113.251013-1-krzysztof.kozlowski@canonical.com
2022-04-04arm64: dts: tesla: add a specific compatible to MCT on FSDKrzysztof Kozlowski1-1/+1
One compatible is used for the Multi-Core Timer on Tesla FSD SoC, which is correct but not specific enough. The MCT blocks have different number of interrupts, so add a second specific compatible to Tesla FSD. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220304122424.307885-5-krzysztof.kozlowski@canonical.com
2022-04-04arm64: dts: exynos: add a specific compatible to MCTKrzysztof Kozlowski2-2/+4
One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos5433 and Exynos850. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220304122424.307885-4-krzysztof.kozlowski@canonical.com
2022-04-04ARM: dts: exynos: add a specific compatible to MCTKrzysztof Kozlowski4-4/+8
One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos3250 and all Exynos5 SoCs. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220304122424.307885-3-krzysztof.kozlowski@canonical.com
2022-04-04arm64: dts: exynos: move aliases to board in Exynos850Krzysztof Kozlowski2-16/+5
The aliases for typical blocks which are disabled by default in DTSI (like I2C, UART and MMC) should be defined in the board DTS. The board should add aliases only for enabled blocks according to its specific order. On Exynos850, move aliases of enabled blocks to E850-96 board and remove unused ones. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220221075219.10827-1-krzysztof.kozlowski@canonical.com
2022-04-04ARM: dts: bcm283x: fix ethernet node nameOleksij Rempel2-2/+2
It should be "ethernet@x" instead of "usbether@x" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-04ARM: dts: exynos: remove deprecated unit address for LPDDR3 timings on OdroidKrzysztof Kozlowski1-5/+2
Passing maximum frequency of LPDDR3 memory timings as unit address was deprecated in favor of 'max-freq' property. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20220206135918.211990-1-krzysztof.kozlowski@canonical.com
2022-04-04ARM: dts: exynos: fix compatible strings for Ethernet USB devicesOleksij Rempel5-9/+9
Fix compatible string for Ethernet USB device as required by USB device schema: Documentation/devicetree/bindings/usb/usb-device.yaml The textual representation of VID and PID shall be in lower case hexadecimal with leading zeroes suppressed. Since there are no kernel driver matching against this compatibles, I expect no regressions with this patch. At the same time, without this fix, we are not be able to validate this device nodes with newly provided DT schema. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/20220216074927.3619425-7-o.rempel@pengutronix.de Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-04ARM: dts: exynos: fix ethernet node name for different odroid boardsOleksij Rempel5-5/+5
The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/20220216074927.3619425-6-o.rempel@pengutronix.de Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-04arm64: dts: renesas: r8a77961: Add CAN-FD nodeKoji Matsuoka1-0/+25
Add the device node for the CAN-FD device on R-Car M3-W+. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220319223306.60782-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: falcon: Enable CANFD 0 and 1Ulrich Hecht1-0/+24
Enables confirmed-working CAN interfaces 0 and 1 on the Falcon board. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20220309162609.3726306-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r8a779a0: Add CANFD device nodeUlrich Hecht1-0/+56
This patch adds a CANFD device node for r8a779a0. Based on patch by Kazuya Mizuguchi. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20220309162609.3726306-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: falcon-cpu: Use INTC_EX for SN65DSI86Kieran Bingham1-2/+10
The INTC block is a better choice for handling the interrupts on the V3U as the INTC will always be powered, while the GPIO block may be de-clocked if not in use. Further more, it may be likely to have a lower power consumption as it does not need to drive the pins. Switch the interrupt parent and interrupts definition from gpio1 to irq0 on intc_ex, and configure the PFC accordingly. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20220309190631.1576372-1-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Add TSU nodeLad Prabhakar1-0/+41
Add TSU and thermal-zones nodes to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220308223324.7456-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Add OPP tableLad Prabhakar1-0/+29
Add OPP table for RZ/V2L SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220308223324.7456-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Fillup the GPU nodeLad Prabhakar1-1/+61
Renesas RZ/V2L SoC has Mali-G31 GPU, this patch fills up the GPU node and adds opp table to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220308223324.7456-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulatorBiju Das1-0/+13
Add vdd core regulator (1.1 V) for GPU. This patch add regulator support for GPU. The H/W manual mentions nothing about a GPU regulator. So using vdd core regulator for GPU. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220307192436.13237-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTMBiju Das1-0/+8
Enable OSTM{1, 2} interfaces on RZ/G2LC SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220307192436.13237-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flashBiju Das1-0/+40
Enable mt25qu512a flash connected to QSPI0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220307192436.13237-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: rzg2lc-smarc: Enable AudioBiju Das2-6/+7
Enable Audio on RZ/G2LC SMARC EVK by deleting ssi0 entries from board DT and adding pincontrol entries to the soc-pinctrl dtsi, so that entries from common dtsi kick in and make audio functionality operational. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220303164155.7706-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2}Biju Das3-13/+20
Enable i2c{0,1} on RZ/G2LC SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable i2c2 by adding to soc dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220303164155.7706-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from common dtsiBiju Das4-21/+26
On RZ/G2L SoM module, the Audio codec is connected to i2c3 bus whereas on RZ/G2LC, it is connected to i2c2 bus. So move out i2c3 and wm8978 nodes from common dtsi to soc specific dtsi. While at it add wm8978 node to RZ/G2LC SoC specific dtsi to fix the build error. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220303164155.7706-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodesBiju Das1-12/+12
Sort the pinctrl nodes alphabetically. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220303164155.7706-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0Biju Das2-46/+11
Enable usb2.0 host/device functionality on RZ/G2LC SMARC EVK by deleting phyrst, usb2_phy{0,1}, ehci/ohci{0,1} and hsusb entries from board DT, so that entries from common dtsi kick in and make USB2.0 functionality operational. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220302074043.21525-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Add SPI{0,2} nodes and fillup SPI1 stub nodeLad Prabhakar1-1/+42
Add SPI{0,2} nodes and fillup SPI1 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-13-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Add USB2.0 device supportLad Prabhakar1-1/+15
Fillup the hsusb stub node in RZ/V2L (R9A07G054) SoC DTSI which enables USB2.0 device support. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Add USB2.0 phy and host supportLad Prabhakar1-7/+67
Add USB2.0 phy and host support to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 ↵Lad Prabhakar1-1/+79
stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Fillup the WDT{0,1,2} stub nodesLad Prabhakar1-3/+33
Fillup the WDT{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodesLad Prabhakar1-3/+21
Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Fillup the sbc stub nodeLad Prabhakar1-1/+9
Fillup the sbc stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054: Fillup the I2C{0,1,2,3} stub nodesLad Prabhakar1-3/+70
Fillup the I2C{0,1,2,3} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoCBiju Das1-2/+3
Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's. SYSC controller found on the RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55 core0 reset vector address configuration register. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220315142644.17660-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog nodesLad Prabhakar1-5/+0
Drop deleting can{0,1}-stb-hog nodes so that CAN becomes operational on Renesas RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220227203744.18355-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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