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2022-04-21ARM: dts: am335x: Guardian: Update interface pinmuxGireesh Hiremath1-7/+37
* Update interface pinmux for - poweroff button - battery and coincell enable - ASP and Miraculix Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-14-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Disable DMA property of USB1Gireesh Hiremath1-0/+2
* Dispble DMA property of USB1 Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-13-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Enable UART port twoGireesh Hiremath1-0/+15
* Add support for uart2 port Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-12-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Update backlight parameterGireesh Hiremath1-2/+29
* Update default brightness and dimming frequency * Enable current sink, while initialization Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-11-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Add lcd portGireesh Hiremath1-0/+54
* Add port to the node lcdc Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-10-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Update regulator node nameGireesh Hiremath1-1/+3
* Update mmcsd voltage regulator node name Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-9-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Update beeper labelGireesh Hiremath1-4/+4
* Update lable pwm to guardian beeper Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-8-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Update life ledGireesh Hiremath1-8/+8
* update life led label and pin number Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-7-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Remove mmc status ledGireesh Hiremath1-9/+0
* MMC presence indicater LED removed from Guardian Board Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-6-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Disable poweroff support from RTCGireesh Hiremath1-1/+0
* Disabling poweroff support form RTC will allow poweroff to handle from other machanism Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-5-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Add keypadGireesh Hiremath1-0/+24
* Add support to guardian mt gpio keypad Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-4-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Rename power button labelGireesh Hiremath1-7/+8
* Rename label button to power button Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-3-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Update NAND partition tableGireesh Hiremath1-17/+48
* Update partition table to save env and splash image * GPMC config values optimized for Bosch Guardian Board * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-2-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: logicpd-som-lv: Move pinmuxing to peripheral nodesAdam Ford1-5/+5
Move some pinmux references to their respective peripherals. This keeps the pins in safe-mode until they are requested. Signed-off-by: Adam Ford <aford173@gmail.com> Message-Id: <20220303171818.11060-2-aford173@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: omap3/4/5: fix ethernet node name for different OMAP boardsOleksij Rempel4-4/+4
The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Message-Id: <20220216074927.3619425-8-o.rempel@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-20ARM: dts: marvell: align SPI NOR node name with dtschemaKrzysztof Kozlowski36-36/+36
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407143234.295426-1-krzysztof.kozlowski@linaro.org
2022-04-20ARM: dts: omap: align SPI NOR node name with dtschemaKrzysztof Kozlowski15-15/+15
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407143304.295610-1-krzysztof.kozlowski@linaro.org
2022-04-20ARM: dts: nuvoton: align SPI NOR node name with dtschemaKrzysztof Kozlowski5-14/+14
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407143127.295008-1-krzysztof.kozlowski@linaro.org
2022-04-19ARM: dts: bcm283x: Align ETH_CLK GPIO line namePhil Elwell4-4/+4
The GPIO line name ETHCLK is not aligned with the other signals like WIFI_CLK. Recently this has been fixed in the vendor tree, so upstream this change. Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-19ARM: dts: bcm283x: Remove gpio line name NCStefan Wahren14-103/+90
The convention to name not connected GPIOs with NC has never been adapted. Also newer Raspberry Pi boards like RPi 4 never did. So fix this inconsistency by removing all of the NC names. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-19ARM: dts: bcm2835-rpi-b: Fix GPIO line namesStefan Wahren1-7/+6
Recently this has been fixed in the vendor tree, so upstream this. Fixes: 731b26a6ac17 ("ARM: bcm2835: Add names for the Raspberry Pi GPIO lines") Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-19ARM: dts: bcm2837-rpi-3-b-plus: Fix GPIO line name of power LEDPhil Elwell1-1/+1
The red LED on the Raspberry Pi 3 B Plus is the power LED. So fix the GPIO line name accordingly. Fixes: 71c0cd2283f2 ("ARM: dts: bcm2837: Add Raspberry Pi 3 B+") Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-19ARM: dts: bcm2837-rpi-cm3-io3: Fix GPIO line names for SMPS I2CPhil Elwell1-2/+2
The GPIOs 46 & 47 are already used for a I2C interface to a SMPS. So fix the GPIO line names accordingly. Fixes: a54fe8a6cf66 ("ARM: dts: add Raspberry Pi Compute Module 3 and IO board") Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-19ARM: dts: bcm2835-rpi-zero-w: Fix GPIO line name for Wifi/BTPhil Elwell1-10/+12
The GPIOs 30 to 39 are connected to the Cypress CYW43438 (Wifi/BT). So fix the GPIO line names accordingly. Fixes: 2c7c040c73e9 ("ARM: dts: bcm2835: Add Raspberry Pi Zero W") Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-19ARM: dts: stm32: enable RTC support on stm32mp135f-dkValentin Caron1-0/+4
Enables the support of RTC on stm32mp135f-dk board. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-04-19ARM: dts: stm32: add RTC node on stm32mp131Valentin Caron1-0/+15
Add RTC node with compatible, clock, and interrupt properties on stm32mp131. Add clk_rtc_k fixed clock for RTC. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-04-19ARM: dts: stm32: Fix PHY post-reset delay on Avenger96Marek Vasut1-0/+1
Per KSZ9031RNX PHY datasheet FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2: After the de-assertion of reset, wait a minimum of 100 μs before starting programming on the MIIM (MDC/MDIO) interface. Add 1ms post-reset delay to guarantee this figure. Fixes: 010ca9fe500bf ("ARM: dts: stm32: Add missing ethernet PHY reset on AV96") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-04-19ARM: dts: stm32: fix pinctrl node name warnings (MPU soc)Fabien Dessenne2-3/+3
The recent addition pinctrl.yaml in commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml") resulted in some node name warnings. Fix the node names to the preferred 'pinctrl'. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-04-19ARM: dts: stm32: fix pinctrl node name warnings (MCU soc)Fabien Dessenne3-3/+3
The recent addition pinctrl.yaml in commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml") resulted in some node name warnings. Fix the node names to the preferred 'pinctrl'. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-04-19arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFSKrzysztof Kozlowski2-4/+4
The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com
2022-04-19ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer nodeGeert Uytterhoeven1-2/+1
"make dtbs_check": arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt.yaml: timer: compatible: 'oneOf' conditional failed, one must be fixed: ['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long 'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv7-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv8-timer'] From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml The Cortex-A7 timer should just declare compatibility with "arm,armv7-timer". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a8e0cf00a983b4c539cdb1cfad5cc6b10b423c5b.1649680220.git.geert+renesas@glider.be
2022-04-19arm64: dts: renesas: r8a779f0: Add GPIO nodesGeert Uytterhoeven1-0/+60
Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that GPIO blocks 4-7 are not added, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be
2022-04-16ARM: dts: BCM5301X: Disable gmac0 and enable port@8 on Asus RT-AC88UArınç ÜNAL1-1/+4
Disable gmac0 which is not connected to any switch MAC. Enable port@8 of the Broadcom switch which is connected to gmac2. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-14ARM: dts: ux500: Add NFC to the CodinaLinus Walleij1-1/+30
This adds the PN544 NFC chip mounted on some of the Codina models numbered GT-I8160P. The "P" at the end of the product number indicates that an NFC chip is mounted. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-14arm64: dts: juno: add CTI entries to device treeMike Leach8-5/+302
Add Coresight Cross Trigger Interface(CTI) entries to the device tree for all the Juno variants. Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-14arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnelSudeep Holla2-4/+4
The SCMI power domain ID for all the coresight components is 8 while the previous/older SCPI domain was 0. When adding SCMI variant, couple of instances retained SCPI domain ID by mistake. Fix the same by using the correct SCMI power domain ID of 8. Link: https://lore.kernel.org/r/20220413093547.1699535-1-sudeep.holla@arm.com Fixes: 96bb0954860a ("arm64: dts: juno: Add separate SCMI variants") Cc: Robin Murphy <robin.murphy@arm.com> Reported-by: Mike Leach <Mike.Leach@arm.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-13arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platformBiju Das2-1/+98
Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0 device selection is based on the SW1[3] switch position. Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. Set SW1[3] to position ON for selecting Ethernet0. This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platformBiju Das2-0/+112
RZ/G2UL SoM has both 64GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on SW1[2] on SoM module. Set SW1[2] to position OFF for selecting eMMC Set SW1[2] to position ON for selecting microSD This patch enables eMMC on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platformBiju Das4-11/+63
Enable the microSD card slot connected to SDHI1 on the RZ/G2UL SMARC platform by removing the sdhi1 override which disabled it, and by adding the necessary pinmux required for SDHI1. This patch also adds gpios property to vccq_sdhi1 regulator. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Add GbEthernet nodesBiju Das1-0/+40
Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Add SDHI nodesBiju Das1-2/+24
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pinsBiju Das2-5/+25
Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting the pinctrl-0 and pinctrl-names properties for scif0 node so that we now actually make use of these properties for scif0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub nodeBiju Das1-1/+7
Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVKBiju Das3-0/+138
Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11): - memory - External input clock - CPG - DMA - SCIF It shares the same carrier board with RZ/G2L, but the pin mapping is different. Disable the device nodes which are not tested and delete the corresponding pinctrl definitions. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoCBiju Das1-0/+413
Add initial DTSI for RZ/G2UL SoC. Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share the common dtsi (rz-smarc.dtsi) file. Place holders are added in device nodes to avoid compilation errors for the devices which have not been enabled yet on RZ/G2UL SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13Merge tag 'renesas-r9a07g043-dt-binding-defs-tag' into HEADGeert Uytterhoeven1-0/+184
Renesas RZ/G2UL DT Binding Definitions Clock and reset definitions for the Renesas RZ/G2UL (R9A07G043) SoC, shared by driver and DT source files.
2022-04-13arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from ↵Biju Das3-1/+8
common dtsi On RZ/G2{L,LC} SoM module, gpio for power selection is connected to P39_1 whereas on RZ/G2UL it is connected to P6_1. So move gpios property of vccq_sdhi1 regulator from common dtsi to soc specific dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220401175427.19078-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier boardBiju Das3-6/+15
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file and drops deleting pinctl* properties from DTS file. RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220401145702.17954-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: ulcb: Add RPC HyperFlash device nodeGeert Uytterhoeven1-0/+49
Add the RPC HyperFlash device node along with its partitions to the common ULCB board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/61a63e819d4296760ca7ae83ef5226a2c4d7bd93.1648548339.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: salvator-common: Add RPC HyperFlash device nodeGeert Uytterhoeven1-0/+49
Add the RPC HyperFlash device node along with its partitions to the common Salvator-X(S) board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cfc6af8a4c42febcc405b7356c38448eec8e29b0.1648548339.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 22:38:19 +0300