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2022-05-03ARM: dts: am33xx: Add i2c voltage scaling firmware to wkup_m3_ipcDave Gerlach3-0/+12
Add appropriate firmware-name property for all am33xx platforms. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> [dfustini: change property from 'ti,scale-data-fw' to 'firmware-name'] Signed-off-by: Drew Fustini <dfustini@baylibre.com> Message-Id: <20220502021508.1342869-3-dfustini@baylibre.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-05-03ARM: dts: am437x-gp-evm: Enable wkup_m3 control of IO isolationDave Gerlach1-0/+4
With this flag wkup_m3 is able to control IO isolation during suspend on the board. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Message-Id: <20220502021508.1342869-2-dfustini@baylibre.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-05-02ARM: dts: stm32: add support for Protonic PRTT1x boardsOleksij Rempel5-0/+651
This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux groupOleksij Rempel1-0/+15
Add spi1-1 pingroup as preparation for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02dt-bindings: net: silabs,wfx: add prt,prtt1c-wfm200 antenna variantOleksij Rempel1-0/+1
Add compatible for wfm200 antenna configuration variant for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02dt-bindings: arm: stm32: Add compatible strings for Protonic T1L boardsOleksij Rempel1-0/+8
This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02dt-bindings: arm: stm32: correct blank linesKrzysztof Kozlowski1-1/+2
Correct blank lines to precesily separate entries. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02dt-bindings: arm: stm32: narrow DH STM32MP1 SoM boardsKrzysztof Kozlowski1-15/+22
The bindings for DH STM32MP1 SoM boards allows invalid combinations, e.g. st,stm32mp153 SoC on a dh,stm32mp157c-dhcom-som SoM. Split the enums to properly match valid setups. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-04-30arm64: dts: juno: Drop useless 'dma-channels/requests' propertiesKrzysztof Kozlowski1-2/+0
The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Another reason is that the number of requests also does not seem right (should be 8). Link: https://lore.kernel.org/r/20220430121902.59895-5-krzysztof.kozlowski@linaro.org Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-29Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19Geert Uytterhoeven2-0/+135
Renesas R-Car V4H DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0) SoC, shared by driver and DT source files.
2022-04-29arm64: tegra: Add memory controller channelsAshish Mhetre3-7/+49
From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping. Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-29dt-bindings: memory: tegra: Update validation for reg and reg-namesAshish Mhetre1-6/+74
From Tegra186 onwards, memory controller support multiple channels. "reg" items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and Tegra234 have overall 17 memory controller channels each. There is one "reg" entry for memory controller stream-ID registers. So update the "reg" property's "minItems" and "maxItems" accordingly in the Tegra186 devicetree documentation. Also update validation for "reg-names" added for these corresponding "reg" items. ABI change due to new bindings is intended but backward compatibility is preserved in driver. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-29arm64: dts: renesas: rzg2ul-smarc-som: Enable watchdogBiju Das1-0/+10
Enable watchdog{0,2} interfaces on RZ/G2UL SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-14-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc-som: Enable OSTMBiju Das1-0/+8
Enable OSTM{1, 2} interfaces on RZ/G2UL SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc: Enable CANFDBiju Das3-6/+36
Enable CANFD on RZ/G2UL SMARC platform. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc: Enable i2c{0,1} and wm8978Biju Das3-18/+18
Enable i2c{0,1} on RZ/G2UL SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable wm8978 audio codec. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29ARM: dts: am335x-myirtech: Update NAND default partition table layoutAlexander Shiyan2-10/+13
This patch replaces the legacy partition table layout with a modern style. As an additional change, we are reserving space for three backup MLO entries and increasing space for the main bootloader. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Message-Id: <20220427081914.6773-2-eagle.alexander923@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-29ARM: dts: am335x-myirtech: Add an external clock oscillator for CPU RTCAlexander Shiyan1-0/+9
The CPU RTC has an external crystal, so to keep time, let's define it for devicetree. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Message-Id: <20220427081914.6773-1-eagle.alexander923@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodesBiju Das1-2/+22
Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodesBiju Das1-3/+21
Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the CANFD stub nodeBiju Das1-1/+30
Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add USB2.0 supportBiju Das1-8/+82
Add USB2.0 host and device support by filling usb phy control, phy, device and host stub nodes in RZ/G2UL SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 ↵Biju Das1-1/+79
stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub ↵Biju Das1-3/+70
nodes Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28ARM: dts: r9a06g032: Add missing '#power-domain-cells'Herve Codina1-0/+1
Without '#power-domain-cells' property, power-domains cannot be used. This property is noted required in the device-tree binding. Add '#power-domain-cells' as needed. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220422120850.769480-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK boardPhil Edworthy1-0/+6
Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output The RZ/V2M Evaluation Kit (V2MEVK) consists of the RZ/V2M Main Board, RZ/V2M Base Board, and CIS IMX415 Board (CIS). Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220330154024.112270-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28dt-bindings: power: renesas,rcar-sysc: Document r8a779g0 SYSC bindingsYoshihiro Shimoda1-0/+1
Document bindings for the R-Car V4H (aka R8A779G0) SYSC block. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220420084255.375700-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-27ARM: dts: ux500: Add GPS to the CodinaLinus Walleij1-4/+28
The Codina has a Broadcom BCM4751 GPS chip. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-26arm64: tegra: Enable ASRC on various platformsSameer Pujar4-0/+892
Enable ASRC module usage on various Jetson Platforms. This can be plugged into an audio path using ALSA mixer controls. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-26arm64: tegra: Add ASRC device on Tegra186 and laterSameer Pujar3-0/+23
Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is present on Tegra186 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-26arm64: dts: marvell: align SPI NOR node name with dtschemaKrzysztof Kozlowski12-14/+14
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407143234.295426-2-krzysztof.kozlowski@linaro.org
2022-04-26arm64: dts: microchip: align SPI NOR node name with dtschemaKrzysztof Kozlowski4-7/+7
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220407143223.295344-2-krzysztof.kozlowski@linaro.org
2022-04-25arm64: tegra: Update PWM fan node nameJon Hunter4-4/+4
According to the device-tree binding document for PWM fans [0], the PWM fan node name should be 'pwm-fan'. Update the PWM fan node name to align with this. [0] Documentation/devicetree/bindings/hwmon/pwm-fan.txt Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-25arm64: tegra: Add node for Tegra234 CCPLEX clusterSumit Gupta1-0/+7
Adding CCPLEX cluster node to represent Tegra234 cpufreq. Tegra234 uses some of the CRAB (Control Register Access Bus) registers for CPU frequency requests. These registers are memory mapped to the CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB registers is required only for CPU frequency info. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-25arm64: dts: fvp: Align virtio device node names with dtschemaSudeep Holla3-5/+5
Align the virtio mmio device tree node names with the schema to avoid any schema warnings. Link: https://lore.kernel.org/r/20220425135524.1077986-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25arm64: dts: fvp: Add virtio-rng supportDiego Sueiro3-2/+10
The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17, so add the devicetree node to support it. It is disabled by default to avoid any issues with models that doesn't support it. Link: https://lore.kernel.org/r/ac3be672c636091ee1e079cadce776b1fb7e0b2e.1650543392.git.diego.sueiro@arm.com Signed-off-by: Diego Sueiro <diego.sueiro@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25arm64: dts: Add Arm corstone1000 platform supportRui Miguel Silva4-0/+248
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Link: https://lore.kernel.org/r/20220408131922.3864348-3-rui.silva@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25dt-bindings: Add Arm corstone1000 platformRui Miguel Silva1-0/+45
Add bindings to describe the FPGA in a prototyping board (MPS3) implementation and the Fixed Virtual Platform implementation of the ARM Corstone1000 platform. Link: https://lore.kernel.org/r/20220408131922.3864348-2-rui.silva@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25dt-bindings: reset: renesas,rst: Document r8a779g0 reset moduleYoshihiro Shimoda1-0/+1
Document bindings for the R-Car V4H (R8A779G0) reset module. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220420084255.375700-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: arm: renesas: Document R-Car V4H White Hawk DT bindingsYoshihiro Shimoda1-0/+12
Add device tree binding documentation for the Renesas R-Car V4H (r8a779g0) SoC and the Renesas White Hawk CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220420084255.375700-2-yoshihiro.shimoda.uh@renesas.com Link: https://lore.kernel.org/r/20220420084255.375700-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: clock: Add r8a779g0 CPG Core Clock DefinitionsYoshihiro Shimoda1-0/+90
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: power: Add r8a779g0 SYSC power domain definitionsYoshihiro Shimoda1-0/+45
Add power domain indices for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220425064201.459633-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-23ARM: dts: add dts files for bcmbca soc 47622William Zhang3-0/+158
Add dts for ARMv7 based broadband SoC BCM47622. bcm47622.dtsi is the SoC description dts header and bcm947622.dts is a simple dts file for Broadcom BCM947622 Reference board that only enable the UART port. Signed-off-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-23dt-bindings: arm: add bcmbca device tree binding documentWilliam Zhang1-0/+33
Add arch bcmbca device tree binding document for Broadcom ARM based broadband SoC chipsets. In this change, only BCM47622 is added. Other chipsets will be added in the future. Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-04-21Merge tag 'samsung-dt64-5.19' of ↵Arnd Bergmann4-19/+10
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM64 changes for v5.19 1. Cleanup: move aliases of board-related features to board in Exynos850. 2. Add specific compatibles to Multi Core Timer to allow stricter DT schema matching. * tag 'samsung-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: tesla: add a specific compatible to MCT on FSD arm64: dts: exynos: add a specific compatible to MCT arm64: dts: exynos: move aliases to board in Exynos850 Link: https://lore.kernel.org/r/20220420072152.11696-3-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-21Merge tag 'samsung-dt-5.19' of ↵Arnd Bergmann15-64/+52
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.19 1. Several DT schema related changes to make DTBs passing schema checks: EHCI/OHCI/DMA/Ethernet node names, DMA channels order, USB-like compatibles. 2. Add specific compatibles to Multi Core Timer to allow stricter DT schema matching. 3. Cleanup from deprecated bindings: - Remove deprecated unit-address workaround for Exynos5422 Odroid XU3 LPDDR3 memory timings. - Do not use unit-address (and SFR region) in Exynos5250 MIPI phy in favor of syscon node (unit-address deprecated in 2016). - Use standard generic PHYs for EHCI/OHCI device in S5PV210. 4. Fix inverted SPI CS (thus blank panel) on S5PV210 Aries boards. 5. Correct Bluetooth interupt name on S5PV210 Aries boards. * tag 'samsung-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: s5pv210: align DMA channels with dtschema ARM: dts: s5pv210: Adjust DMA node names to match spec ARM: dts: s5pv210: Adjust memory reg entries to match spec ARM: dts: s5pv210: Correct interrupt name for bluetooth in Aries ARM: dts: s5pv210: Remove spi-cs-high on panel in Aries ARM: dts: s5pv210: Use standard arrays of generic PHYs for EHCI/OHCI device ARM: dts: s5pv210: align EHCI/OHCI nodes with dtschema ARM: dts: exynos: align EHCI/OHCI nodes with dtschema on Exynos4 ARM: dts: exynos: drop deprecated SFR region from MIPI phy ARM: dts: exynos: add a specific compatible to MCT ARM: dts: exynos: remove deprecated unit address for LPDDR3 timings on Odroid ARM: dts: exynos: fix compatible strings for Ethernet USB devices ARM: dts: exynos: fix ethernet node name for different odroid boards Link: https://lore.kernel.org/r/20220420072152.11696-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-21Merge tag 'dt-cleanup-5.19' of ↵Arnd Bergmann6-40/+40
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Minor cleanup of ARM DTS for v5.19 Align node names and unit addresses to DT schema and DT coding style in nspire, ox820 and socfpga. * tag 'dt-cleanup-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: socfpga: align interrupt controller node name with dtschema ARM: dts: ox820: align interrupt controller node name with dtschema ARM: dts: nspire: use lower case hex addresses in node unit addresses Link: https://lore.kernel.org/r/20220420072152.11696-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-21ARM: dts: am335x-baltos: update MPU regulator rangeYegor Yefremov1-1/+1
Update the max MPU voltage range to align with the maximum possible value allowed in the operating-points table, which is max target voltage of 132500 uV + 2%. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Message-Id: <20220419143923.25196-1-yegorslists@googlemail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Update commentsGireesh Hiremath1-9/+15
* Add comment to improve readability Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-16-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-04-21ARM: dts: am335x: Guardian: Add gpio line manesGireesh Hiremath1-0/+74
* assign name to gpio line Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Message-Id: <20220325100613.1494-15-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 15:08:39 +0300