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The MV88E6060 switch has internal PHY registers at MDIO
addresses 0x00..0x04. Tie each port to the corresponding
PHY.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.8
- Fix dtbs_check warnings for nand, usb, FPGA firmware, and pin-controller
- Clean up of DTS for Agilex5
* tag 'socfpga_dts_updates_for_v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: intel: minor whitespace cleanup around '='
arm64: dts: socfpga: agilex: drop redundant status
arm64: dts: socfpga: agilex: add unit address to soc node
arm64: dts: socfpga: agilex: move firmware out of soc node
arm64: dts: socfpga: agilex: move FPGA region out of soc node
arm64: dts: socfpga: agilex: align pin-controller name with bindings
arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
arm64: dts: socfpga: stratix10: add unit address to soc node
arm64: dts: socfpga: stratix10: move firmware out of soc node
arm64: dts: socfpga: stratix10: move FPGA region out of soc node
arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
ARM: dts: socfpga: align NAND controller name with bindings
ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
Link: https://lore.kernel.org/r/20240104001354.152410-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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New device nodes are enabled by default.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The "soc" node has ranges with addresses, so it is should have unit
address to fix dtc W=1 warnings like:
socfpga_agilex.dtsi:152.6-674.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The "soc" node is supposed to have only MMIO children, so move the
firmware/svc node to top level to fix dtc W=1 warnings like:
socfpga_agilex.dtsi:663.12-673.5: Warning (simple_bus_reg): /soc@0/firmware: missing or empty reg/ranges property
The node should still be instantiated by drivers/of/platform.c, just
like in all other platforms.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The "soc" node is supposed to have only MMIO children, so move the FPGA
region node to top level to fix dtc W=1 warnings like:
socfpga_agilex.dtsi:141.20-146.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Use a generic node name for the pin controller node to fix:
/socfpga_agilex_n6000.dtb: pinconf@ffd13100: $nodename:0: 'pinconf@ffd13100' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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altr,dw-mshc-ciu-div and altr,dw-mshc-sdr-timing are neither documented
nor used by Linux, so remove them to fix dtbs_check warnings like:
socfpga_stratix10_swvp.dtb: mmc@ff808000: Unevaluated properties are not allowed
('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing' were unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Bindings expect NAND child node name to match certain patterns:
socfpga_agilex_socdk_nand.dtb: nand-controller@ffb90000: Unevaluated properties are not allowed ('flash@0' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The "soc" node has ranges with addresses, so it is should have unit
address to fix dtc W=1 warnings like:
socfpga_stratix10.dtsi:128.6-636.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The "soc" node is supposed to have only MMIO children, so move the
firmware/svc node to top level to fix dtc W=1 warnings like:
socfpga_stratix10.dtsi:625.12-635.5: Warning (simple_bus_reg): /soc@0/firmware: missing or empty reg/ranges property
The node should still be instantiated by drivers/of/platform.c, just
like in all other platforms.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The "soc" node is supposed to have only MMIO children, so move the FPGA
region node to top level to fix dtc W=1 warnings like:
socfpga_stratix10.dtsi:136.20-141.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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pinctrl-single bindings require pin configuration node names to match
certain patterns:
socfpga_stratix10_socdk.dtb: pinctrl@ffd13000: 'i2c1-pmx-func', 'i2c1-pmx-func-gpio'
do not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The DWC2 USB bindings require clock-names property, to provide such to
fix warnings like:
socfpga_stratix10_swvp.dtb: usb@ffb40000: 'clock-names' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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cdns,page-size and cdns,block-size are neither documented nor used by
Linux, so remove them to fix dtbs_check warnings like:
socfpga_n5x_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Bindings expect NAND controller node name to match certain patterns:
socfpga_arria10_socdk_nand.dtb: nand@ffb90000: $nodename:0: 'nand@ffb90000' does not match '^nand-controller(@.*)?'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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cdns,page-size and cdns,block-size are neither documented nor used by
Linux, so remove them to fix dtbs_check warnings like:
socfpga_arria5_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
RK3036 fix for emmc init issue and stdout-path for the console
on rk3036 kylin.
* tag 'v6.8-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Remove rockchip,default-sample-phase from rk3036.dtsi
ARM: dts: rockchip: Add stdout-path for rk3036 kylin
Link: https://lore.kernel.org/r/15502825.JCcGWNJJiE@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
One new boards, the CoolPi CM5 SoM and 4B SBC. Basic node for the rk3588
display controller and a bunch of small improvements for different boards,
* tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits)
arm64: dts: rockchip: Fix led pinctrl of lubancat 1
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
arm64: dts: rockchip: support poweroff on the rock-5b
arm64: dts: rockchip: Support poweroff on Orange Pi 5
arm64: dts: rockchip: nanopc-t6 sdmmc beautification
arm64: dts: rockchip: Fix rk3588 USB power-domain clocks
arm64: dts: rockchip: configure eth pad driver strength for orangepi r1 plus lts
arm64: dts: rockchip: Support poweroff on NanoPC-T6
arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names cleanup
arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB
dt-bindings: arm: rockchip: Add Cool Pi CM5
arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B
dt-bindings: arm: rockchip: Add Cool Pi 4B
dt-bindings: vendor-prefixes: Add Cool Pi
arm64: dts: rockchip: add gpio-line-names to rk3328-rock-pi-e
arm64: dts: rockchip: make use gpio-keys for buttons on puma-haikou
arm64: dts: rockchip: expose BIOS Disable feedback pin on rk3399-puma
arm64: dts: rockchip: fix misleading comment in rk3399-puma-haikou.dts
arm64: dts: rockchip: Add vop on rk3588
...
Link: https://lore.kernel.org/r/3711719.VqM8IeB0Os@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
A few more Qualcomm Arm64 DeviceTree updates for v6.8
This corrects the rate of the UTMI clock on IPQ6018 USB0. The SDHCI
controller on SC7280 gains missing markings for being cache-coherent.
For SC8180X a typo in assignment of PCIe refgen clocks is corrected, PCI
controllers are marked cache-coherent, and the USB SS PHY interrupts are
corrected to allow wakeup.
Similarly USB HS PHY and SS PHY interrupts are corrected to allow
wakeup on SDM670.
On SM8550 the X3 cluster idle state is properly described, and the
latency numbers are adjusted for all the idle states.
The PM8550 regulator supplies on X1E are corrected to match the driver
and binding, and the timer node is updated to avoid an unnecessary
validation error.
* tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: dts: qcom: sc8180x: Fix up PCIe nodes
arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent
arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550
arm64: dts: qcom: sm8550: Update idle state time requirements
arm64: dts: qcom: sm8550: Separate out X3 idle state
arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK
arm64: dts: qcom: x1e80100: align mem timer size cells with bindings
arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent
arm64: dts: qcom: sc8180x: fix USB SS wakeup
arm64: dts: qcom: sdm670: fix USB SS wakeup
arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts
Link: https://lore.kernel.org/r/20231231034108.3262678-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
A few more Qualcomm Arm32 DeviceTree updates fr v6.8
The recently introduced changes to the SDX55 USB controller interrupt
flags prevents the USB controller from probing. These patches corrects
the PDC's interrupt-cells, so that appropriate interrupt controller
(which supports both-edge interrupts) can be used instead, which
resolves the issue.
The SDX55 PCIe PHY base address is also adjusted, from a mistake when
the node recently was transitioned to the modernized DeviceTree binding.
* tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: sdx55: Fix the base address of PCIe PHY
ARM: dts: qcom: sdx55: fix USB SS wakeup
ARM: dts: qcom: sdx55: fix USB DP/DM HS PHY interrupts
ARM: dts: qcom: sdx55: fix pdc '#interrupt-cells'
Link: https://lore.kernel.org/r/20231231033153.3262575-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 6.8, please pull the following:
- Rafal adds a Device Tree node for the BCM63138 high-speed UART used
for Bluetooth devices
* tag 'arm-soc/for-6.8/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: broadcom: Add BCM63138's high speed UART
Link: https://lore.kernel.org/r/20231228085822.3656546-1-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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ARM: sprd: DTS and bindings for v6.8-rc1
Unisoc ARM64 DTS and bindings changes are:
- Fixed a few dtb_check warnings
- Add bindings for a new SoC - UMS9620
- Fixed an issue on UMS512
* tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux:
arm64: dts: sprd: Change UMS512 idle-state nodename to match bindings
arm64: dts: sprd: Add clock reference for pll2 on UMS512
arm64: dts: sprd: Removed unused clock references from etm nodes
arm64: dts: sprd: Add support for Unisoc's UMS9620
dt-bindings: arm: Add compatible strings for Unisoc's UMS9620
arm64: dts: sprd: fix the cpu node for UMS512
Link: https://lore.kernel.org/r/20231228084958.1439115-1-chunyan.zhang@unisoc.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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According to the schematics, the gpio control sys_led is GPIO0_C5.
Fixes: 8d94da58de53 ("arm64: dts: rockchip: Add EmbedFire LubanCat 1")
Reported-by: Zhang Ning <zhangn1985@outlook.com>
Closes: https://lore.kernel.org/linux-rockchip/OS0P286MB06412D049D8BF7B063D41350CD95A@OS0P286MB0641.JPNP286.PROD.OUTLOOK.COM/T/#u
Signed-off-by: Andy Yan <andyshrk@163.com>
Link: https://lore.kernel.org/r/20231225005055.3102743-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and
gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1.
Signed-off-by: John Clark <inindev@gmail.com>
Link: https://lore.kernel.org/r/20231225223226.17690-1-inindev@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and
gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1.
Signed-off-by: John Clark <inindev@gmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20231225222859.17153-2-inindev@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Allow the rock-5b to poweroff its pmic. When issuing a "shutdown -h now"
on the rock-5b it reboots instead. Defining 'system-power-controller'
allows the rk806 to power down.
Commit c699fbfdfd54 ("arm64: dts: rockchip: Support poweroff on
NanoPC-T6") similarly resolves this issue for the nanopc-t6.
Signed-off-by: John Clark <inindev@gmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20231225222859.17153-1-inindev@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The RK806 on the Orange Pi 5 can be used to power on/off the whole board.
Mark it as the system power controller.
Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com>
Link: https://lore.kernel.org/r/20231227203211.1047-1-honyuenkwun@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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drop max-frequency = <200000000> as it is already defined in rk3588s.dtsi
order no-sdio & no-mmc properties while we are here
Signed-off-by: John Clark <inindev@gmail.com>
Link: https://lore.kernel.org/r/20231228173011.2863-1-inindev@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Fix below dtbs_check warning:
idle-states: 'core-pd' does not match any of the regexes: '^(cpu|cluster)-', 'pinctrl-[0-9]+'
Link: https://lore.kernel.org/r/20231221092824.1169453-3-chunyan.zhang@unisoc.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
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Fix below dtbs_check warning:
'clocks' is a dependency of 'clock-names'
Link: https://lore.kernel.org/r/20231221092824.1169453-2-chunyan.zhang@unisoc.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
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Remove these unused clock references to fix dtbs_check warnings:
etm@3f740000: clocks: [[11], [35, 34], [36, 8]] is too long
etm@3f740000: clock-names:1: 'atclk' was expected
etm@3f740000: clock-names: ['apb_pclk', 'clk_cs', 'cs_src'] is too long
Link: https://lore.kernel.org/r/20231221092824.1169453-1-chunyan.zhang@unisoc.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
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Add basic support for Unisoc's UMS9620, with this patch,
the board ums9620-2h10 can run into console.
Link: https://lore.kernel.org/r/20231218100234.1102916-4-chunyan.zhang@unisoc.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
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Added bindings for Unisoc's UMS9620-2H10 board and UMS9620 SoC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231218100234.1102916-3-chunyan.zhang@unisoc.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
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The UMS512 Socs have 8 cores contains 6 a55 and 2 a75.
modify the cpu nodes to correct information.
Fixes: 2b4881839a39 ("arm64: dts: sprd: Add support for Unisoc's UMS512")
Cc: stable@vger.kernel.org
Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
Link: https://lore.kernel.org/r/20230711162346.5978-1-cixi.geng@linux.dev
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
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The QoS blocks saved/restored when toggling the PD_USB power domain are
clocked by ACLK_USB. Attempting to access these memory regions without
that clock running will result in an indefinite CPU stall.
The PD_USB node wasn't specifying this clock dependency, resulting in
hangs when trying to toggle the power domain (either on or off), unless
we get "lucky" and have ACLK_USB running for another reason at the time.
This "luck" can result from the bootloader leaving USB powered/clocked,
and if no built-in driver wants USB, Linux will disable the unused
PD+CLK on boot when {pd,clk}_ignore_unused aren't given. This can also
be unlucky because the two cleanup tasks run in parallel and race: if
the CLK is disabled first, the PD deactivation stalls the boot. In any
case, the PD cannot then be reenabled (if e.g. the driver loads later)
once the clock has been stopped.
Fix this by specifying a dependency on ACLK_USB, instead of only
ACLK_USB_ROOT. The child-parent relationship means the former implies
the latter anyway.
Fixes: c9211fa2602b8 ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Cc: stable@vger.kernel.org
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Link: https://lore.kernel.org/r/20231216021019.1543811-1-CFSworks@gmail.com
[changed to only include the missing clock, not dropping the root-clocks]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The default strength is not enough to provide stable connection
under 3.3v LDO voltage.
Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
Cc: stable@vger.kernel.org # 6.6+
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The RK806 on the NanoPC-T6 can be used to power on/off the whole board.
Mark it as the system power controller.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Link: https://lore.kernel.org/r/20231216212134.23314-1-sigmaris@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Perform the following cleanups on a previous patch:
- indent lines after "gpio-line-names"
- fix D0-D8 -> D0-D7
- sort phandle references
Fixes: c45de75d7a9a ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s")
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Cool Pi CM5 EVB works as a mother board connect with CM5.
CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S
CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header
Signed-off-by: Andy Yan <andyshrk@163.com>
Link: https://lore.kernel.org/r/20231212124407.1897604-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add Cool Pi CM5, a board powered by RK3588
CM5 EVB works with a mother board connect with
CM5
Signed-off-by: Andy Yan <andyshrk@163.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231212124340.1897502-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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CoolPi 4B is a rk3588s based SBC.
Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header
Signed-off-by: Andy Yan <andyshrk@163.com>
arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B
Link: https://lore.kernel.org/r/20231212124253.1897438-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add Cool Pi 4B, a SBC powered by RK3588S
Signed-off-by: Andy Yan <andyshrk@163.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231212124237.1897378-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add vendor prefix for Cool Pi(https://cool-pi.com/)
Signed-off-by: Andy Yan <andyshrk@163.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231212124223.1897314-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add names to the pins of the general-purpose expansion header as given
in the Radxa GPIO page[1] following the conventions in the kernel
documentation[2] to make it easier for users to correlate the pins with
functions when using utilities such as 'gpioinfo'.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Link: https://lore.kernel.org/r/20231213160556.14424-1-twoerner@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This should be a per board property, should not be put in
a soc core dtsi.
And when this property convert from default-sample-phase
in linux-5.7 by commit 8a385eb57296 ("ARM: dts: rockchip: fix
rockchip,default-sample-phase property names"), the emmc
on rk3036 kylin board get a initialising error:
[ 4.512797] Freeing unused kernel memory: 8192K
[ 4.519500] mmc_host mmc1: Bus speed (slot 0) = 37125000Hz (slot req 37500000Hz, actual 37125000HZ div = 0)
[ 4.530971] mmc1: error -84 whilst initialising MMC card
[ 4.537277] Run /init as init process
[ 4.550932] mmc_host mmc1: Bus speed (slot 0) = 300000Hz (slot req 300000Hz, actual 300000HZ div = 0)
[ 4.664717] mmc_host mmc1: Bus speed (slot 0) = 37125000Hz (slot req 37500000Hz, actual 37125000HZ div = 0)
[ 4.676156] mmc1: error -84 whilst initialising MMC card
I think the reason why the emmc on rk3036 kylin board was able
to work before linux-5.7 was that the illegal property was not
correctly identified by the rockchip dw_mmc driver.
Fixes: faea098e1808 ("ARM: dts: rockchip: add core rk3036 dtsi")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20231218105523.2478315-4-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add stdout-path to get a uart console when system boot.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20231218105523.2478315-3-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 updates for v6.8
Support is added for the new Snapdragon 8 Gen 3 mobile platform, with
support for the MTP and QRD development devices, the new Snapdragon X
Elite compute platform with QCP and CRD development/references devices,
the QCS6590/QCM6490 platform with support for the IDP development device
and the Robotics RB3gen2 board, the Huawei Honor 5X/GR5 handset
built on MSM8939, and Xiaomi Pad 6 on SM8250.
On IPQ5018 and IPQ6018 platform support for CPUfreq, USB, and one
additional QUP SPI controller is added.
CPU OPP tables are selectively enabled based on fuses, for both IPQ5332
and IPQ6018. IPQ6018 gains description of a few more SPI and UART nodes.
Common elements of the IPQ9574 RDP boards are refactored into a common
include file. IPQ9574 also gains description of its LEDs and WPS
busttons.
MSM8916 finally gets the DSP-based audio described, and this is enabled
for a variety of boards. Acer Iconia Talk S and Loncheer L8910 gains
notification LED, battery and charger support is added to Loncheer
L8150, and GPU is enabled for Samsung Galaxy Tab A.
Similariy DSP-based audio is added on MSM8939, the BAM-DMUX support is
enabled as well. The Longcheer L9100 gains RGB notification LED support,
and the wireless subsystem is enabled.
Missing SPI controllers are described on MSM8953. On MSM8996 the MPM is
enabled, to allow using wakeup interrupts. Interconnect providers, MPM
and display are added to QCM2290.
UFS, remoteprocs and WiFi is enabled for Fairphone FP5.
On Fairphone FP3 audio, WiFi and Bluetooth are enabled.
On the Robotics RB1, HDMI and the CAN bus controller are added. On
Robotics RB2 Bluetooth, the modem remoteproc and WiFi are enabled.
Bluetooth is enabled on the Robotics RB5.
On SA8775P tsens and thermal is added, as well as the random number
generator.
Sound and RTC support is added for the Acer Aspire 1.
On SC7280 DeviceTree is refactored, in order to allow non-Chrome devices
to inherit the base dtsi. Support for UFS, crypto, TrustZone based
remoteprocs, the Camera Control Interface (CCI) and random number
generator support are added. Additionally a variety of smaller fixes are
introduced.
A variety of fixes are introduced for SC8180X, in particular missing
power-domains and interconnects.
On SC8280XP the camera clock controller is added, and a number of
smaller fixes are introduced.
The display subsystem in SDM670 is described.
On SDX75 interconnect providers are added, as is USB3 and the related
PHY, which is then enabled on the IDP device.
On SM6115 interconnect providers are added and existing clients are
wired up. A UART controller is added as well.
The MPM is added, to provide wakeup interrutps, on SM6375. The modem
subsystem, and WiFi are enabled on Sony Xperia 10 IV, a few regulator
supplies are corrected.
On SM8150 the DisplayPort controller is added, for USB Type-C output,
which together with the addition of HDMI is described on the HDK board.
GPU and random number generator support are added to SM8450, and enabled
on the HDK board.
On SM8550 GPU, IPA, random number generator, missing SoundWire ports are
added, and enabled on both MTP and QRD devices.
Additionally a large number of smaller functional and DeviceTree binding
validation issues are corrected across a variety of platforms.
* tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (288 commits)
arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting
arm64: dts: qcom: sc8180x: Describe the GIC redistributor
arm64: dts: qcom: sc8180x: Add interconnects to UFS
arm64: dts: qcom: sc8180x: Add missing MDP clocks
arm64: dts: qcom: sc8180x: Add UFS GDSC
arm64: dts: qcom: sc7280*: move MPSS and WPSS memory to dtsi
arm64: dts: qcom: sc7280: Rename reserved-memory nodes
arm64: dts: qcom: sc7280: Remove unused second MPSS reg
arm64: dts: qcom: sdm670: add display subsystem
arm64: dts: qcom: sm8150-hdk: enable DisplayPort and USB-C altmode
arm64: dts: qcom: sm8150: add USB-C ports to the OTG USB host
arm64: dts: qcom: sm8150: add USB-C ports to the USB+DP QMP PHY
arm64: dts: qcom: sm8150: add DisplayPort controller
arm64: dts: qcom: sm8150-hdk: fix SS USB regulators
arm64: dts: qcom: sm8150-hdk: enable HDMI output
arm64: dts: qcom: sm8150: make dispcc cast minimal vote on MMCX
arm64: dts: qcom: sm8650: add fastrpc-compute-cb nodes
arm64: dts: qcom: sm8550-qrd: add PM8010 regulators
arm64: dts: qcom: sm8550-mtp: Add pm8010 regulators
arm64: dts: qcom: qcm2290: Hook up MPM
...
Link: https://lore.kernel.org/r/20231219145402.874161-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.8
StarFive:
Key peripheral support for the jh7100 that depended on the non-standard
non-coherent DMA operations, namely mmc, sdcard and sdio wifi. This
platform has long been supported out of tree by Emil and Ubuntu etc ship
images for it, so having mainline support for a wider range of
peripherals (at last) is great.
Microchip:
The flash used by Auto Update support and the corresponding QSPI
controller are added. On publicly available Icicle kits this flash is
not usable (engineering sample silicon issues) but in the future Icicle
kits will be available that have production silicon.
T-Head:
Jisheng is busy with RL this cycle and hence T-Head appears here. The
Lichee Pi and BeagleV both grow eMMC and uSD support.
Sopgho:
Support for the Huashan Pi and the cv1812h SoC it uses. The cv1812h is
almost identical to the existing cv1800b SoC. These SoCs are intended
for use in IP camera type systems but also appear on SBCs, with the last
digit denoting the amount integrated DDR3 the device has. The difference
between the cv1812h and the existing cv180x devices appears to be the
addition of video output interfaces.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: Enable SDIO wifi on JH7100 boards
riscv: dts: starfive: Enable SD-card on JH7100 boards
riscv: dts: starfive: Add JH7100 MMC nodes
riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
riscv: dts: starfive: Add JH7100 cache controller
riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs
riscv: dts: starfive: Group tuples in interrupt properties
riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
riscv: dts: microchip: add the mpfs' system controller qspi & associated flash
riscv: dts: sophgo: add Huashan Pi board device tree
riscv: dts: sophgo: add initial CV1812H SoC device tree
riscv: dts: sophgo: cv18xx: Add gpio devices
riscv: dts: sophgo: Separate compatible specific for CV1800B soc
dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
dt-bindings: timer: Add SOPHGO CV1812H clint
dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
Link: https://lore.kernel.org/r/20231221-skimmed-boxy-b78aed8afdc4@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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