summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2014-06-04drm/nouveau: replace drm_get_connector_name() with direct name field useJani Nikula7-11/+11
Generated using semantic patches: @@ expression E; @@ - drm_get_connector_name(&E) + E.name @@ expression E; @@ - drm_get_connector_name(E) + E->name v2: Turn drm_get_connector_name(&E) into E.name instead of &(E)->name. Acked-by: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-06-04drm/i915: replace drm_get_connector_name() with direct name field useJani Nikula12-31/+31
Generated using semantic patches: @@ expression E; @@ - drm_get_connector_name(&E) + E.name @@ expression E; @@ - drm_get_connector_name(E) + E->name v2: Turn drm_get_connector_name(&E) into E.name instead of &(E)->name. Acked-by: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-06-04staging: imx-drm-core: replace drm_get_connector_name() with direct name ↵Jani Nikula1-1/+1
field use Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name Acked-by: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-06-04drm/qxl: use surface_id 0 for primary surface on all monitorsDavid Mansfield1-0/+4
spice-server and downstream code expect that the primary surface will always have surface_id = 0, while in reality, once allocated, the surface_id in qxl.ko is NEVER 0. In a dual head environment, all monitors render portions of the primary surface. However, when the monitor config events are generated and sent, the primary surface is only mapped to the correct identifier (i.e. 0) for the primary head (where crtc index is 0). The fix is to look at the "primary" flag in the bo and always use id 0, irrespective of which head is being configured. [airlied: qxl hw really needs to be fixed to scanout surfaces] Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-06-04drm/radeon: rework page flip handling v4Christian König3-112/+147
Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling v4: update crtc->primary->fb when the flip actually happens Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-06-04Revert "drm/radeon: rework page flip handling v3"Dave Airlie3-150/+115
This reverts commit 1aab5514ca9604e0263f658a067da0189c86a35b. Apply the fixed up version instead.
2014-06-03Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie40-607/+1135
into drm-next Highlights: - GPUVM opimtizations - HDMI audio cleanups - Deep color HDMI support - more bug fixes, cleanups * 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux: (29 commits) drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color. drm/edid: Parse and handle HDMI deep color modes. drm/radeon: Limit hdmi deep color bit depth to 12 bpc. drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2) drm/radeon: fix pll setup for hdmi deep color (v7) drm/radeon: use hw cts/n values for deep color drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi drm/radeon/atom: fix dithering on certain panels drm/radeon: optimize CIK VM handling v2 drm/radeon: optimize SI VM handling drm/radeon: add define for flags used in R600+ GTT drm/radeon: rework page flip handling v3 drm/radeon: separate vblank and pflip crtc handling drm/radeon: split page flip and pending callback drm/radeon: remove drm_vblank_get|put from pflip handling drm/radeon: remove (pre|post)_page_flip callbacks drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices drm/radeon: fix typo in radeon_connector_is_dp12_capable() radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770 vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled ...
2014-06-03drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.Mario Kleiner1-0/+8
The Sony PVM-2541A OLED high precision color display supports both 10 bpc and 12 bpc hdmi deep color input, but its edid does not signal any deep color support. Add a quirk to force it being treated as a 12 bpc panel. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-03drm/edid: Parse and handle HDMI deep color modes.Mario Kleiner2-2/+113
Check the HDMI cea block for deep color mode bits. If available, assign the highest supported bpc for a hdmi display, corresponding to the given deep color modes. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-03drm/radeon: Limit hdmi deep color bit depth to 12 bpc.Mario Kleiner1-0/+25
DCE-4/5/6 can't support more than 12 bpc deep color over hdmi, so clamp to 12 bpc when a hdmi deep color capable display is connected. This even makes sense on DCE-8+, which could do up to 16 bpc, as driving with more than 12 bpc would only waste video bandwidth as long as we don't support framebuffers with more than 12 bpc depth. On pre-DCE4 we clamp hdmi bit depth to 8 bpc, as those asics don't support hdmi deep color. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-03drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)Alex Deucher2-1/+32
Program HDMI_CONTROL to send general control packets for hdmi deep color mode signalling at every video frame if bpc > 8. This is only supported on evergreen / DCE-4 and later. v2: rebase Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-03drm/radeon: fix pll setup for hdmi deep color (v7)Alex Deucher1-9/+36
Need to adjust the pll up for deep color modes. Additionally, the atom bpc defines were wrong in certain cases. v2: set the adjusted clock to the pll clock for hdmi deep color. This fixes display and audio issues with deep color as reported by Andy Furniss <adf.lists@gmail.com> v3: set crtc_clock as well v4: setcrtcinfo on the adjusted mode v5: just use the adjusted clock for setting the pll v6: only use the adjusted clock for hdmi v7: only DCE5 and DCE6 and bpc > 8 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: use hw cts/n values for deep colorAlex Deucher1-3/+15
I'm not really sure how these should be calculated for deep color. The hw generated values seem to work. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmiAlex Deucher1-22/+26
May fix display issues with non-HDMI displays. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-06-02drm/radeon/atom: fix dithering on certain panelsAlex Deucher1-1/+4
We need to specify the encoder mode as LVDS for eDP when using the Crtc_Source atom table in order to properly set up the FMT hardware. bug: https://bugs.freedesktop.org/show_bug.cgi?id=73911 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-06-02drm/radeon: optimize CIK VM handling v2Christian König1-1/+20
Fill VM page tables from the GART page table if applicable. v2: fix copy&paste error Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: optimize SI VM handlingChristian König1-1/+19
Fill VM page tables from the GART page table if applicable. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: add define for flags used in R600+ GTTChristian König2-8/+5
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: rework page flip handling v3Christian König3-115/+150
Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: separate vblank and pflip crtc handlingChristian König8-26/+56
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: split page flip and pending callbackChristian König8-15/+88
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: remove drm_vblank_get|put from pflip handlingChristian König1-17/+0
We activate the VBLANK irq manually anyway, so this is unnecessary. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: remove (pre|post)_page_flip callbacksChristian König7-128/+2
They are doing the same on all generations anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devicesAlex Deucher1-2/+15
Only DCE5+ asics support DP 1.2. Noticed by ArtForz on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-06-02drm/radeon: fix typo in radeon_connector_is_dp12_capable()Alex Deucher1-1/+1
We were checking the ext clock rather than the display clock. Noticed by ArtForz on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-06-02radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770Émeric MASCHINO1-3/+0
Removes useless quirk a7f465f73363fce409870f62173d518b1bc02ae6 introduced with fdo #7770 as a failed attempt to minimize stability issues with hp zx1 chipset/ ATI FireGL X1 graphics adapter configuration (see http://marc.info/?l=linux-ia64&m=140077543819871&w=2 for details/reason) Signed-off-by: Émeric MASCHINO <emeric.maschino@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02vgaswitcheroo: switch the mux to the igp on power down when runpm is enabledAlex Deucher1-1/+2
Avoids blank screens on muxed systems when runpm is active. bug: https://bugs.freedesktop.org/show_bug.cgi?id=75917 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-06-02drm/radeon: use NULL instead of zero in clearstate headersMichele CURTI3-8/+8
Signed-off-by: Michele Curti <michele.curti@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: use NULL instead of zero in object functionsMichele CURTI2-2/+2
Signed-off-by: Michele Curti <michele.curti@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon/hdmi: DCE2: simplify audio workaroundRafał Miłecki1-60/+22
Thanks to advanced RE of fglrx we finally know what exactly needs to be handled of AFMT change. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon/hdmi: DCE2: update setmodeRafał Miłecki2-37/+90
Recent RE efforts revealed ops performed by fglrx during HDMI setup. This mostly adds masks to r/w ops plus few single missing bits. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon/hdmi: DCE3: clean ACR controlRafał Miłecki2-3/+7
What initially seemed to be a typo in fglrx (using register 0x740c instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and CRC registers swapped which explains why we needed WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); This has been tested for possible regressions on DCE3 HD3470 (RV620). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon/hdmi: use separated file for DCE 3.1/3.2 codeRafał Miłecki5-141/+263
DCE 3.1 and 3.2 should be programmed in a different way than DCE 2 and DCE 3. The order of setting registers and sets of registers are different. It's still unsure how we will handle DCE 3.1 vs. DCE 3.2, since they have few differences as well. For now separate DCE 2 and DCE 3 path, so we can work on it without a risk of breaking DCE 3.1+. This has been tested for possible regressions on DCE32 HD4550 (RV710). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2Christian König7-1/+9
This patch makes it possible to decide how many address bits are spend on the page directory vs the page tables. v2: remove unintended change Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: add large PTE support for NI, SI and CIK v5Christian König5-9/+98
This patch implements support for VRAM page table entry compression. PTE construction is enhanced to identify physically contiguous page ranges and mark them in the PTE fragment field. L1/L2 TLB support is enabled for 64KB (SI/CIK) and 256KB (NI) PTE fragments, significantly improving TLB utilization for VRAM allocations. Linear store bandwidth is improved from 60GB/s to 125GB/s on Pitcairn. Unigine Heaven 3.0 sees an average improvement from 24.7 to 27.7 FPS on default settings at 1920x1200 resolution with vsync disabled. See main comment in radeon_vm.c for a technical description. v2 (chk): rebased and simplified. v3 (chk): add missing hw setup v4 (chk): rebased on current drm-fixes-3.15 v5 (chk): fix comments and commit text Signed-off-by: Jay Cornwall <jay@jcornwall.me> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02drm/radeon: add a i2c bus mutexAlex Deucher4-8/+37
The i2c and aux buses use the same pads so add a mutex to protect access to the pads. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
2014-06-02drm/msm: use correct gfp flag for vram allocationRob Clark1-1/+1
We want at least __GFP_WAIT, otherwise dma-mapping tries to use coherent pool rather than CMA pool. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-06-02drm/msm/mdp5: fix error return valueRob Clark1-6/+16
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-06-02drm/msm: remove redundant private plane cleanupRob Clark2-4/+0
Now that drm core knows about private planes, it cleans them up for us. Trying to do this twice results in badness. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-06-02drm/msm: add perf logging debugfsRob Clark7-5/+436
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-06-02drm/msm: add rd logging debugfsRob Clark7-1/+392
To ease debugging, add debugfs file which can be cat/tail'd to log submits, along with fence #. If GPU hangs, you can look at 'gpu' debugfs file to find last completed fence and current register state, and compare with logged rd file to narrow down the DRAW_INDX which triggered the GPU hang. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-06-02Merge tag 'drm-intel-next-2014-05-23' of ↵Dave Airlie49-1771/+6778
git://anongit.freedesktop.org/drm-intel into drm-next - prep refactoring for execlists (Oscar Mateo) - corner-case fixes for runtime pm (Imre) - tons of vblank improvements from Ville - prep work for atomic plane/sprite updates (Ville) - more chv code, now almost complete (tons of different people) - refactoring and improvements for drm_irq.c merged through drm-intel-next - g4x/ilk reset improvements (Ville) - removal of encoder->mode_set - moved audio state tracking into pipe_config - shuffled fb pinning out of the platform crtc modeset callbacks into core code - userptr support (Chris) - OOM handling improvements from Chris, with now have a neat oom notifier which jumps additional debug information. - topdown allocation of ppgtt PDEs (Ben) - fixes and small improvements all over * tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel: (187 commits) drm/i915: Kill private_default_ctx off drm/i915: s/i915_hw_context/intel_context drm/i915: Split the ringbuffers from the rings (3/3) drm/i915: Split the ringbuffers from the rings (2/3) drm/i915: Split the ringbuffers from the rings (1/3) drm/i915: s/intel_ring_buffer/intel_engine_cs drm/i915: disable GT power saving early during system suspend drm/i915: fix possible RPM ref leaking during RPS disabling drm/i915: remove user GTT mappings early during runtime suspend drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk drm/i915: Fix gen2 and hsw+ scanline counter drm/i915: Draw a picture about video timings drm/i915: Improve gen3/4 frame counter drm/i915: Add a small adjustment to the pixel counter on interlaced modes drm/i915: Hold CRTC lock whilst freezing the planes drm/i915: Only discard backing storage on releasing the last ref drm/i915: Wait for pending page flips before enabling/disabling the primary plane drm/i915: grab the audio power domain when enabling audio on HSW+ drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off drm/i915: move bsd dispatch index somewhere better ...
2014-06-02imx-drm: imx-tve: remove unused variableVincent Stehlé1-1/+0
Commit f9b0e251dfbf 'drm: make mode_valid callback optional' left variable ret unused; remove it. This fixes the following compilation warning: drivers/staging/imx-drm/imx-tve.c: In function ‘imx_tve_connector_mode_valid’: drivers/staging/imx-drm/imx-tve.c:252:6: warning: unused variable ‘ret’ [-Wunused-variable] Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02drm: Missed clflushopt in drm_clflush_virt_rangeRoss Zwisler1-1/+1
With this commit: 2a0788dc9bc4 x86: Use clflushopt in drm_clflush_virt_range If clflushopt is available on the system, we use it instead of clflush in drm_clflush_virt_range. There were two calls to clflush in this function, but only one was changed to clflushopt. This patch changes the other clflush call to clflushopt. Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Reported-by: Matthew Wilcox <matthew.r.wilcox@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: dri-devel@lists.freedesktop.org Cc: H Peter Anvin <h.peter.anvin@intel.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02drm/plane: Fix a couple of checkpatch warningsThierry Reding1-3/+3
Code should be indented using tabs rather than spaces (see CodingStyle) and the canonical form to declare a constant static variable is using "static const" rather than "const static". Fixes the following warnings from checkpatch: $ scripts/checkpatch.pl -f drivers/gpu/drm/drm_plane_helper.c WARNING: storage class should be at the beginning of the declaration #40: FILE: drivers/gpu/drm/drm_plane_helper.c:40: +const static uint32_t safe_modeset_formats[] = { WARNING: please, no spaces at the start of a line #41: FILE: drivers/gpu/drm/drm_plane_helper.c:41: + DRM_FORMAT_XRGB8888,$ WARNING: please, no spaces at the start of a line #42: FILE: drivers/gpu/drm/drm_plane_helper.c:42: + DRM_FORMAT_ARGB8888,$ Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02drm/plane: Fix sparse warningsThierry Reding2-1/+2
Include the drm_plane_helper.h header file to fix the following sparse warnings: CHECK drivers/gpu/drm/drm_plane_helper.c drivers/gpu/drm/drm_plane_helper.c:102:5: warning: symbol 'drm_primary_helper_update' was not declared. Should it be static? drivers/gpu/drm/drm_plane_helper.c:219:5: warning: symbol 'drm_primary_helper_disable' was not declared. Should it be static? drivers/gpu/drm/drm_plane_helper.c:233:6: warning: symbol 'drm_primary_helper_destroy' was not declared. Should it be static? drivers/gpu/drm/drm_plane_helper.c:241:30: warning: symbol 'drm_primary_helper_funcs' was not declared. Should it be static? drivers/gpu/drm/drm_plane_helper.c:259:18: warning: symbol 'drm_primary_helper_create_plane' was not declared. Should it be static? Doing that makes gcc complain as follows: CC drivers/gpu/drm/drm_plane_helper.o drivers/gpu/drm/drm_plane_helper.c:260:19: error: conflicting types for 'drm_primary_helper_create_plane' struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev, ^ In file included from drivers/gpu/drm/drm_plane_helper.c:29:0: include/drm/drm_plane_helper.h:42:19: note: previous declaration of 'drm_primary_helper_create_plane' was here struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev, ^ drivers/gpu/drm/drm_plane_helper.c: In function 'drm_primary_helper_create_plane': drivers/gpu/drm/drm_plane_helper.c:274:11: warning: assignment discards 'const' qualifier from pointer target type formats = safe_modeset_formats; ^ In file included from include/linux/linkage.h:6:0, from include/linux/kernel.h:6, from include/drm/drmP.h:45, from drivers/gpu/drm/drm_plane_helper.c:27: drivers/gpu/drm/drm_plane_helper.c: At top level: drivers/gpu/drm/drm_plane_helper.c:289:15: error: conflicting types for 'drm_primary_helper_create_plane' EXPORT_SYMBOL(drm_primary_helper_create_plane); ^ include/linux/export.h:57:21: note: in definition of macro '__EXPORT_SYMBOL' extern typeof(sym) sym; \ ^ drivers/gpu/drm/drm_plane_helper.c:289:1: note: in expansion of macro 'EXPORT_SYMBOL' EXPORT_SYMBOL(drm_primary_helper_create_plane); ^ In file included from drivers/gpu/drm/drm_plane_helper.c:29:0: include/drm/drm_plane_helper.h:42:19: note: previous declaration of 'drm_primary_helper_create_plane' was here struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev, ^ Which can easily be fixed by making the signatures of the implementation and the prototype match. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02drm/exynos: Fix double locks at PM resumeTakashi Iwai1-1/+1
The recent commit [3ea87855: drm/helper: lock all around force mode restore] introduced drm_modeset_lock_all() in drm_helper_resume_force_mode() itself, while exynos driver takes this lock before calling it. Move the function call outside the lock for avoiding a deadlock. Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02drm/ast: Fix double lock at PM resumeTakashi Iwai1-2/+0
The recent commit [3ea87855: drm/helper: lock all around force mode restore] introduced drm_modeset_lock_all() in drm_helper_resume_force_mode() itself, while ast driver still takes this lock before calling it. Remove the caller side lock for avoid a fatal deadlock. Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02drm/dp-helper: Deprecate old i2c-over-dp_aux heleprsDaniel Vetter1-0/+4
Only gma500 is still using this, once that's converted we can kill all this code. If that conversion doesn't happen soonish I think we should just move this helper code into the gma500 driver itself to avoid abuse from new drivers. Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02drm/exynos: consider deferred probe caseInki Dae8-75/+303
This patch makes sure that exynos drm framework handles deferred probe case correctly. Sub drivers could be probed before resources, clock, regulator, phy or panel, are ready for them so we should make sure that exynos drm core waits until all resources are ready and sub drivers are probed correctly. Chagelog v2: - Make sure that exynos drm core tries to bind sub drivers only in case that they have a pair: crtc and encoder/connector components should be a pair. - Remove unnecessary patch: drm/exynos: mipi-dsi: consider panel driver-deferred probe - Return error type correctly. Signed-off-by: Inki Dae <inki.dae@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>