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2018-05-19drm/amdgpu: flag Vega20 as experimentalAlex Deucher1-6/+6
Must set amdgpu.exp_hw_support=1 on the kernel command line in grub to enable support. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu: Add vega20 pci idsFeifei Xu1-0/+7
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu: Switch to use df_v3_6_funcs for vega20 (v2)Feifei Xu1-1/+5
v2: fix whitespace (Alex) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/df: implement df v3_6 callback functions (v2)Feifei Xu3-1/+158
New df helpers for 3.6. v2: switch to using df 3.6 headers (Alex) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu: add df 3.6 headersAlex Deucher3-0/+107
Needed for vega20. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:Enable UVD/VCE for Vega20James Zhu1-4/+2
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default. So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled at this moment. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:Enable 2nd instance queue maping for uvd 7.2James Zhu1-4/+10
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD instance presents. there is two rings for uvd decode, and 4 rings for uvd encode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2James Zhu1-2/+10
For Vega20, the 2nd instance uvd IRQ using different client id. Enable the 2nd instance IRQ for uvd 7.2 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:Add IH client ID for the 2nd UVDJames Zhu1-0/+1
For Vega20, there are two UVD hardware. Need add the 2nd IH client ID for the 2nd UVD Hardware. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:Enable the 2nd instance for uvdJames Zhu2-15/+22
For Vega20, set num of uvd instance to 2, to enble 2nd instance. The IB test build-in registers need update for vega20 2nd instance. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:increase 3 rings for AMDGPU_MAX_RINGSJames Zhu1-1/+1
For Vega20, there are two UVD Hardware. One more UVD hardware adds one decode ring and two encode rings. So AMDGPU_MAX_RINGS need increase by 3. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:Restruct uvd.inst to support multiple instancesJames Zhu5-590/+660
Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu/vg20:Restruct uvd to support multiple uvdsJames Zhu9-194/+205
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amdgpu: Disable ip modules that are not ready yetFeifei Xu1-5/+9
Please enable above ips on soc15.c when they're available. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-19drm/amd/powerplay: update vega20 cg flags (v2)Evan Quan1-1/+17
v2: remove duplicate flag. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18drm/tegra: vic: Track interface versionThierry Reding1-0/+5
Set the interface version implemented by the VIC module. This allows userspace to pass the correct command stream when programming the VIC module. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18drm/tegra: gr3d: Track interface versionThierry Reding1-3/+25
Set the interface version implemented by the gr3d module. This allows userspace to pass the correct command stream when programming the gr3d module. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18drm/tegra: gr2d: Track interface versionThierry Reding1-2/+20
Set the interface version implemented by the gr2d module. This allows userspace to pass the correct command stream when programming the gr2d module. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18drm/tegra: Track client versionThierry Reding1-0/+1
Userspace needs to know the version of the interface implemented by a client so it can create the proper command streams. Allow individual drivers to store this version along with the client so that it can be returned to userspace upon opening a channel. Acked-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18drm/tegra: dc: Support rotation propertyThierry Reding3-1/+28
Currently only the DRM_MODE_REFLECT_Y rotation is supported. The driver already supports reflection on the Y axis via a custom flag which is not very useful because it requires custom userspace. Add the standard rotation property that supports 0 degree rotation and Y axis reflection for primary and overlay planes to provide a better interface than the custom flag. v2: keep custom flag for ABI compatibility (Dmitry) Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18drm/tegra: gem: Fill in missing export infoThierry Reding1-0/+2
Set the owner and name of the exported DMA-BUF in addition to the already filled-in fields. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18drm/tegra: Use proper arguments for DRM_TEGRA_CLOSE_CHANNEL IOCTLThierry Reding1-1/+1
A separate data structure exists for the DRM_TEGRA_CLOSE_CHANNEL IOCTL, but it is currently unused. The IOCTL was using the data structure for the DRM_TEGRA_OPEN_CHANNEL IOCTL. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18gpu: host1x: Use not explicitly sized typesThierry Reding3-9/+10
The number of words and the offset in a gather don't need to be explicitly sized, so make them unsigned int instead. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18gpu: host1x: Rename relocarray -> relocs for consistencyThierry Reding3-7/+7
All other array variables use a plural, and this is the only one using the *array suffix. This is confusing, so rename it for consistency. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18gpu: host1x: Drop unnecessary host1x argumentThierry Reding4-13/+13
Functions taking a pointer to a host1x syncpoint as an argument don't need to specify a pointer to a host1x instance because it can be obtained from the syncpoint. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18gpu: host1x: Cleanup loop variable usageThierry Reding4-5/+5
Use unsigned int where possible and don't unnecessarily initialize the loop variable. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18gpu: host1x: Store pointer to client in jobsThierry Reding4-5/+7
Rather than storing some identifier derived from the application context that can't be used concretely anywhere, store a pointer to the client directly so that accesses can be made directly through that client object. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18gpu: host1x: Remove wait check supportThierry Reding9-234/+14
The job submission userspace ABI doesn't support this and there are no plans to implement it, so all of this code is dead and can be removed. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18drm/amdgpu: conditionally compile amdgpu's amdkfd filesOded Gabbay3-9/+63
In case CONFIG_HSA_AMD is not chosen, there is no need to compile amdkfd files that reside inside amdgpu dirver. In addition, because amdkfd depends on x86_64 architecture and amdgpu is not, compiling amdkfd files under i386 architecture can cause compiler errors and warnings. This patch modifies amdgpu's makefile to build amdkfd files only if CONFIG_HSA_AMD is chosen. The only file to be compiled unconditionally is amdgpu_amdkfd.c There are stub functions that are compiled only if amdkfd is not compiled. In that case, calls from amdgpu driver proper will go to those functions instead of the real functions. v2: instead of using function pointers, use stub functions v3: initialize kgd2kfd to NULL in case amdkfd is not compiled Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
2018-05-18drm/rockchip: rockchip_drm_fb -> drm_framebufferDaniel Stone3-40/+21
Now that rockchip_drm_fb is just a wrapper around drm_framebuffer, we can remove it. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Acked-by: Heiko Stübner <heiko@sntech.de> Tested-by: Heiko Stübner <heiko@sntech.de> Cc: Sandy Huang <hjc@rock-chips.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-5-daniels@collabora.com
2018-05-18drm/rockchip: Place GEM BOs in drm_framebufferDaniel Stone1-30/+6
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle and destroy functions the same as the GEM framebuffer helper, we can reuse those. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Acked-by: Heiko Stübner <heiko@sntech.de> Tested-by: Heiko Stübner <heiko@sntech.de> Cc: Sandy Huang <hjc@rock-chips.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-4-daniels@collabora.com
2018-05-18drm/mtk: mtk_drm_fb -> drm_framebufferDaniel Stone1-26/+14
Now that mtk_drm_fb is an empty wrapper around drm_framebuffer, we can just delete it. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/20180518134705.12533-3-daniels@collabora.com
2018-05-18drm/mtk: Move GEM BO to drm_framebufferDaniel Stone3-35/+6
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle and destroy functions the same as the GEM framebuffer helper, we can reuse those. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/20180518134705.12533-2-daniels@collabora.com
2018-05-18drm/mtk: Remove impossible internal errorDaniel Stone1-5/+0
We cannot create a framebuffer with no objects, so there's no point testing for it. v2: Remove the error entirely. (Sean, CK, Thierry) Signed-off-by: Daniel Stone <daniels@collabora.com> Acked-by: Thierry Reding <treding@nvidia.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: CK Hu <ck.hu@mediatek.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/20180518134705.12533-1-daniels@collabora.com
2018-05-18drm/msm: Move GEM BOs to drm_framebufferDaniel Stone1-43/+11
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle function the same as the GEM framebuffer helper, we can reuse that. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Cc: Rob Clark <robdclark@gmail.com> Cc: linux-arm-msm@vger.kernel.org Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-21-daniels@collabora.com
2018-05-18drm/gma500: Move GEM BO to drm_framebufferDaniel Stone6-60/+20
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle and destroy functions the same as the GEM framebuffer helper, we can reuse those. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-20-daniels@collabora.com
2018-05-18drm/armada: Move GEM BO to drm_framebufferDaniel Stone2-21/+5
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle and destroy functions the same as the GEM framebuffer helper, we can reuse those. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Russell King <linux@armlinux.org.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-19-daniels@collabora.com
2018-05-18drm/virtio: Place GEM BOs in drm_framebufferDaniel Stone4-32/+11
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle and destroy functions the same as the GEM framebuffer helper, we can reuse those. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: virtualization@lists.linux-foundation.org Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-3-daniels@collabora.com
2018-05-18drm/cirrus: cirrus_framebuffer -> drm_framebufferDaniel Stone4-36/+25
Now cirrus_framebuffer is just an empty wrapper around drm_framebuffer, we can drop it. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: virtualization@lists.linux-foundation.org Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-2-daniels@collabora.com
2018-05-18drm/cirrus: Place GEM BOs in drm_framebufferDaniel Stone4-28/+10
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle and destroy functions the same as the GEM framebuffer helper, we can reuse those. Signed-off-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: virtualization@lists.linux-foundation.org Link: https://patchwork.freedesktop.org/patch/msgid/20180330141138.28987-1-daniels@collabora.com
2018-05-18drm/etnaviv: replace license text with SPDX tagsLucas Stach23-296/+40
This replaces the repetitive GPL-2.0 license text in code and header files with the SPDX tags. Generated hardware headers aren't changed, as any changes there need to be done in the upstream rnndb repository. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-05-18drm/etnaviv: mmuv2: support 40 bit phys addressLucas Stach1-1/+4
MMUv2 supports up to 40 bits of physical address by folding the upper 8 bits into bits [4:11] of the PTE. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-05-18drm/etnaviv: mmuv2: allocate 2nd level page tables on demandLucas Stach1-28/+33
With etnaviv not being tied into the IOMMU framework anymore, the MMU functions will only be called under sleeping locks. Thus we are able to allocate the memory for the 2nd level page tables on demand without having to deal with memory allocation in atomic context. This speeds up driver intitialization on MMUv2 GPU cores, as we don't need to preallocate all the page table memory and also reduces memory consumption for most workloads, as most of them won't use the full GPU virtual address space. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-05-18drm/etnaviv: switch MMU page tables to writecombine memoryLucas Stach2-59/+49
We are likely to write multiple page entries at once and already ensure proper write buffer flushing before GPU submit, so this improves CPU time usage in the submit path without any downsides. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-05-18drm/etnaviv: remove register loggingLucas Stach5-67/+5
I'm not aware of any case where tracing GPU register manipulation at the kernel level would have been useful. It only adds more indirections and adds to the code size. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-05-18drm/etnaviv: remove cycling through MMU address spaceLucas Stach2-16/+1
This was useful on MMUv1 GPUs, which don't generate proper faults, when the GPU write caches weren't fully understood and not properly handled by the kernel driver. As this has been fixed for quite some time, the cycling though the MMU address space needlessly spreads out the MMU mappings. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-05-18drm/etnaviv: correct timeout calculationRussell King1-8/+17
The old way did clamp the jiffy conversion and thus caused the timeouts to become negative after some time. Also it didn't work with userspace which actually fills the upper 32bits of the 64bit timestamp value. clock_gettime() is 32-bit on 32-bit architectures. Using 64-bit timespec math, like we do in this commit, means that when a wrap occurs, the specified timeout goes into the past and we can't request a timeout in the future. As the Linux implementation of CLOCK_MONOTONIC is reasonable and starts at 0, the first such timer wrap will occur after approx. 68 years of system uptime. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-05-18drm/panel: simple: Fix data type in KEO TX31D200VM0BAA timingsStefan Agner1-2/+2
All values in a struct struct timing_entry (every entry in struct display_timing) require an integer. Choose the closest safe integer of 32. This avoids a warning seen with clang: drivers/gpu/drm/panel/panel-simple.c:1250:27: warning: implicit conversion from 'double' to 'u32' (aka 'unsigned int') changes value from 33.5 to 33 [-Wliteral-conversion] .vfront_porch = { 6, 21, 33.5 }, ~ ^~~~ drivers/gpu/drm/panel/panel-simple.c:1251:26: warning: implicit conversion from 'double' to 'u32' (aka 'unsigned int') changes value from 33.5 to 33 [-Wliteral-conversion] .vback_porch = { 6, 21, 33.5 }, ~ ^~~~ Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180419212003.8155-1-stefan@agner.ch
2018-05-18drm/panel: simple: AUO P320HVN03 uses SPWG data orderingLucas Stach1-1/+1
The patch adding support for the AUO P320HVN03 panel was written against a preliminary datasheet, which specified JEIDA data ordering. Testing with real hardware has shown that the actually used data ordering is SPWG. Fixes: 70c0d5b783f5 (drm/panel: simple: add support for AUO P320HVN03) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180411152741.22483-1-l.stach@pengutronix.de
2018-05-18drm/panel: simple: Add Innolux TV123WAM panel driver supportspanda@codeaurora.org1-0/+27
Add support for Innolux TV123WAM, which is a 12.3" eDP display panel with 2160x1440 resolution. Changes in v1: - Add the compatibility string, display_mode and panel_desc structures in alphabetical order (Sean Paul). Signed-off-by: Sandeep Panda <spanda@codeaurora.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526363564-13823-4-git-send-email-spanda@codeaurora.org
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 23:09:47 +0300