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2017-08-30PCI: dwc: Enable write permission for Class Code, Interrupt Pin updatesHou Zhiqiang1-0/+6
dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt Pin registers, but the fixes don't actually work because these registers are read-only. Enable write permission before updating the Class Code and Interrupt Pin. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: dwc: Add accessors for write permission of DBI read-only registersHou Zhiqiang2-3/+27
The read-only DBI registers can be written only when the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set. Add accessors to enable and disable write permission, and use them instead of accessing MISC_CONTROL_1_OFF directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: layerscape: Disable outbound windows configured by bootloaderHou Zhiqiang1-0/+17
Disable all the outbound windows to avoid one transaction hitting multiple outbound windows. dw_pcie_setup_rc() will reconfigure the outbound windows, which may conflict with windows configured by the bootloader. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: layerscape: Refactor ls1021_pcie_host_init()Hou Zhiqiang1-10/+1
ls1021_pcie_host_init() duplicated the code in the generic ls_pcie_host_init(). Call ls_pcie_host_init() instead of duplicating the code. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Move generic init functions earlier in fileHou Zhiqiang1-32/+32
We will use the generic ls_pcie_link_up() and ls_pcie_host_init() from device-specific routines. Move the generic functions earlier in the file so we won't need forward declarations. This is strictly a code move with no functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Add class code and multifunction fixups for ls1021aHou Zhiqiang1-0/+5
The current code depends on class code and multifunction fixups done by the bootloader. Perform these fixups in ls1021_pcie_host_init() to remove this dependency. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracketHou Zhiqiang1-1/+2
The STRFMR1 is not a DBI read-only register, so move it out from the write-enable bracket. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()Hou Zhiqiang1-0/+2
We called dw_pcie_setup_rc() from the ls1021a host init function, but not from the common ls_pcie_host_init() function, so platforms other than ls1021a still depended on initialization by the bootloader. Call dw_pcie_setup_rc() from ls_pcie_host_init() to reduce dependencies on the bootloader. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: rockchip: Umap IO space if probe failsJeffy Chen1-3/+5
Call pci_unmap_iospace() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Remove IRQ domain if probe failsJeffy Chen1-1/+3
Call irq_domain_remove() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Disable vpcie0v9 if resume_noirq failsJeffy Chen1-1/+4
Disable vpcie0v9 regulator if resume_noirq fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Clean up PHY if driver probe or resume failsShawn Lin1-17/+29
We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Factor out rockchip_pcie_deinit_phys()Shawn Lin1-14/+15
Factor out rockchip_pcie_deinit_phys() so it can be reused by rockchip_pcie_suspend_noirq() and rockchip_pcie_remove(). No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Factor out rockchip_pcie_disable_clocks()Shawn Lin1-16/+14
Factor out rockchip_pcie_disable_clocks() so it can be reused by other functions. No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path so it matches the other paths. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Factor out rockchip_pcie_enable_clocks()Shawn Lin1-45/+45
Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Factor out rockchip_pcie_setup_irq()Shawn Lin1-35/+47
Factor out rockchip_pcie_setup_irq() to prepare for future bug fixes. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expandersFabio Estevam1-2/+2
The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-08-29PCI: rockchip: Use PCI_NUM_INTXPaul Burton1-1/+1
Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Shawn Lin <shawn.lin@rock-chips.com>
2017-08-29PCI: rockchip: Explicitly request exclusive reset controlPhilipp Zabel1-7/+8
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-08-29dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY modelShawn Lin1-1/+6
Deprecate the legacy Rockchip PCIe PHY and encourage users to use per-lane PHY mode by setting #phy-cells to 1. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org>
2017-08-29dt-bindings: PCI: rockchip: Convert to per-lane PHY modelShawn Lin1-2/+23
Deprecate legacy PHY model and encourage per-lane PHY model. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org>
2017-08-29arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339Shawn Lin1-3/+5
Convert all RK3399 platforms to use per-lane PHY model in order to save more power by idling unused lane(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2017-08-29PCI: iproc: Work around Stingray CRS defectsOza Pawandeep1-1/+81
Configuration Request Retry Status ("CRS") completions are a required part of PCIe. A PCIe device may respond to config a request with a CRS completion to indicate that it needs more time to initialize. A Root Port that receives a CRS completion may automatically retry the request, or it may treat the request as a failed transaction. For a failed read, it will likely synthesize all 1's data, i.e., 0xffffffff, to complete the read to the CPU. CRS Software Visibility ("CRS SV") is an optional feature. Per PCIe r3.1, sec 2.3.2, if supported and enabled, a Root Port that receives a CRS completion for a config read of the Vendor ID will synthesize 0x0001 data (an invalid Vendor ID) instead of retrying or failing the transaction. The 0x0001 data makes the CRS completion visible to software, so it can perform other tasks while waiting for the device. The iProc "Stingray" PCIe controller does not support CRS completions correctly. From the Stingray PCIe Controller spec: 4.7.3.3. Retry Status On Configuration Cycle Endpoints are allowed to generate retry status on configuration cycles. In this case, the RC needs to re-issue the request. The IP does not handle this because the number of configuration cycles needed will probably be less than the total number of non-posted operations needed. When a retry status is received on the User RX interface for a configuration request that was sent on the User TX interface, it will be indicated with a completion with the CMPL_STATUS field set to 2=CRS, and the user will have to find the address and data values and send a new transaction on the User TX interface. When the internal configuration space returns a retry status during a configuration cycle (user_cscfg = 1) on the Command/Status interface, the pcie_cscrs will assert with the pcie_csack signal to indicate the CRS status. When the CRS Software Visibility Enable register in the Root Control register is enabled, the IP will return the data value to 0x0001 for the Vendor ID value and 0xffff (all 1’s) for the rest of the data in the request for reads of offset 0 that return with CRS status. This is true for both the User RX Interface and for the Command/Status interface. When CRS Software Visibility is enabled, the CMPL_STATUS field of the completion on the User RX Interface will not be 2=CRS and the pcie_cscrs signal will not assert on the Command/Status interface. The Stingray hardware never reissues configuration requests when it receives CRS completions. Contrary to what sec 4.7.3.3 above says, when it receives a CRS completion, it synthesizes 0xffff0001 data regardless of the address of the read or the value of the CRS SV enable bit. This is broken in two ways: 1) When CRS SV is disabled, the Root Port should never synthesize the 0x0001 value. If it receives a CRS completion, it should fail the transaction and synthesize all 1's data. 2) When CRS SV is enabled, the Root Port should only synthesize 0x0001 data if it receives a CRS completion for a read of the Vendor ID. If it receives a CRS completion for any other read, it should fail the transaction and synthesize all 1's data. This breaks pci_flr_wait(), which reads the Command register and expects to see all 1's data if the read fails because of CRS completions. On Stingray, it sees the incorrect 0xffff0001 data instead. It also breaks config registers that contain the 0xffff0001 value. If we read such a register, software can't distinguish a CRS completion from the actual value read from the device. On Stingray, if we read 0xffff0001 data, assume this indicates a CRS completion and retry the read for 500ms. If we time out, return all 1's (0xffffffff) data. Note that this corrupts registers that happen to contain 0xffff0001. Stingray advertises CRS SV support in its Root Capabilities register, and the CRS SV enable bit is writable (even though the hardware ignores it). Mask out PCI_EXP_RTCAP_CRSVIS so software doesn't try to use CRS SV. Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com> [bhelgaas: changelog, add probe-time warning about corruption, don't advertise CRS SV support, remove duplicate pci_generic_config_read32(), fix alignment based on patch from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: iproc: Factor out memory-mapped config access address calculationOza Pawandeep1-13/+26
Factor out the address calculation for memory-mapped config accesses as a separate function. No functional change intended. Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-28PCI: rockchip: Idle inactive PHY(s)Shawn Lin1-2/+38
Check the status of all lanes and idle the inactive one(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: always set lanes_map, even for legacy_phy case] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-28phy: rockchip-pcie: Reconstruct driver to support per-lane PHYsShawn Lin1-14/+117
Reconstruct the whole driver to support per-lane PHYs. Note that we could also support the legacy PHY if you don't provide argument to rockchip_pcie_phy_of_xlate(). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: use postincrement/decrement when order doesn't matter, uninline to_pcie_phy() so decl fits on one line] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-28PCI: rockchip: Add per-lane PHY supportShawn Lin1-20/+58
We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-24PCI: qcom: Add support for IPQ8074 PCIe controllerVaradarajan Narayanan1-1/+206
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one lane, two PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the similar to the existing SoC, however the clocks and reset lines differ. Signed-off-by: smuthayy <smuthayy@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> [bhelgaas: fix capitalization and "dev" usage to match existing style] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-24dt-bindings: PCI: qcom: Add support for IPQ8074Varadarajan Narayanan1-0/+23
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one lane, two PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2017-08-24PCI: qcom: Use block IP version for operationsVaradarajan Narayanan1-67/+71
Presently, when support for a new SoC is added, the driver ops structures and functions are versioned with plain 1, 2, 3 etc. Instead use the block IP version number. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-24PCI: qcom: Explicitly request exclusive reset controlPhilipp Zabel1-18/+22
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-24PCI: qcom: Use gpiod_set_value_cansleep() to allow reset via expandersFabio Estevam1-2/+2
The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-22PCI: dwc: Clear MSI interrupt status after it is handled, not beforeFaiz Abbas1-1/+1
If the interrupt status is cleared before it is handled, it is possible that another interrupt will trigger while servicing the previous one. This is causing timeouts in some wireless lan cards which use PCIe. Clear MSI interrupt status after it gets serviced instead of before calling generic_handler. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Joao Pinto <jpinto@synopsys.com>
2017-08-22PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe()Gustavo A. R. Silva1-2/+2
platform_get_irq() returns an error code, but the pci-dra7xx driver ignores it and always returns -EINVAL. This is not correct and prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq() on failure. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-20PCI: kirin: Constify dw_pcie_host_ops structureBhumika Goyal1-1/+1
Make this structure const as it is only stored in the ops field of a pcie_port structure, which is of type const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-20PCI: hisi: Constify dw_pcie_host_ops structureBhumika Goyal1-1/+1
Make this structure const as it is only stored in the ops field of a pcie_port structure, which is of type const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16PCI: keystone: Use PCI_NUM_INTXBjorn Helgaas3-6/+4
Switch from using custom MAX_LEGACY_IRQS and MAX_LEGACY_HOST_IRQS macros to the generic PCI_NUM_INTX definition for the number of INTx interrupts. Based-on-similar-patches-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
2017-08-16PCI: keystone: Remove duplicate MAX_*_IRQS defsBjorn Helgaas1-4/+0
MAX_MSI_HOST_IRQS and MAX_LEGACY_HOST_IRQS are defined in both pci-keystone.h (which is included by pci-keystone.c) and in pci-keystone.c itself. Remove the duplicate definitions from pci-keystone.c. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
2017-08-16PCI: rockchip: Factor out rockchip_pcie_get_phys()Shawn Lin1-6/+16
We plan to introduce per-lane PHYs, so factor out rockchip_pcie_get_phys() to make it easier in the future. No functional change intended. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-16PCI: rockchip: Control optional 12v power supplyShawn Lin1-1/+24
Get vpcie12v from DT and control it if available. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16dt-bindings: PCI: rockchip: Add vpcie12v-supply for Rockchip PCIe controllerShawn Lin1-0/+1
The PCIe connector provide a optional 12V power supply for high power downstream components, so we add this as an optional one if we need to control it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2017-08-16PCI: keystone-dw: Remove unused ks_pcie, pci variablesShawn Lin1-8/+0
The ks_pcie and pci variables in ks_dw_pcie_msi_irq_mask() and ks_dw_pcie_msi_irq_unmask() are never used. Remove them. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16PCI: faraday: Use PCI_NUM_INTXPaul Burton1-1/+1
Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16PCI: faraday: Fix of_irq_get() error checkSergei Shtylyov1-2/+2
of_irq_get() may return a negative error number as well as 0 on failure, while the driver only checks for 0, blithely continuing with the call to irq_set_chained_handler_and_data() -- that function expects *unsigned int* so should probably do nothing when a large IRQ number resulting from a conversion of a negative error number is passed to it. The driver then probes successfully while being only partly functional... Check for 'irq <= 0' instead and propagate the negative error number to the probe method -- that will allow the deferred probing as well. Fixes: d3c68e0a7e34 ("PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-16PCI: dra7xx: Use PCI_NUM_INTXBjorn Helgaas1-1/+1
Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Based-on-similar-patches-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-16PCI: altera: Use size=4 IRQ domain for legacy INTxPaul Burton1-5/+4
The devicetree binding documentation for the Altera PCIe controller shows an example which uses an interrupt-map property to map PCI INTx interrupts to hardware IRQ numbers 1-4. The driver creates an IRQ domain with size 5 in order to cover this range, with hwirq=0 left unused. This patch cleans up this wasted IRQ domain entry, modifying the driver to use an IRQ domain of size 4 which matches the actual number of PCI INTx interrupts. Since the hwirq numbers 1-4 are part of the devicetree binding, and this is considered ABI, we cannot simply change the interrupt-map property to use the range 0-3. Instead we make use of the pci_irqd_intx_xlate() helper function to translate the range 1-4 used at the DT level into the range 0-3 which is now used within the driver, and stop adding 1 to decoded hwirq numbers in altera_pcie_isr(). Whilst cleaning up INTx handling we make use of the new PCI_NUM_INTX macro & drop the custom INTX_NUM definition. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
2017-08-16PCI: altera: Remove unused num_of_vectors variableShawn Lin1-2/+0
The local variable "num_of_vectors" was unused, so remove it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
2017-08-16PCI: aardvark: Use PCI_NUM_INTXPaul Burton1-3/+2
Switch from using a custom LEGACY_IRQ_NUM macro to the generic PCI_NUM_INTX definition for the number of INTx interrupts. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-08-16PCI: Add pci_irqd_intx_xlate()Paul Burton1-0/+32
Legacy PCI INTx interrupts are represented in the PCI_INTERRUPT_PIN register using the range 1-4, which matches our enum pci_interrupt_pin. This is however not ideal for an IRQ domain, where with 4 interrupts we would ideally have a domain of size 4 & hwirq numbers in the range 0-3. Different PCI host controller drivers have handled this in different ways. Of those under drivers/pci/ which register an INTx IRQ domain, we have: - pcie-altera uses the range 1-4 in device trees and an IRQ domain of size 5 to cover that range, with entry 0 wasted. - pcie-xilinx & pcie-xilinx-nwl use the range 1-4 in device trees but register an IRQ domain of size 4, which doesn't cover the hwirq=4/INTD case leading to that interrupt being broken. - pci-ftpci100 & pci-aardvark use the range 0-3 in both device trees & as hwirq numbering in the driver & IRQ domain. In order to introduce some level of consistency in at least the hwirq numbering used by the drivers & IRQ domains, this patch introduces a new pci_irqd_intx_xlate() helper function which drivers using the 1-4 range in device trees can assign as the xlate callback for their INTx IRQ domain. This translates the 1-4 range into a 0-3 range, allowing us to use an IRQ domain of size 4 & avoid a wasted entry. Further patches will make use of this in drivers to allow them to use an IRQ domain of size 4 for legacy INTx interrupts without breaking INTD. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16PCI: rcar: Fix memory leak when no PCIe card is insertedHarunobu Kurokawa1-0/+1
When no PCIe card is inserted, there is a memory leak as pci_free_resource_list() is not called before returning. Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
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