summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-08-31Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ↵Stephen Boyd66-3473/+5010
'clk-rockchip' into clk-next - Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-08-31Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and ↵Stephen Boyd249-668/+2094
'clk-cleanup' into clk-next - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes
2023-08-23clk: mvebu: Convert to devm_platform_ioremap_resource()Yangtao Li2-6/+2
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-13-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: nuvoton: Convert to devm_platform_ioremap_resource()Yangtao Li1-2/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-12-frank.li@vivo.com Acked-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-11-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: ti: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-6/+2
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-10-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: mediatek: Convert to devm_platform_ioremap_resource()Yangtao Li2-19/+8
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-9-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: hsdk-pll: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-7-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: gemini: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-6-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: fsl-sai: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-5-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: bm1880: Convert to devm_platform_ioremap_resource()Yangtao Li1-5/+2
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-4-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: axm5516: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-3-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: actions: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-2-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: cdce925: Remove redundant of_match_ptr()Ruan Jinjie1-1/+1
The driver depends on CONFIG_OF, it is not necessary to use of_match_ptr() here. Signed-off-by: Ruan Jinjie <ruanjinjie@huawei.com> Link: https://lore.kernel.org/r/20230808125341.4073115-1-ruanjinjie@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()Biju Das1-1/+1
The device_get_match_data(), is to get match data for firmware interfaces such as just OF/ACPI. This driver has I2C matching table as well. Use i2c_get_match_data() to get match data for I2C, ACPI and DT-based matching. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230721070019.96627-3-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()Biju Das1-1/+1
The device_get_match_data(), is to get match data for firmware interfaces such as just OF/ACPI. This driver has I2C matching table as well. Use i2c_get_match_data() to get match data for I2C, ACPI and DT-based matching. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230721070019.96627-2-biju.das.jz@bp.renesas.com Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22Merge tag 'v6.6-rockchip-clk1' of ↵Stephen Boyd2-1/+61
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - PLL rates for rk3568 and the display clock tree for rv1126 which wasn't present before * tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-08-22Merge tag 'renesas-clk-for-v6.6-tag2' of ↵Stephen Boyd9-1/+9
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull another Renesas clk driver update from Geert Uytterhoeven: - Add Audio Clock Generator (ADG) clocks on R-Car Gen3 and RZ/G2 SoCs * tag 'renesas-clk-for-v6.6-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto9-1/+9
R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use clk_i which came from the internal S0D4 or ZA2 clock. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> # R-Car M3-N Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> # R-Car M3-N Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87pm47prox.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87o7jrpros.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87mszbpron.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87leevproh.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87jzufprod.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87il9zpro8.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87h6pjpro4.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87fs53prny.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87edknprnt.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-15Merge tag 'sunxi-clk-for-6.6-2' of ↵Stephen Boyd9-54/+204
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver changes from Chen-Yu Tsai: - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for NKM clocks * tag 'sunxi-clk-for-6.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW
2023-08-11clk: rockchip: rv1126: Add PD_VO clock treeJagan Teki1-0/+59
PD_VO clock tree diagram in RV1126 is connected to - BIU_VO - VOP - RGA - IEP - DSIHOST Add entire PD_VO clock tree for rv1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230731110012.2913742-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-08-10Merge tag 'sunxi-clk-for-6.6-1' of ↵Stephen Boyd2-7/+5
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Jernej Skrabec: - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c * tag 'sunxi-clk-for-6.6-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()
2023-08-10Merge tag 'clk-meson-v6.6-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd41-3396/+3471
clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - dt-bindings: expose all Amlogic clock ids - Migrate Amlogic gxbb clock controllers dt-bindings to schema * tag 'clk-meson-v6.6-1' of https://github.com/BayLibre/clk-meson: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ...
2023-08-09clk: sunxi-ng: nkm: Prefer current parent rateFrank Oltmanns1-1/+2
Similar to ccu_mp, if the current parent rate allows getting the ideal rate, prefer to not change the parent clock's rate. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-11-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: a64: select closest rate for pll-video0Frank Oltmanns1-22/+16
Selecting the closest rate for pll-video0 instead of the closest rate that is less than the requested rate has no downside for this clock, while allowing for selecting a more suitable rate, e.g. for the connected panels. Furthermore, the algorithm that sets an NKM clock's parent benefits from the closest rate. Without it, the NKM clock's rate might drift away from the requested rate in the multiple successive calls to ccu_nkm_determine_rate that the clk framework performs when setting a clock rate. Therefore, configure pll-video0 and, in consequence, all of its descendents to select the closest rate. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-10-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: div: Support finding closest rateFrank Oltmanns1-0/+30
Add initalization macros for divisor clocks with mux (SUNXI_CCU_M_WITH_MUX) to support finding the closest rate. This clock type requires the appropriate flags to be set in the .common structure (for the mux part of the clock) and the .div part. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-9-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: mux: Support finding closest rateFrank Oltmanns2-12/+39
When finding the best rate for a mux clock, consider rates that are higher than the requested rate when CCU_FEATURE_ROUND_CLOSEST is used. Furthermore, introduce an initialization macro that sets this flag. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-8-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: nkm: Support finding closest rateFrank Oltmanns2-12/+10
When finding the best rate for a NKM clock, consider rates that are higher than the requested rate, if the CCU_FEATURE_CLOSEST_RATE flag is set by using the helper function ccu_is_better_rate(). Accommodate ccu_mux_helper_determine_rate to this change. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-7-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: nm: Support finding closest rateFrank Oltmanns2-11/+50
Use the helper function ccu_is_better_rate() to determine the rate that is closest to the requested rate, thereby supporting rates that are higher than the requested rate if the clock uses the CCU_FEATURE_CLOSEST_RATE. Add the macro SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST which sets CCU_FEATURE_CLOSEST_RATE. To avoid code duplication, add the macros SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT that allows selecting arbitrary features and use it in the original SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX as well as the newly introduced SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST macros. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-6-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: Add helper function to find closest rateFrank Oltmanns2-0/+17
The default behaviour of clocks in the sunxi-ng driver is to select a clock rate that is closest to but less than the requested rate. Add the ccu_is_better_rate() helper function that - depending on the fact if thc CCU_FEATURE_CLOSEST_RATE flag is set - decides if a rate is closer than another rate. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-5-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: Add feature to find closest rateFrank Oltmanns1-0/+1
The default behaviour of clocks in the sunxi-ng driver is to select a clock rate that is closest to but less than the requested rate. Add the CCU_FEATURE_CLOSEST_RATE flag, which can be used to allow clocks to find the closest rate instead. Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-4-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: a64: allow pll-mipi to set parent's rateFrank Oltmanns1-1/+2
The nkm clock now supports setting the parent's rate. Utilize this option to find the optimal rate for pll-mipi. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-3-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: nkm: consider alternative parent rates when determining rateFrank Oltmanns1-1/+43
In case the CLK_SET_RATE_PARENT flag is set, consider using a different parent rate when determining a new rate. To find the best match for the requested rate, perform the following steps for each NKM combination: - calculate the optimal parent rate, - find the best parent rate that the parent clock actually supports - use that parent rate to calculate the effective rate. In case the clk does not support setting the parent rate, use the same algorithm as before. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-2-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-09clk: sunxi-ng: nkm: Use correct parameter name for parent HWFrank Oltmanns1-1/+1
ccu_nkm_round_rate() takes a clk_hw as parameter "hw". Since "hw" is the nkm clock's parent clk_hw, not the clk_hw of the nkm clock itself, change the parameter name to "parent_hw" to make it more clear what we're dealing with. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-1-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-08dt-bindings: soc: amlogic: document System Control registersNeil Armstrong1-0/+160
Document the System Control registers regions found on all Amlogic SoC families and it's clock, power, pinctrl and phy subnodes. The regions has various independent registers tied to other hardware devices, thus the syscon compatible. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230706-b4-amlogic-bindings-convert-take2-v3-3-f63de6f12dcc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schemaNeil Armstrong2-64/+85
Convert the Amlogic Always-On Clock Controller bindings to dt-schema. [jbrunet: Fixed whitespace checkpatch warning] Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230706-b4-amlogic-bindings-convert-take2-v3-2-f63de6f12dcc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schemaNeil Armstrong2-53/+37
Convert the Amlogic Clock Controller bindings to dt-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230706-b4-amlogic-bindings-convert-take2-v3-1-f63de6f12dcc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: axg-audio: move bindings include to main driverNeil Armstrong2-3/+2
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-19-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: meson8b: move bindings include to main driverNeil Armstrong2-7/+3
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-18-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: a1: move bindings include to main driverNeil Armstrong4-6/+4
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-17-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: eeclk: move bindings include to main driverNeil Armstrong6-9/+6
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-16-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: aoclk: move bindings include to main driverNeil Armstrong6-45/+9
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-15-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: axg-audio-clkc: expose all clock idsNeil Armstrong2-70/+65
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-audio-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-14-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock idsNeil Armstrong2-15/+5
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock idsNeil Armstrong2-63/+53
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 peripherals ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-12-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: meson8b-clkc: expose all clock idsNeil Armstrong2-108/+97
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every meson8b-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-11-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: g12a-aoclkc: expose all clock idsNeil Armstrong2-17/+7
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-aoclkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-10-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: g12a-clks: expose all clock idsNeil Armstrong2-140/+130
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-9-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: axg-clkc: expose all clock idsNeil Armstrong2-58/+48
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-8-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08dt-bindings: clk: gxbb-clkc: expose all clock idsNeil Armstrong2-76/+65
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every gxbb-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 02:16:35 +0300