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2021-09-28arm64: dts: qcom: sm6350: Add SPMI busKonrad Dybcio1-0/+18
Add a node for SPMI to allow for communication with on-board PMICs. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-11-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add AOSS_QMPKonrad Dybcio1-0/+11
Add a node for AOSS_QMP in preparation for remote processor enablement. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-10-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add TSENS nodesKonrad Dybcio1-0/+22
Add nodes required for TSENS block using the common qcom,tsens-v2 binding. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-9-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add cpufreq-hw supportKonrad Dybcio1-0/+18
Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-8-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add USB1 nodesKonrad Dybcio1-0/+101
Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and SC7180 IP, so no additional code porting is required. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Renamed dwc3 node "usb"] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-7-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add TLMM block nodeKonrad Dybcio1-0/+19
Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-6-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add GCC nodeKonrad Dybcio1-0/+16
Add and configure GCC node to allow for referencing GCC-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-5-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add RPMHCC nodeKonrad Dybcio1-0/+7
Add RPMHCC node to allow for referencing RPMH-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-4-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add LLCC nodeKonrad Dybcio1-0/+6
Add a node for LLCC with SM6350-specific compatible. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-3-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: Add SM6350 device treeKonrad Dybcio1-0/+485
Add a base DT for SM6350 SoC Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-2-konrad.dybcio@somainline.org
2021-09-28dt-bindings: arm: cpus: Add Kryo 560 CPUsKonrad Dybcio1-0/+1
Document Kryo 560 CPUs found in Qualcomm Snapdragon 690 (SM6350). Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-1-konrad.dybcio@somainline.org
2021-09-27arm64: dts: qcom: sm8350: Use QMP property to control load stateSibi Sankar1-14/+16
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8350 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-11-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sm8250: Use QMP property to control load stateSibi Sankar1-11/+11
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8250 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-10-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sm8150: Use QMP property to control load stateSibi Sankar1-14/+14
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8150 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-9-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sdm845: Use QMP property to control load stateSibi Sankar1-4/+8
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SDM845 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-8-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7280: Use QMP property to control load stateSibi Sankar1-2/+0
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7280 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-7-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7180: Use QMP property to control load stateSibi Sankar1-5/+4
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7180 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-6-git-send-email-sibis@codeaurora.org
2021-09-25arm64: dts: qcom: sc7180: Base homestar's power coefficients in realityDouglas Anderson1-1/+1
The commit 82ea7d411d43 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") and the commit be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") passed each other in the tubes that make up the Internet. Despite the fact the patches didn't cause a merge conflict, they need to account for each other. Do that. Fixes: 82ea7d411d43 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") Fixes: be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923081352.1.I2a2ee0ac428a63927324d65022929565aa7d8361@changeid
2021-09-25arm64: dts: qcom: msm8998-xperia: Add audio clock and its pinAngeloGioacchino Del Regno1-0/+19
All smartphones of this platform are equipped with a WCD9335 audio codec, getting its MCLK from PM8998 gpio13: add this clock to DT. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-7-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add camera regulatorsAngeloGioacchino Del Regno1-0/+56
All of the machines of the Sony Yoshino platform are equipped with two cameras, sharing the same regulators configuration. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-6-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Configure display boost regulatorsAngeloGioacchino Del Regno4-0/+58
Add configuration for the LAB and IBB regulators (in boost mode): this platform has smartphones with three different display sizes, hence different displays requiring different voltage. The common configuration parameters have been put in the common device-tree, while specific voltage specs and soft-start-us are variant specific, so they have been put into the machine specific dts file. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-5-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add support for gpio vibratorAngeloGioacchino Del Regno1-0/+19
All smartphones in the Sony Yoshino platforms have got a simple vibrator hooked to a GPIO: add support for that and add its own pin configuration. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-4-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add support for wcn3990 BluetoothAngeloGioacchino Del Regno1-0/+16
This platform uses the WCN3990 Bluetooth chip, reachable on UART-3. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-3-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add RMI4 touchscreen supportAngeloGioacchino Del Regno1-0/+60
All of the devices in the Sony Yoshino platform are using a Synaptics RMI4-compatible touch IC with identical pins and supplies: enable the I2C-5 bus and add the rmi4-i2c node along with the required pin configurations. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-2-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platformAngeloGioacchino Del Regno5-0/+564
This commit introduces support for the Sony Yoshino platform, using the MSM8998 SoC, including: - Sony Xperia XZ1 (codename Poplar), - Sony Xperia XZ1 Compact (codename Lilac), - Sony Xperia XZ Premium (codename Maple). All of the three aforementioned smartphones are sharing a 99% equal board configuration, with very small differences between each other, which is the reason for the introduction of a common msm8998-sony-xperia-yoshino DT. This base configuration includes regulators and project-wide pin configurations and it's made to boot to a serial console. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-1-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: pm660: Add reboot mode supportShawn Guo1-2/+3
It turns out that the pm660 PON is a GEN2 device. Update the compatible to "qcom,pm8998-pon" and add reboot mode support, so that devices can be rebooted into bootloader and recovery mode. Tested on Xiaomi Redmi Note 7 phone. While at it, drop the unnecessary newline between 'compatible' and 'reg' property. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210824021918.17271-1-shawn.guo@linaro.org
2021-09-25arm64: dts: qcom: sc7280: Add aliases for I2C and SPIRajesh Patil1-0/+32
Add aliases for i2c and spi for sc7280 soc. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-9-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Add QUPv3 wrapper_1 nodesRoja Rani Yarubandi2-0/+753
Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-8-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Configure uart7 to support bluetooth on sc7280-idpRajesh Patil1-0/+85
Add bluetooth uart pin configuration for sc7280-idp. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-7-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT nodeRoja Rani Yarubandi2-16/+33
Uart5 is treated as dedicated debug uart.Change the compatible as "qcom,geni-uart" in SoC DT to make it generic and later update it as "qcom,geni-debug-uart" in sc7280-idp Add interconnects and power-domains. Split the pinctrl functions and correct the gpio pins. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-6-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Add QUPv3 wrapper_0 nodesRoja Rani Yarubandi1-2/+722
Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-5-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Configure SPI-NOR FLASH for sc7280-idpRajesh Patil1-0/+27
Add spi-nor flash node and pinctrl configurations for the SC7280 IDP. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-4-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Add QSPI nodeRoja Rani Yarubandi1-0/+61
Add QSPI DT node and qspi_opp_table for SC7280 SoC. Move qspi_opp_table to / because SPI nodes assume any child node is a spi device and so we can't put the table underneath the spi controller. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-3-git-send-email-rajpat@codeaurora.org
2021-09-24arm64: dts: qcom: sm6125: Remove leading zeroesFabio Estevam1-3/+3
dtc complains about the leading zeroes: arch/arm64/boot/dts/qcom/sm6125.dtsi:497.19-503.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f121000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:505.19-510.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f123000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:512.19-517.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f124000: unit name should not have leading 0 Remove them. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210922195208.1734936-1-festevam@gmail.com
2021-09-23arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMCShaik Sajida Bhanu1-2/+2
The current drive strength values are not sufficient on non discrete boards and this leads to CRC errors during switching to HS400 enhanced strobe mode. Hardware simulation results on non discrete boards shows up that use the maximum drive strength values for data and command lines could helps in avoiding these CRC errors. So, update data and command line drive strength values to maximum. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1629132650-26277-1-git-send-email-sbhanu@codeaurora.org
2021-09-22arm64: dts: qcom: sc7180-trogdor: Enable IPA on LTE only SKUsSujit Kautkar2-11/+11
Enable the IPA node for LTE and skip for wifi-only SKUs Signed-off-by: Sujit Kautkar <sujitka@chromium.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210920113220.v1.1.I904da9664f294fcf222f6f378d37eaadd72ca92e@changeid
2021-09-22arm64: dts: qcom: msm8916: Add "qcom,msm8916-sdhci" compatibleStephan Gerhold1-2/+2
According to Documentation/devicetree/bindings/mmc/sdhci-msm.txt a SoC specific compatible should be used in addition to the IP version compatible, but for some reason it was never added for MSM8916. Add the "qcom,msm8916-sdhci" compatible additionally to make the device tree match the documented bindings. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210921152120.6710-3-stephan@gerhold.net
2021-09-22arm64: dts: qcom: msm8916: Add unit name for /soc nodeStephan Gerhold1-1/+1
This fixes the following warning when building with W=1: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210921152120.6710-1-stephan@gerhold.net
2021-09-22arm64: dts: qcom: sc7280: Use GIC_SPI for intc cellsStephen Boyd1-2/+2
Let's use the GIC_SPI macro instead of a plain 0 here to match other uses of the primary interrupt controller on sc7280. Suggested-by: Matthias Kaehlcke <mka@chromium.org> Cc: Alex Elder <elder@linaro.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210811181904.779316-1-swboyd@chromium.org
2021-09-22arm64: dts: qcom: sc7280: Add gpu thermal zone cooling supportManaf Meethalavalappu Pallikunhi1-7/+22
Add cooling-cells property and the cooling maps for the gpu thermal zones to support GPU thermal cooling. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1628691835-36958-2-git-send-email-akhilpo@codeaurora.org
2021-09-22arm64: dts: qcom: sc7280: Add gpu supportAkhil P Oommen1-0/+115
Add the necessary dt nodes for gpu support in sc7280. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1628691835-36958-1-git-send-email-akhilpo@codeaurora.org
2021-09-22arm64: dts: qcom: sc7280: Add clock controller ID headersTaniya Das1-0/+3
Add the GPUCC, DISPCC and VIDEOCC clock headers which were dropped earlier. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1628642571-25383-1-git-send-email-tdas@codeaurora.org
2021-09-22arm64: dts: qcom: sc7280: Add volume up support for sc7280-idpsatya priya1-0/+32
Add pm7325 PMIC gpio support for vol+ on sc7280-idp. Signed-off-by: satya priya <skakit@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631877040-26587-1-git-send-email-skakit@codeaurora.org
2021-09-22arm64: dts: qcom: qrb5165-rb5: enabled pwrkey and resin nodesDmitry Baryshkov1-0/+10
Enable powerkey and resin nodes to let the board handle POWER and Volume- keys properly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210916151341.1797512-3-dmitry.baryshkov@linaro.org
2021-09-22arm64: dts: qcom: pm8150: specify reboot mode magicsDmitry Baryshkov1-0/+2
Specify recovery and bootloader magic values to be programmed by the qcom-pon driver. This allows the bootloader to handle reboot-to-bootloader functionality. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210916151341.1797512-2-dmitry.baryshkov@linaro.org
2021-09-22arm64: dts: qcom: pm8150: use qcom,pm8998-pon bindingDmitry Baryshkov1-1/+1
Change pm8150 to use the qcom,pm8998-pon compatible string for the pon in order to pass reboot mode properly. Fixes: 5101f22a5c37 ("arm64: dts: qcom: pm8150: Add base dts file") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210916151341.1797512-1-dmitry.baryshkov@linaro.org
2021-09-22arm64: dts: qcom: ipq6018: add usb3 DT descriptionKathiravan T1-0/+83
Based on downstream codeaurora code. Tested (USB2 only) on IPQ6010 based hardware. Signed-off-by: Kathiravan T <kathirav@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> [bjorn: Changed dwc3 node name to usb, per binding] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/ebc2d340d566fa2d43127e253d5b8b134a87a78e.1630389452.git.baruch@tkos.co.il
2021-09-22arm64: dts: qcom: Update BAM DMA node name per DT schemaShawn Guo4-5/+5
Follow dma-controller.yaml schema to use `dma-controller` as node name of BAM DMA devices. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org
2021-09-22arm64: dts: qcom: sc7280: Move the SD CD GPIO pin out of the dtsi fileDouglas Anderson2-4/+1
There's nothing magical about GPIO91 and boards could use different GPIOs for card detect. Move the pin out of the dtsi file and to the only existing board file. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210830080621.1.Ia15d97bc4a81f2916290e23a8fde9cbc66186159@changeid
2021-09-22arm64: dts: qcom: sdm845: Fix qcom,controlled-remotely propertyShawn Guo1-1/+1
Property qcom,controlled-remotely should be boolean. Fix it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829111628.5543-4-shawn.guo@linaro.org
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 01:39:58 +0300