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2022-07-13[NOT-FOR-UPSTREAM] Add build instructionsvisionfive-5.18.yEmil Renner Berthing9-0/+421
For convenience this also adds a small visionfive_defconfig and the firmware needed for the brcmfmac driver along with the signed regulatory database. The firmware is from the linux-firmware repo and the regulatory database from the wireless-regdb Fedora package. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Drew Fustini <drew@beagleboard.org>
2022-07-13[NOT-FOR-UPSTREAM] riscv: Add StarFive JH7100 Fedora defconfigFu Wei1-0/+3112
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2022-07-13riscv: dts: Add full JH7100, Starlight and VisionFive supportEmil Renner Berthing6-151/+1223
Based on the device tree in https://github.com/starfive-tech/u-boot/ with contributions from: yanhong.wang <yanhong.wang@starfivetech.com> Huan.Feng <huan.feng@starfivetech.com> ke.zhu <ke.zhu@starfivetech.com> yiming.li <yiming.li@starfivetech.com> jack.zhu <jack.zhu@starfivetech.com> Samin Guo <samin.guo@starfivetech.com> Chenjieqin <Jessica.Chen@starfivetech.com> bo.li <bo.li@starfivetech.com> Rearranged, cleanups, fixes, pins and resets added by Emil. Cleanups, fixes, clocks added by Geert. Cleanups and GPIO fixes from Drew. Thermal zone added by Stephen. PWM pins added by Jianlong. cpu-map added by Jonas. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org> Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
2022-07-13spi: cadence-quadspi: Allow compilation on RISC-VEmil Renner Berthing1-1/+1
This IP is also used on the StarFive JH7100 riscv64 SoC and presumably also the upcoming JH7110 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13nvdla: add NVDLA driverFarzad Farshchi34-0/+32587
Additional update from Prashant Gaikwad <pgaikwad@nvidia.com> Adapted for Linux 5.13 and the BeagleV Starlight board by <cybergaszcz@gmail.com> kernel test robot: fix platform_no_drv_owner.cocci warnings Geert: Use div_u64() in dla_get_time_us() Signed-off-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20220119060057.GA1143@7f39e361da8f Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://lore.kernel.org/r/alpine.DEB.2.22.394.2203090905560.780932@ramsan.of.borg Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13drm/i2c/tda998x: Hardcode register values for Starlightsw.multimedia1-2/+5
A proper solution to this hack should be found. Signed-off-by: jack.zhu <jack.zhu@starfivetech.com> Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
2022-07-13[WIP] drm/starfive: Support DRM_FORMAT_XRGB8888Emil Renner Berthing2-0/+2
When creating dumb buffers with 32bpp and 24bit colour depth this is default mode return by drm_mode_legacy_fb_format. So we need to support this for common dumb buffers to just work. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13drm/starfive: Add StarFive drm driversw.multimedia19-0/+3425
Add starfive DRM Display driver framework Signed-off-by: jack.zhu <jack.zhu@starfivetech.com> Signed-off-by: keith.zhao <keith.zhao@starfivetech.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://lore.kernel.org/r/a8ca722539672d6369d6e4092e1e08cb6b58c546.1645535955.git.geert@linux-m68k.org Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13ASoC: starfive: Add StarFive JH7100 audio driversWalker Chen16-0/+4191
Signed-off-by: Michael Yan <michael.yan@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13net: stmmac: use GFP_DMA32Matteo Croce1-2/+2
Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2022-07-13net: stmmac: Configure gtxclk based on speedTom1-0/+47
2022-07-13net: phy: motorcomm: Add WIP YT8521 wake-on-lan codeWalker Chen1-0/+201
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-07-13net: phy: motorcomm: Add YT8521 supportWalker Chen2-1/+69
This adds basic support for the Motorcomm YT8521 Gigabit Ethernet PHY. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13dmaengine: dw-axi-dmac: Add StarFive JH7100 supportSamin Guo2-1/+14
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13dmaengine: dw-axi-dmac: Handle xfer start while non-idleSamin Guo2-1/+13
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
2022-07-13[WIP] dt-bindings: dma: dw-axi-dmac: Increase DMA channel limit to 16Geert Uytterhoeven1-3/+3
The first DMAC instance in the StarFive JH7100 SoC supports 16 DMA channels. FIXME Given there are more changes to the driver than just increasing DMAC_MAX_CHANNELS, we probably need a new compatible value, too. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-13pwm: sifive-ptc: Add SiFive PWM PTC driverChenjieqin3-0/+270
yiming.li: clear CNTR of PWM after setting period & duty_cycle Emil: cleanups, clock, reset and div_u64 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13drivers/tty/serial/8250: update driver for JH7100Samin Guo1-0/+8
2022-07-13power: reset: tps65086: Allow building as a moduleEmil Renner Berthing1-1/+1
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13RISC-V: Add non-coherent DMA supportEmil Renner Berthing3-0/+63
This implements the cache management operations to support non-coherent DMAs on RISC-V. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13soc: sifive: l2 cache: Add non-coherent DMA handlingEmil Renner Berthing2-0/+71
Add functions to flush the caches and handle non-coherent DMA. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13soc: sifive: l2 cache: Add StarFive JH7100 supportEmil Renner Berthing4-2/+9
This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. Unfortunately the data corrected interrupt is broken and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13soc: sifive: l2 cache: Convert to platform driverEmil Renner Berthing1-39/+40
This converts the driver to use the builtin_platform_driver_probe macro to initialize the driver. This macro ends up calling device_initcall as was used previously, but also allocates a platform device which gives us access to much nicer APIs such as platform_ioremap_resource, platform_get_irq and dev_err_probe. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13dt-bindings: sifive-l2-cache: Support StarFive JH7100 SoCEmil Renner Berthing1-0/+2
This cache controller is also used on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13hwrng: Add StarFive JH7100 Random Number Generator driverHuan Feng4-0/+437
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13watchdog: Add StarFive SI5 watchdog driverSamin Guo3-0/+773
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13hwmon: (sfctemp) Add StarFive JH7100 temperature sensorEmil Renner Berthing6-0/+401
Register definitions and conversion constants based on sfctemp driver by Samin in the StarFive 5.10 kernel. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-07-13dt-bindings: hwmon: add starfive,jh7100-temp bindingsEmil Renner Berthing1-0/+74
Add bindings for the temperature sensor on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Reviewed-by: Rob Herring <robh@kernel.org>
2022-07-13serial: 8250_dw: Add starfive,jh7100-hsuart compatibleEmil Renner Berthing1-0/+1
This adds a compatible for the high speed UARTs on the StarFive JH7100 RISC-V SoC. Just like the regular uarts we also need to keep the input clocks at their default rate and rely only on the divisor in the UART. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13serial: 8250_dw: Use device tree match dataEmil Renner Berthing1-6/+12
..rather than multiple calls to of_device_is_compatible(). Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13pinctrl: starfive: Reset pinmux settingsEmil Renner Berthing2-0/+70
Current u-boot doesn't seem to take into account that some GPIOs are configured as inputs/outputs of certain peripherals on power-up. This means it ends up configuring some GPIOs as inputs to more than one peripheral which the documentation explicitly says is illegal. Similarly it also ends up configuring more than one GPIO as output of the same peripheral. While not explicitly mentioned by the documentation this also seems like a bad idea. The easiest way to remedy this mess is to just disconnect all GPIOs from peripherals and have our pinmux configuration set everything up properly. This, however, means that we'd disconnect the serial console from its pins for a while, so add a device tree property to keep certain GPIOs from being reset. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13pinctrl: starfive: Serialize pinconf_generic callsJianlong Huang1-0/+5
The pinctrl dt_node_to_map method may be called in parallel which leads us to call pinconf_generic_add_group (and pinconf_generic_add_function) in parallel. This is not supported though and leads to errors, so add a mutex to serialize these calls per device. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13clk: starfive: jh7100: Keep more clocks aliveEmil Renner Berthing1-18/+18
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13RISC-V: Add StarFive JH7100 audio reset nodeEmil Renner Berthing1-0/+6
Add device tree node for the audio resets on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13reset: starfive: Add JH7100 audio reset driverEmil Renner Berthing6-15/+112
The audio resets are almost identical to the system resets, there are just fewer of them. So factor out and export a generic probe function, so most of the reset controller implementation can be shared. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13reset: starfive: Use 32bit I/O on 32bit registersEmil Renner Berthing1-20/+20
The driver currently uses 64bit I/O on the 32bit registers. This works because there are 4 assert registers and 4 status register, so they're only ever accessed on 64bit boundaries. There are however other reset controllers for audio and video on the SoC with only one status register that isn't 64bit aligned so 64bit I/O would result in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13reset: Create subdirectory for StarFive driversEmil Renner Berthing6-9/+13
This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13dt-bindings: reset: Add starfive,jh7100-audrst bindingsEmil Renner Berthing1-0/+38
Add bindings for the audio reset controller on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13dt-bindings: reset: Add StarFive JH7100 audio reset definitionsEmil Renner Berthing1-0/+31
Add all resets for the StarFive JH7100 audio reset controller. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13RISC-V: Add StarFive JH7100 audio clock nodeEmil Renner Berthing1-0/+10
Add device tree node for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13riscv: dts: starfive: correct number of external interruptsMark Kettenis1-1/+1
The PLIC integrated on the Vic_U7_Core integrated on the StarFive JH7100 SoC actually supports 133 external interrupts. 127 of these are exposed to the outside world; the remainder are used by other devices that are part of the core-complex such as the L2 cache controller. But all 133 interrupts are external interrupts as far as the PLIC is concerned. Fix the property so that the driver can manage these additional external interrupts, which is important since the interrupts for the L2 cache controller are enabled by default. Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree") Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Link: https://lore.kernel.org/r/20220606162924.71418-1-kettenis@openbsd.org
2022-07-13riscv: dts: starfive: Group tuples in interrupt propertiesGeert Uytterhoeven1-4/+4
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-07-13riscv: optimized memsetMatteo Croce6-134/+43
The generic memset is defined as a byte at time write. This is always safe, but it's slower than a 4 byte or even 8 byte write. Write a generic memset which fills the data one byte at time until the destination is aligned, then fills using the largest size allowed, and finally fills the remaining data one byte at time. Signed-off-by: Matteo Croce <mcroce@microsoft.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13riscv: optimized memmoveMatteo Croce5-322/+26
When the destination buffer is before the source one, or when the buffers doesn't overlap, it's safe to use memcpy() instead, which is optimized to use a bigger data size possible. Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2022-07-13riscv: optimized memcpyMatteo Croce5-113/+101
Write a C version of memcpy() which uses the biggest data size allowed, without generating unaligned accesses. The procedure is made of three steps: First copy data one byte at time until the destination buffer is aligned to a long boundary. Then copy the data one long at time shifting the current and the next u8 to compose a long at every cycle. Finally, copy the remainder one byte at time. On a BeagleV, the TCP RX throughput increased by 45%: before: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44840 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 76.4 MBytes 641 Mbits/sec 27 624 KBytes [ 5] 1.00-2.00 sec 72.5 MBytes 608 Mbits/sec 0 708 KBytes [ 5] 2.00-3.00 sec 73.8 MBytes 619 Mbits/sec 10 451 KBytes [ 5] 3.00-4.00 sec 72.5 MBytes 608 Mbits/sec 0 564 KBytes [ 5] 4.00-5.00 sec 73.8 MBytes 619 Mbits/sec 0 658 KBytes [ 5] 5.00-6.00 sec 73.8 MBytes 619 Mbits/sec 14 522 KBytes [ 5] 6.00-7.00 sec 73.8 MBytes 619 Mbits/sec 0 621 KBytes [ 5] 7.00-8.00 sec 72.5 MBytes 608 Mbits/sec 0 706 KBytes [ 5] 8.00-9.00 sec 73.8 MBytes 619 Mbits/sec 20 580 KBytes [ 5] 9.00-10.00 sec 73.8 MBytes 619 Mbits/sec 0 672 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 736 MBytes 618 Mbits/sec 71 sender [ 5] 0.00-10.01 sec 733 MBytes 615 Mbits/sec receiver after: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44864 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 109 MBytes 912 Mbits/sec 48 559 KBytes [ 5] 1.00-2.00 sec 108 MBytes 902 Mbits/sec 0 690 KBytes [ 5] 2.00-3.00 sec 106 MBytes 891 Mbits/sec 36 396 KBytes [ 5] 3.00-4.00 sec 108 MBytes 902 Mbits/sec 0 567 KBytes [ 5] 4.00-5.00 sec 106 MBytes 891 Mbits/sec 0 699 KBytes [ 5] 5.00-6.00 sec 106 MBytes 891 Mbits/sec 32 414 KBytes [ 5] 6.00-7.00 sec 106 MBytes 891 Mbits/sec 0 583 KBytes [ 5] 7.00-8.00 sec 106 MBytes 891 Mbits/sec 0 708 KBytes [ 5] 8.00-9.00 sec 106 MBytes 891 Mbits/sec 28 433 KBytes [ 5] 9.00-10.00 sec 108 MBytes 902 Mbits/sec 0 591 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 1.04 GBytes 897 Mbits/sec 144 sender [ 5] 0.00-10.01 sec 1.04 GBytes 894 Mbits/sec receiver And the decreased CPU time of the memcpy() is observable with perf top. This is the `perf top -Ue task-clock` output when doing the test: before: Overhead Shared O Symbol 42.22% [kernel] [k] memcpy 35.00% [kernel] [k] __asm_copy_to_user 3.50% [kernel] [k] sifive_l2_flush64_range 2.30% [kernel] [k] stmmac_napi_poll_rx 1.11% [kernel] [k] memset after: Overhead Shared O Symbol 45.69% [kernel] [k] __asm_copy_to_user 29.06% [kernel] [k] memcpy 4.09% [kernel] [k] sifive_l2_flush64_range 2.77% [kernel] [k] stmmac_napi_poll_rx 1.24% [kernel] [k] memset Signed-off-by: Matteo Croce <mcroce@microsoft.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-07-13riscv: add ARCH_DMA_MINALIGN supportXianting Tian1-0/+2
Introduce ARCH_DMA_MINALIGN to riscv arch. Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
2022-07-12Linux 5.18.11Greg Kroah-Hartman1-1/+1
Link: https://lore.kernel.org/r/20220711090549.543317027@linuxfoundation.org Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Shuah Khan <skhan@linuxfoundation.org> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Fenil Jain <fkjainco@gmail.com> Tested-by: Rudi Heitbaum <rudi@heitbaum.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-07-12dmaengine: idxd: force wq context cleanup on device disable pathDave Jiang1-4/+1
commit 44c4237cf3436bda2b185ff728123651ad133f69 upstream. Testing shown that when a wq mode is setup to be dedicated and then torn down and reconfigured to shared, the wq configured end up being dedicated anyays. The root cause is when idxd_device_wqs_clear_state() gets called during idxd_driver removal, idxd_wq_disable_cleanup() does not get called vs when the wq driver is removed first. The check of wq state being "enabled" causes the cleanup to be bypassed. However, idxd_driver->remove() releases all wq drivers. So the wqs goes to "disabled" state and will never be "enabled". By that point, the driver has no idea if the wq was previously configured or clean. So force call idxd_wq_disable_cleanup() on all wqs always to make sure everything gets cleaned up. Reported-by: Tony Zhu <tony.zhu@intel.com> Tested-by: Tony Zhu <tony.zhu@intel.com> Fixes: 0dcfe41e9a4c ("dmanegine: idxd: cleanup all device related bits after disabling device") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Co-developed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20220628230056.2527816-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-07-12dmaengine: ti: Add missing put_device in ti_dra7_xbar_route_allocateMiaoqian Lin1-0/+4
commit 615a4bfc426e11dba05c2cf343f9ac752fb381d2 upstream. of_find_device_by_node() takes reference, we should use put_device() to release it when not need anymore. Fixes: a074ae38f859 ("dmaengine: Add driver for TI DMA crossbar on DRA7x") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20220605042723.17668-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-07-12dmaengine: qcom: bam_dma: fix runtime PM underflowCaleb Connolly1-28/+11
commit 0ac9c3dd0d6fe293cd5044cfad10bec27d171e4e upstream. Commit dbad41e7bb5f ("dmaengine: qcom: bam_dma: check if the runtime pm enabled") caused unbalanced pm_runtime_get/put() calls when the bam is controlled remotely. This commit reverts it and just enables pm_runtime in all cases, the clk_* functions already just nop when the clock is NULL. Also clean up a bit by removing unnecessary bamclk null checks. Suggested-by: Stephan Gerhold <stephan@gerhold.net> Fixes: dbad41e7bb5f ("dmaengine: qcom: bam_dma: check if the runtime pm enabled") Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20220629140559.118537-1-caleb.connolly@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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