starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-09-03	KVM: riscv: selftests: Drop SBI multi registers	Andrew Jones	1	-2/+0
2024-09-03	RISC-V: KVM: Don't add SBI multi regs in get-reg-list	Andrew Jones	1	-34/+2
2024-09-03	KVM: riscv: selftests: Generate ISA extension reg_list using macros	Anup Patel	1	-255/+76
2024-09-03	RISC-V: KVM: remove a redundant condition in kvm_arch_vcpu_ioctl_run()	Chao Du	1	-2/+1
2024-09-03	riscv: kvm: use ".L" local labels in assembly when applicable	Clément Léger	1	-2/+2
2024-09-03	riscv: kvm: Use SYM_*() assembly macros instead of deprecated ones	Clément Léger	1	-16/+12
2024-09-03	riscv: kernel: Use correct SYM_DATA_*() macro for data	Clément Léger	1	-5/+4
2024-09-03	riscv: Use SYM_*() assembly macros instead of deprecated ones	Clément Léger	17	-74/+60
2024-09-03	riscv: use ".L" local labels in assembly when applicable	Clément Léger	4	-44/+44
2024-09-03	KVM: riscv: selftests: Fix get-reg-list print_reg defaults	Andrew Jones	1	-4/+6
2024-09-03	KVM: riscv: selftests: Add SBI DBCN extension to get-reg-list test	Anup Patel	1	-0/+2
2024-09-03	KVM: riscv: selftests: get-reg-list print_reg should never fail	Andrew Jones	1	-51/+42
2024-09-03	KVM: riscv: selftests: Add condops extensions to get-reg-list test	Anup Patel	1	-0/+17
2024-09-03	KVM: riscv: selftests: Add smstateen registers to get-reg-list test	Anup Patel	1	-0/+34
2024-09-03	KVM: riscv: selftests: Add senvcfg register to get-reg-list test	Anup Patel	1	-0/+3
2024-09-03	KVM: selftests: Add array order helpers to riscv get-reg-list	Andrew Jones	1	-39/+47
2024-09-03	MAINTAINERS: RISC-V: KVM: Add another kselftests path	Andrew Jones	1	-0/+1
2024-09-03	work around gcc bugs with 'asm goto' with outputs	Linus Torvalds	5	-14/+14
2024-09-03	riscv: Avoid code duplication with generic bitops implementation	Xiao Wang	5	-122/+48
2024-09-03	riscv: Decouple emulated unaligned accesses from access speed	Charlie Jenkins	3	-13/+29
2024-09-03	riscv: Only check online cpus for emulated accesses	Charlie Jenkins	1	-1/+1
2024-09-03	riscv: fix __user annotation in traps_misaligned.c	Ben Dooks	1	-3/+3
2024-09-03	RISC-V: Remove __init on unaligned_emulation_finish()	Evan Green	1	-1/+1
2024-09-03	riscv: lib: Introduce has_fast_unaligned_access()	Charlie Jenkins	3	-11/+13
2024-09-03	riscv: Add checksum library	Charlie Jenkins	3	-0/+338
2024-09-03	riscv: Add checksum header	Charlie Jenkins	1	-0/+82
2024-09-03	riscv: Add static key for misaligned accesses	Charlie Jenkins	2	-3/+89
2024-09-03	riscv: Save/restore envcfg CSR during CPU suspend	Samuel Holland	2	-0/+5
2024-09-03	riscv: Add a custom ISA extension for the [ms]envcfg CSR	Samuel Holland	2	-2/+13
2024-09-03	riscv: Fix enabling cbo.zero when running in M-mode	Samuel Holland	2	-1/+3
2024-09-03	tools: riscv: Add header file vdso/processor.h	Haibo Xu	1	-0/+32
2024-09-03	tools: riscv: Add header file csr.h	Haibo Xu	1	-0/+541
2024-09-03	RISC-V: Implement archrandom when Zkr is available	Samuel Ortiz	2	-0/+81
2024-09-03	riscv: Optimize hweight API with Zbb extension	Xiao Wang	2	-1/+81
2024-09-03	RISC-V: hwprobe: Introduce which-cpus flag	Andrew Jones	4	-10/+114
2024-09-03	RISC-V: Move the hwprobe syscall to its own file	Andrew Jones	3	-321/+425
2024-09-03	riscv: hwprobe: export Zicond extension	Clément Léger	3	-0/+7
2024-09-03	riscv: hwprobe: export Zacas ISA extension	Clément Léger	3	-0/+6
2024-09-03	riscv: hwprobe: export Ztso ISA extension	Clément Léger	3	-0/+6
2024-09-03	riscv: hwprobe: export Zfa ISA extension	Clément Léger	3	-0/+6
2024-09-03	riscv: hwprobe: export Zvfh[min] ISA extensions	Clément Léger	3	-0/+12
2024-09-03	riscv: hwprobe: export Zhintntl ISA extension	Clément Léger	3	-0/+5
2024-09-03	riscv: hwprobe: export Zfh[min] ISA extensions	Clément Léger	3	-0/+13
2024-09-03	riscv: hwprobe: export vector crypto ISA extensions	Clément Léger	3	-0/+53
2024-09-03	riscv: hwprobe: add support for scalar crypto ISA extensions	Clément Léger	3	-0/+46
2024-09-03	riscv: hwprobe: export missing Zbc ISA extension	Clément Léger	3	-0/+5
2024-09-03	riscv: add ISA extension parsing for Zacas	Clément Léger	2	-0/+2
2024-09-03	riscv: add ISA extension parsing for Ztso	Clément Léger	2	-0/+2
2024-09-03	riscv: add ISA extension parsing for Zfa	Clément Léger	2	-0/+2
2024-09-03	riscv: add ISA extension parsing for Zvfh[min]	Clément Léger	2	-0/+4