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2024-06-19riscv: dts: starfive: dubhe-70: Remove svpbmtREL_DUBHE_JUN2024starfive-6.6.31-dubheLey Foon Tan1-4/+4
Remove Svpmbt extension from Dubhe-70. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2024-05-24Merge branch 'starfive-6.6.31-dubhe-sta' into 'starfive-6.6.31-dubhe'leyfoon.tan49-653/+1656
MAINTAINERS: RISC-V: KVM: Add another kselftests path See merge request starfive-tech/linux!367
2024-05-23riscv: dts: starfive: dubhe: Enable paravirtualization featuresTan En De1-0/+2
riscv: dts: starfive: dubhe: Enable paravirtualization features Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2024-05-22selftests/exec: Convert execveat test to generate KTAP outputMark Brown1-35/+52
[ Upstream commit 47903c1d153d5178d54ea086e2bfa5298506f04f ] Currently the execveat test does not produce KTAP output but rather a custom format. This means that we only get a pass/fail for the suite, not for each individual test that the suite does. Convert to using the standard kselftest output functions which result in KTAP output being generated. The main trick with this is that, being an exec() related test, the program executes itself and returns specific exit codes to verify success meaning that we need to only use the top level kselftest header/summary functions when invoked directly rather than when run as part of a test. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
2024-05-22kselftest: Add a ksft_perror() helperMark Brown1-0/+14
[ Upstream commit 907f33028871fa7c9a3db1efd467b78ef82cce20 ] The standard library perror() function provides a convenient way to print an error message based on the current errno but this doesn't play nicely with KTAP output. Provide a helper which does an equivalent thing in a KTAP compatible format. nolibc doesn't have a strerror() and adding the table of strings required doesn't seem like a good fit for what it's trying to do so when we're using that only print the errno. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
2024-05-22KVM: riscv: selftests: Add Zfa extension to get-reg-list testAnup Patel1-0/+4
[ Upstream commit 4d0e8f9a361b3a1f7b67418c536b258323de734f ] The KVM RISC-V allows Zfa extension for Guest/VM so let us add this extension to get-reg-list test. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Allow Zfa extension for Guest/VMAnup Patel2-0/+3
[ Upstream commit 41182cc6f507011a2e6c82657779e451ed9942bb ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zfa extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Add Zvfh[min] extensions to get-reg-list testAnup Patel1-0/+8
[ Upstream commit 1216fdd99be113fa75ccdd0497802bd0fe4369aa ] The KVM RISC-V allows Zvfh[min] extensions for Guest/VM so let us add these extensions to get-reg-list test. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Allow Zvfh[min] extensions for Guest/VMAnup Patel2-0/+6
[ Upstream commit f46300285926c2b0d0c79bf40c87d45e169cecb6 ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zvfh[min] extensions for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Add Zihintntl extension to get-reg-list testAnup Patel1-0/+4
[ Upstream commit 1a3bc507821d24a80a6af8beb08af8032c33ebd7 ] The KVM RISC-V allows Zihintntl extension for Guest/VM so let us add this extension to get-reg-list test. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Allow Zihintntl extension for Guest/VMAnup Patel2-0/+3
[ Upstream commit ab6da9cdc3f3d1d091d657219fb6e98f710ee098 ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zihintntl extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Add Zfh[min] extensions to get-reg-list testAnup Patel1-0/+8
[ Upstream commit 496ee21a17ce45e92483fdf1827ba91f4867f160 ] The KVM RISC-V allows Zfh[min] extensions for Guest/VM so let us add these extensions to get-reg-list test. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Allow Zfh[min] extensions for Guest/VMAnup Patel2-0/+6
[ Upstream commit f3901ece5b3894177d1816208d0fb06b295617e0 ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zfh[min] extensions for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Add vector crypto extensions to get-reg-list testAnup Patel1-0/+40
[ Upstream commit 2ddf79070f7edada19fecec57d8591d6b718fa53 ] The KVM RISC-V allows vector crypto extensions for Guest/VM so let us add these extensions to get-reg-list test. This includes extensions Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, and Zvkt. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Allow vector crypto extensions for Guest/VMAnup Patel2-0/+30
[ Upstream commit afd1ef3adfbc36e35fcf4f742fd90aea6480a276 ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable vector crypto extensions for Guest/VM. This includes extensions Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, and Zvkt. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Add scaler crypto extensions to get-reg-list testAnup Patel1-0/+40
[ Upstream commit 14d70de562dfd78be638fc59b0a323235acc67be ] The KVM RISC-V allows scaler crypto extensions for Guest/VM so let us add these extensions to get-reg-list test. This includes extensions Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zkr, Zksed, Zksh, and Zkt. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Allow scalar crypto extensions for Guest/VMAnup Patel2-0/+30
[ Upstream commit f370b4e668f017f523968f7490163fa922dcd92e ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable scalar crypto extensions for Guest/VM. This includes extensions Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zkr, Zksed, Zksh, and Zkt. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Add Zbc extension to get-reg-list testAnup Patel1-0/+4
[ Upstream commit ac396141308d07a9534c5a7f1f7c80cb95e35b20 ] The KVM RISC-V allows Zbc extension for Guest/VM so let us add this extension to get-reg-list test. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Allow Zbc extension for Guest/VMAnup Patel2-0/+3
[ Upstream commit 367188297254e7f81e3c3c94e6d6a623f757c4cb ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zbc extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: selftests: Add get-reg-list test for STA registersAndrew Jones1-0/+43
[ Upstream commit aad86da229bc9d0390dc2c02eb0db9ab1f50d059 ] Add SBI STA and its two registers to the get-reg-list test. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: selftests: Add steal_time test supportAndrew Jones3-2/+103
[ Upstream commit 60b6e31c499643b25d4b3ccb4cc8e365dfdb8863 ] With the introduction of steal-time accounting support for RISC-V KVM we can add RISC-V support to the steal_time test. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: selftests: Add guest_sbi_probe_extensionAndrew Jones2-0/+40
[ Upstream commit 945d880d6be0fd19bbc77d80d113bd2ca74c74f8 ] Add guest_sbi_probe_extension(), allowing guest code to probe for SBI extensions. As guest_sbi_probe_extension() needs SBI_ERR_NOT_SUPPORTED, take the opportunity to bring in all SBI error codes. We don't bring in all current extension IDs or base extension function IDs though, even though we need one of each, because we'd prefer to bring those in as necessary. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: selftests: Move sbi_ecall to processor.cAndrew Jones2-26/+26
[ Upstream commit 0dcab5c4762ac166aa7e635ae4b6d649e15717e2 ] sbi_ecall() isn't ucall specific and its prototype is already in processor.h. Move its implementation to processor.c. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Implement SBI STA extensionAndrew Jones2-2/+95
[ Upstream commit e9f12b5fff8ad0eefd0340273767d329ef65fd69 ] Add a select SCHED_INFO to the KVM config in order to get run_delay info. Then implement SBI STA's set-steal-time-shmem function and kvm_riscv_vcpu_record_steal_time() to provide the steal-time info to guests. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Add support for SBI STA registersAndrew Jones5-14/+97
[ Upstream commit f61ce890b1f0742f17b3a5d1f8c72574a33ffeb2 ] KVM userspace needs to be able to save and restore the steal-time shared memory address. Provide the address through the get/set-one-reg interface with two ulong-sized SBI STA extension registers (lo and hi). 64-bit KVM userspace must not set the hi register to anything other than zero and is allowed to completely neglect saving/restoring it. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Add support for SBI extension registersAndrew Jones4-4/+103
[ Upstream commit 5b9e41321ba919dd051c68d2a1d2c753aa61634c ] Some SBI extensions have state that needs to be saved / restored when migrating the VM. Provide a get/set-one-reg register type for SBI extension registers. Each SBI extension that uses this type will have its own subtype. There are currently no subtypes defined. The next patch introduces the first one. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Add SBI STA info to vcpu_archAndrew Jones3-0/+19
[ Upstream commit 38b3390ee4880140b6245fe3273fe9ce53f65bde ] KVM's implementation of SBI STA needs to track the address of each VCPU's steal-time shared memory region as well as the amount of stolen time. Add a structure to vcpu_arch to contain this state and make sure that the address is always set to INVALID_GPA on vcpu reset. And, of course, ensure KVM won't try to update steal- time when the shared memory address is invalid. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Add steal-update vcpu requestAndrew Jones3-0/+12
[ Upstream commit 2a1f6bf079700f0f9d8045ab77b302aeb4d12c06 ] Add a new vcpu request to inform a vcpu that it should record its steal-time information. The request is made each time it has been detected that the vcpu task was not assigned a cpu for some time, which is easy to do by making the request from vcpu-load. The record function is just a stub for now and will be filled in with the rest of the steal-time support functions in following patches. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Add SBI STA extension skeletonAndrew Jones5-0/+54
[ Upstream commit 5fed84a800e6048656c17be6e921787db2b5c6c0 ] Add the files and functions needed to support the SBI STA (steal-time accounting) extension. In the next patches we'll complete the functions to fully enable SBI STA support. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: paravirt: Implement steal-time supportAndrew Jones2-3/+78
[ Upstream commit fdf68acccfc6af9497c34ee411d89af13b6516ed ] When the SBI STA extension exists we can use it to implement paravirt steal-time support. Fill in the empty pv-time functions with an SBI STA implementation and add the Kconfig knobs allowing it to be enabled. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: Add SBI STA extension definitionsAndrew Jones1-0/+17
[ Upstream commit 6cfc624576a64145b1d6d3d48de7161a7505f403 ] The SBI STA extension enables steal-time accounting. Add the definitions it specifies. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: paravirt: Add skeleton for pv-time supportAndrew Jones6-3/+115
[ Upstream commit 323925ed6dbb0ed877047b28fae4152527cc63db ] Add the files and functions needed to support paravirt time on RISC-V. Also include the common code needed for the first application of pv-time, which is steal-time. In the next patches we'll complete the functions to fully enable steal-time support. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Fix indentation in kvm_riscv_vcpu_set_reg_csr()Anup Patel1-1/+1
[ Upstream commit 4c460eb369514d53383a7c6ba1aefbca4914c68b ] The indentation of "break" in kvm_riscv_vcpu_set_reg_csr() is inconsistent hence let us fix it. Fixes: c04913f2b54e ("RISCV: KVM: Add sstateen0 to ONE_REG") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312190719.kBuYl6oJ-lkp@intel.com/ Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: add vector registers and CSRs in KVM_GET_REG_LISTDaniel Henrique Barboza1-0/+55
[ Upstream commit 3975525e554559117bbf569239c8b41f2c2fa5cf ] Add all vector registers and CSRs (vstart, vl, vtype, vcsr, vlenb) in get-reg-list. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: add 'vlenb' Vector CSRDaniel Henrique Barboza1-0/+15
[ Upstream commit 2fa290372dfe7dd248b1c16f943f273a3e674f22 ] Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise it is not possible to retrieve any vector reg since we're returning EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()Daniel Henrique Barboza1-0/+1
[ Upstream commit 197bd237b67268651ac544e8fedbe1fd275d41e0 ] 'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V: vector: export VLENB csr in __sc_riscv_v_state"), isn't being initialized in guest_context. If we export 'vlenb' as a KVM CSR, something we want to do in the next patch, it'll always return 0. Set 'vlenb' to riscv_v_size/32. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: selftests: Treat SBI ext regs like ISA ext regsAndrew Jones2-14/+92
[ Upstream commit bdf6aa328f137e184b0fce607fd585354c3742f1 ] SBI extension registers may not be present and indeed when running on a platform without sscofpmf the PMU SBI extension is not. Move the SBI extension registers from the base set of registers to the filter list. Individual configs should test for any that may or may not be present separately. Since the PMU extension may disappear and the DBCN extension is only present in later kernels, separate them from the rest into their own configs. The rest are lumped together into the same config. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Use register subtypesAndrew Jones1-40/+73
[ Upstream commit b26e70d72d12dc9ddb276898a78b1c35c7ab9b95 ] Always use register subtypes in the get-reg-list test when registers have them. The only registers neglecting to do so were ISA extension registers. While we don't really need to use KVM_REG_RISCV_ISA_SINGLE (since it's zero), the main purpose is to avoid confusion and to self-document the tests. Also add print support for the multi registers like SBI extensions have, even though they're only used for debugging. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Add RISCV_SBI_EXT_REGAndrew Jones2-19/+25
[ Upstream commit 6ccf119a4cc886678099a3526f37db98b67024d7 ] While adding RISCV_SBI_EXT_REG(), acknowledge that some registers have subtypes and extend __kvm_reg_id() to take a subtype field. Then, update all macros to set the new field appropriately. The general CSR macro gets renamed to include "GENERAL", but the other macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Make SBI uapi consistent with ISA uapiAndrew Jones4-45/+65
[ Upstream commit 23e1dc45022eb65529aa30b1851a8d21a639c8f5 ] When an SBI extension cannot be enabled, that's a distinct state vs. enabled and disabled. Modify enum kvm_riscv_sbi_ext_status to accommodate it, which allows KVM userspace to tell the difference in state too, as the SBI extension register will disappear when it cannot be enabled, i.e. accesses to it return ENOENT. get-reg-list is updated as well to only add SBI extension registers to the list which may be enabled. Returning ENOENT for SBI extension registers which cannot be enabled makes them consistent with ISA extension registers. Any SBI extensions which were enabled by default are still enabled by default, if they can be enabled at all. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Drop SBI multi registersAndrew Jones1-2/+0
[ Upstream 7602730d7f18ad9738d8fc5e5fd7f52a11fee399 ] These registers are no longer getting added to get-reg-list. We keep sbi_ext_multi_id_to_str() for printing, even though we don't expect it to normally be used, because it may be useful for debug. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: Don't add SBI multi regs in get-reg-listAndrew Jones1-34/+2
[ Upstream commit 7f58de96aa5e871dd553499e2c84fc801658eab6 ] The multi regs are derived from the single registers. Only list the single registers in get-reg-list. This also makes the SBI extension register listing consistent with the ISA extension register listing. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22KVM: riscv: selftests: Generate ISA extension reg_list using macrosAnup Patel1-255/+76
[ Upstream c19829ba1e4d119e69b1ac9a96d5a0b86f7233e9 ] Various ISA extension reg_list have common pattern so let us generate these using macros. We define two macros for the above purpose: 1) KVM_ISA_EXT_SIMPLE_CONFIG - Macro to generate reg_list for ISA extension without any additional ONE_REG registers 2) KVM_ISA_EXT_SUBLIST_CONFIG - Macro to generate reg_list for ISA extension with additional ONE_REG registers This patch also adds the missing config for svnapot. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22RISC-V: KVM: remove a redundant condition in kvm_arch_vcpu_ioctl_run()Chao Du1-2/+1
[ Upstream commit bcd08e9bae57b5585e438b7fa58aba4b145a59cf ] The latest ret value is updated by kvm_riscv_vcpu_aia_update(), the loop will continue if the ret is less than or equal to zero. So the later condition will never hit. Thus remove it. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22riscv: kvm: use ".L" local labels in assembly when applicableClément Léger1-2/+2
[ Upstream commit e5ff012743cbc3cf13d2243aaaf032a2ca4d0791 ] For the sake of coherency, use local labels in assembly when applicable. This also avoid kprobes being confused when applying a kprobe since the size of function is computed by checking where the next visible symbol is located. This might end up in computing some function size to be way shorter than expected and thus failing to apply kprobes to the specified offset. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22riscv: kvm: Use SYM_*() assembly macros instead of deprecated onesClément Léger1-16/+12
[ Upstream commit 683c5bbbf6aea247bc95a7eb9fdfba4fcc8c909a ] ENTRY()/END()/WEAK() macros are deprecated and we should make use of the new SYM_*() macros [1] for better annotation of symbols. Replace the deprecated ones with the new ones and fix wrong usage of END()/ENDPROC() to correctly describe the symbols. [1] https://docs.kernel.org/core-api/asm-annotations.html Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-05-22riscv: kernel: Use correct SYM_DATA_*() macro for dataClément Léger1-5/+4
[ Upstream commit 4cc0d8a3f109fbdd8100ed88fc9417203a5d5b4e ] Some data were incorrectly annotated with SYM_FUNC_*() instead of SYM_DATA_*() ones. Use the correct ones. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231024132655.730417-4-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-05-22riscv: Use SYM_*() assembly macros instead of deprecated onesClément Léger17-74/+60
[ Upstream commit 76329c693924d8f37afbf361f0d8daab594e1644 ] ENTRY()/END()/WEAK() macros are deprecated and we should make use of the new SYM_*() macros [1] for better annotation of symbols. Replace the deprecated ones with the new ones and fix wrong usage of END()/ENDPROC() to correctly describe the symbols. [1] https://docs.kernel.org/core-api/asm-annotations.html Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231024132655.730417-3-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-05-22riscv: use ".L" local labels in assembly when applicableClément Léger4-44/+44
[ Upstream commit b18f7296fbfdb2ad0871f00f3042fc74663d52ac ] For the sake of coherency, use local labels in assembly when applicable. This also avoid kprobes being confused when applying a kprobe since the size of function is computed by checking where the next visible symbol is located. This might end up in computing some function size to be way shorter than expected and thus failing to apply kprobes to the specified offset. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231024132655.730417-2-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-05-22KVM: riscv: selftests: Fix get-reg-list print_reg defaultsAndrew Jones1-4/+6
[ Upstream commit 3279f526952f82b2967663c36c12a01f125cbbfd ] print_reg() will print everything it knows when it encounters a register ID it's unfamiliar with in the default cases of its decoding switches. Fix several issues with these (until now, never tested) paths; missing newlines in printfs, missing complement operator in mask, and missing return in order to avoid continuing to decode. Fixes: 62d0c458f828 ("KVM: riscv: selftests: get-reg-list print_reg should never fail") Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Haibo Xu <haibo1.xu@intel.com> Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-21 00:10:50 +0300