starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-05-22	KVM: riscv: selftests: Add SBI DBCN extension to get-reg-list test	Anup Patel	1	-0/+2
2024-05-22	KVM: riscv: selftests: get-reg-list print_reg should never fail	Andrew Jones	1	-51/+42
2024-05-22	KVM: riscv: selftests: Add condops extensions to get-reg-list test	Anup Patel	1	-0/+17
2024-05-22	KVM: riscv: selftests: Add smstateen registers to get-reg-list test	Anup Patel	1	-0/+34
2024-05-22	KVM: riscv: selftests: Add senvcfg register to get-reg-list test	Anup Patel	1	-0/+3
2024-05-22	KVM: selftests: Add array order helpers to riscv get-reg-list	Andrew Jones	1	-39/+47
2024-05-22	MAINTAINERS: RISC-V: KVM: Add another kselftests path	Andrew Jones	1	-0/+1
2024-05-21	work around gcc bugs with 'asm goto' with outputs	Linus Torvalds	5	-14/+14
2024-05-21	riscv: Avoid code duplication with generic bitops implementation	Xiao Wang	5	-122/+48
2024-05-21	riscv: Decouple emulated unaligned accesses from access speed	Charlie Jenkins	3	-13/+29
2024-05-21	riscv: Only check online cpus for emulated accesses	Charlie Jenkins	1	-1/+1
2024-05-21	riscv: fix __user annotation in traps_misaligned.c	Ben Dooks	1	-3/+3
2024-05-21	RISC-V: Remove __init on unaligned_emulation_finish()	Evan Green	1	-1/+1
2024-05-21	riscv: lib: Introduce has_fast_unaligned_access()	Charlie Jenkins	3	-11/+13
2024-05-21	riscv: Add checksum library	Charlie Jenkins	3	-0/+338
2024-05-21	riscv: Add checksum header	Charlie Jenkins	1	-0/+82
2024-05-21	riscv: Add static key for misaligned accesses	Charlie Jenkins	2	-3/+89
2024-05-21	riscv: Save/restore envcfg CSR during CPU suspend	Samuel Holland	2	-0/+5
2024-05-21	riscv: Add a custom ISA extension for the [ms]envcfg CSR	Samuel Holland	2	-2/+13
2024-05-21	riscv: Fix enabling cbo.zero when running in M-mode	Samuel Holland	2	-1/+3
2024-05-21	tools: riscv: Add header file vdso/processor.h	Haibo Xu	1	-0/+32
2024-05-21	tools: riscv: Add header file csr.h	Haibo Xu	1	-0/+541
2024-05-21	RISC-V: Implement archrandom when Zkr is available	Samuel Ortiz	2	-0/+81
2024-05-21	riscv: Optimize hweight API with Zbb extension	Xiao Wang	2	-1/+81
2024-05-21	RISC-V: hwprobe: Introduce which-cpus flag	Andrew Jones	4	-10/+114
2024-05-21	RISC-V: Move the hwprobe syscall to its own file	Andrew Jones	3	-321/+425
2024-05-21	riscv: hwprobe: export Zicond extension	Clément Léger	3	-0/+7
2024-05-21	riscv: hwprobe: export Zacas ISA extension	Clément Léger	3	-0/+6
2024-05-21	riscv: hwprobe: export Ztso ISA extension	Clément Léger	3	-0/+6
2024-05-21	riscv: hwprobe: export Zfa ISA extension	Clément Léger	3	-0/+6
2024-05-21	riscv: hwprobe: export Zvfh[min] ISA extensions	Clément Léger	3	-0/+12
2024-05-21	riscv: hwprobe: export Zhintntl ISA extension	Clément Léger	3	-0/+5
2024-05-21	riscv: hwprobe: export Zfh[min] ISA extensions	Clément Léger	3	-0/+13
2024-05-21	riscv: hwprobe: export vector crypto ISA extensions	Clément Léger	3	-0/+53
2024-05-21	riscv: hwprobe: add support for scalar crypto ISA extensions	Clément Léger	3	-0/+46
2024-05-21	riscv: hwprobe: export missing Zbc ISA extension	Clément Léger	3	-0/+5
2024-05-21	riscv: add ISA extension parsing for Zacas	Clément Léger	2	-0/+2
2024-05-21	riscv: add ISA extension parsing for Ztso	Clément Léger	2	-0/+2
2024-05-21	riscv: add ISA extension parsing for Zfa	Clément Léger	2	-0/+2
2024-05-21	riscv: add ISA extension parsing for Zvfh[min]	Clément Léger	2	-0/+4
2024-05-21	riscv: add ISA extension parsing for Zihintntl	Clément Léger	2	-0/+2
2024-05-21	riscv: add ISA extension parsing for Zfh/Zfh[min]	Clément Léger	2	-0/+4
2024-05-21	riscv: add ISA extension parsing for vector crypto	Clément Léger	2	-0/+74
2024-05-21	riscv: add ISA extension parsing for scalar crypto	Evan Green	3	-24/+109
2024-05-21	riscv: add ISA extension parsing for Zbc	Clément Léger	2	-0/+2
2024-05-21	RISC-V: hwprobe: Move ZICBOP extension to back	Ji Sheng Teoh	2	-3/+3
2024-05-21	selftests: riscv: Generalize mm selftests	Charlie Jenkins	3	-89/+67
2024-05-21	RISC-V: hwprobe: Clarify cpus size parameter	Andrew Jones	6	-30/+23
2024-05-21	RISC-V: selftests: cbo: Ensure asm operands match constraints, take 2	Andrew Jones	2	-1/+11
2024-05-21	RISC-V: selftests: cbo: Ensure asm operands match constraints	Andrew Jones	1	-10/+8