summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2024-03-07Merge branch 'starfive-6.6.10-dubhe-emphasize-l2-cache-compatibility' into ↵REL_DUBHE_MAR2024starfive-6.6.10-dubheleyfoon.tan6-22/+22
'starfive-6.6.10-dubhe' cache: dubhe: emphasize controller's L2 cache compatibility See merge request starfive-tech/linux!276
2024-03-07dt-bindings: cache: starfive: emphasize controller's L2 cache compatibilityJi Sheng Teoh1-7/+7
Dubhe cache controller handles level 2 cache. Update dt-bindings to emphasize Dubhe's L2 cache controller compatibility. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-03-07riscv: dts: starfive: dubhe: update L2 cache compatibleJi Sheng Teoh2-3/+3
Following the change to emphasize L2 cache compatibility in Dubhe cache controller, update the compatible string to reflect the changes. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-03-07cache: dubhe: emphasize controller's L2 cache compatibilityJi Sheng Teoh3-12/+12
Dubhe cache controller handles level 2 cache. To avoid confusion, emphasize it's L2 cache compatibility through driver name update and Kconfig description. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-03-07Merge branch 'starfive-6.6.10-dubhe-use-4k-sector' into 'starfive-6.6.10-dubhe'leyfoon.tan1-1/+1
riscv: configs: dubhe: Enable 4K erase sector for QSPI See merge request starfive-tech/linux!275
2024-03-06riscv: configs: dubhe: Enable 4K erase sector for QSPIJi Sheng Teoh1-1/+1
Dubhe QSPI uses 64KB erase sector by default and causes MTD driver to warn about "partition doesn't start on an erase/write block boundary -- force read-only", changing r/w partition to read only to avoid unintended access to adjacent partition. Update the erase sector size to 4KB to ensure the partition size is multiple of flash block-size to meet the flash block boundary requirement, and allowing r/w access to the QSPI partition. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-03-04Merge branch 'starfive-6.6.10-dubhe-tftp' into 'starfive-6.6.10-dubhe'leyfoon.tan1-0/+2
riscv: configs: dubhe: Enable iptables raw table and CT target See merge request starfive-tech/linux!270
2024-02-28riscv: configs: dubhe: Enable iptables raw table and CT targetTan En De1-0/+2
Needed to properly forward TFTP to KVM guest behind NAT, by marking packets to use TFTP-specific NAT helper module. Usage example (setup in host before starting guest): modprobe nf_nat_tftp iptables -t raw -I PREROUTING -j CT -p udp -m udp --dport 69 --helper tftp Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2024-02-27Merge branch 'starfive-6.6.10-dubhe-add-zicbop' into 'starfive-6.6.10-dubhe'leyfoon.tan8-371/+298
riscv: dts: starfive: dubhe: Add ZICBOP isa-extension See merge request starfive-tech/linux!265
2024-02-22riscv: dts: starfive: dubhe: Add ZICBOP isa-extensionJi Sheng Teoh1-2/+2
Add ZICBOP isa-extension support for Dubhe-70. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-02-21riscv: xchg: Prefetch the destination word for sc.wGuo Ren1-1/+3
The cost of changing a cacheline from shared to exclusive state can be significant, especially when this is triggered by an exclusive store, since it may result in having to retry the transaction. This patch makes use of prefetch.w to prefetch cachelines for write prior to lr/sc loops when using the xchg_small atomic routine. This patch is inspired by commit: 0ea366f5e1b6 ("arm64: atomics: prefetch the destination word for write prior to stxr"). Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org>
2024-02-21riscv: Add ARCH_HAS_PRETCHW support with ZicbopGuo Ren1-0/+16
Enable Linux prefetchw primitive with Zicbop cpufeature, which preloads cache line into L1 cache for the next write operation. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org>
2024-02-21riscv: Add Zicbop instruction definitions & cpufeatureGuo Ren4-0/+77
Cache-block prefetch instructions are HINTs to the hardware to indicate that software intends to perform a particular type of memory access in the near future. This patch adds prefetch.i, prefetch.r and prefetch.w instruction definitions by RISCV_ISA_EXT_ZICBOP cpufeature. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org>
2024-02-21riscv/cmpxchg: Implement xchg for variables of size 1 and 2Leonardo Bras1-0/+31
xchg for variables of size 1-byte and 2-bytes is not yet available for riscv, even though its present in other architectures such as arm64 and x86. This could lead to not being able to implement some locking mechanisms or requiring some rework to make it work properly. Implement 1-byte and 2-bytes xchg in order to achieve parity with other architectures. Signed-off-by: Leonardo Bras <leobras@redhat.com>
2024-02-21riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2Leonardo Bras1-0/+34
cmpxchg for variables of size 1-byte and 2-bytes is not yet available for riscv, even though its present in other architectures such as arm64 and x86. This could lead to not being able to implement some locking mechanisms or requiring some rework to make it work properly. Implement 1-byte and 2-bytes cmpxchg in order to achieve parity with other architectures. Signed-off-by: Leonardo Bras <leobras@redhat.com>
2024-02-21riscv/atomic.h : Deduplicate arch_atomic.*Leonardo Bras1-88/+76
Some functions use mostly the same asm for 32-bit and 64-bit versions. Make a macro that is generic enough and avoid code duplication. (This did not cause any change in generated asm) Signed-off-by: Leonardo Bras <leobras@redhat.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
2024-02-21riscv/cmpxchg: Deduplicate cmpxchg() asm and macrosLeonardo Bras1-162/+33
In this header every cmpxchg define (_relaxed, _acquire, _release, vanilla) contain it's own asm file, both for 4-byte variables an 8-byte variables, on a total of 8 versions of mostly the same asm. This is usually bad, as it means any change may be done in up to 8 different places. Unify those versions by creating a new define with enough parameters to generate any version of the previous 8. Then unify the result under a more general define, and simplify arch_cmpxchg* generation (This did not cause any change in generated asm) Signed-off-by: Leonardo Bras <leobras@redhat.com> Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
2024-02-21riscv/cmpxchg: Deduplicate xchg() asm functionsLeonardo Bras1-115/+23
In this header every xchg define (_relaxed, _acquire, _release, vanilla) contain it's own asm file, both for 4-byte variables an 8-byte variables, on a total of 8 versions of mostly the same asm. This is usually bad, as it means any change may be done in up to 8 different places. Unify those versions by creating a new define with enough parameters to generate any version of the previous 8. Then unify the result under a more general define, and simplify arch_xchg* generation. (This did not cause any change in generated asm) Signed-off-by: Leonardo Bras <leobras@redhat.com> Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
2024-02-19riscv: dts: starfive: Remove unused clock gtxcLey Foon Tan2-4/+2
Remove unused clock "gtxc". Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2024-02-07Merge branch 'starfive-6.6.10-dubhe-Add-Svinval' into 'starfive-6.6.10-dubhe'leyfoon.tan2-8/+59
riscv: mm: use svinval instructions instead of sfence.vma See merge request starfive-tech/linux!264
2024-01-31riscv: mm: use svinval instructions instead of sfence.vmaMayuresh Chitale2-8/+59
When svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma: sfence.w.inval svinval.vma . . svinval.vma sfence.inval.ir The maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to 64. This is required to avoid soft lockups and the approach is similar to that used in arm64. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2024-01-26Merge branch 'starfive-6.6.10-dubhe-Add-zihintpause' into ↵leyfoon.tan1-2/+2
'starfive-6.6.10-dubhe' riscv: dts: starfive: dubhe: Add zihintpause isa-extension See merge request starfive-tech/linux!259
2024-01-24riscv: dts: starfive: dubhe: Add zihintpause isa-extensionJi Sheng Teoh1-2/+2
Add zihintpause isa-extension which is supported in Dubhe-80 and Dubhe-90 Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-22riscv: dts: starfive: dubhe: Update CPU isa-extensionsLey Foon Tan2-12/+14
Fix DT binding check errors. Change "b" to "zba", "zbb", "zbc" and "zbs". Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2024-01-22riscv: dts: starfive: dubhe: Update L2 DT nodeLey Foon Tan4-7/+37
Dubhe-80 and Dubhe-70 use private L2, Dubhe-90 uses shared L2. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2024-01-22dt-bindings: riscv: Add Zicond extension entryAnup Patel1-0/+6
[ upstream commit 00c6f39c8247b0a5ddca4586d43aec1af7cbccb6 ] Add an entry for the Zicond extension to the riscv,isa-extensions property. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-17Merge branch 'starfive-6.6.10-dubhe-Add-Dubhe70' into 'starfive-6.6.10-dubhe'leyfoon.tan20-204/+380
arch: riscv: starfive: Add Dubhe70 support See merge request starfive-tech/linux!246
2024-01-16perf vendor events riscv: starfive: add RISC-V firmware JSON fileJi Sheng Teoh1-0/+68
Add standard RISC-V firmware events to support monitoring of firmware events in StarFive's Dubhe platform. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-16riscv: dts: starfive: Convert to riscv,isa-base and riscv,isa-extensionsJi Sheng Teoh1-2/+8
Update StarFive's Dubhe80 and Dubhe90 device tree to use riscv,isa-base and riscv,extensions property to express RISC-V profiles and extensions supported by the platforms. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-16perf vendor events riscv: add StarFive Dubhe-70 JSON fileJi Sheng Teoh2-174/+1
Since Dubhe-70, Dubhe-80, and Dubhe-90 share the same perf JSON file in starfive/dubhe-80/common.json, update the mapfile.csv to cater for this 3 cpu and remove redundant starfive/dubhe-90. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-16riscv: dts: starfive: Add StarFive Dubhe-70 device treeJi Sheng Teoh3-0/+54
Add device tree support for StarFive's Dubhe-70. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-16dt-bindings: riscv: Add StarFive Dubhe-70 compatiblesJi Sheng Teoh1-0/+1
Add new compatible string for Dubhe-70. Dubhe-70 is a low power RISC-V cpu core from StarFive Technology. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-16arch: riscv: errata: bypass envcfg CSRJi Sheng Teoh3-12/+43
CPU core that supports H-extension v0.6.1 does not have henvcfg and senvcfg CSR register support, accessing it will cause kernel to throw illegal access warning. This patch introduce errata for platform that does not support accessing the CSR by bypassing it through the usage of static key. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2024-01-09RISC-V: KVM: Allow Zicond extension for Guest/VMAnup Patel2-0/+3
[ Upstream commit df68f4d8cb49 ] We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zicond extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISCV: KVM: Add sstateen0 to ONE_REGMayuresh Chitale2-2/+70
[ Upstream commit c04913f2b54e ] Add support for sstateen0 CSR to the ONE_REG interface to allow its access from user space. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISCV: KVM: Add sstateen0 context save/restoreMayuresh Chitale3-0/+21
[ Upstream commit 81f0f314fec9 ] Define sstateen0 and add sstateen0 save/restore for guest VCPUs. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISCV: KVM: Add senvcfg context save/restoreMayuresh Chitale3-0/+19
[ Upstream commit db3c01c7a308 ] Add senvcfg context save/restore for guest VCPUs and also add it to the ONE_REG interface to allow its access from user space. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISC-V: KVM: Enable Smstateen accessesMayuresh Chitale5-1/+38
[ Upstream commit d21b5d342fc1 ] Configure hstateen0 register so that the AIA state and envcfg are accessible to the vcpus. This includes registers such as siselect, sireg, siph, sieh and all the IMISC registers. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISC-V: KVM: Add kvm_vcpu_configMayuresh Chitale2-13/+21
[ Upstream commit fe0bab701e3b ] Add a placeholder for all registers such as henvcfg, hstateen etc which have 'static' configurations depending on extensions supported by the guest. The values are derived once and are then subsequently written to the corresponding CSRs while switching to the vcpu. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISC-V: Detect Zicond from ISA stringAnup Patel2-0/+2
[ Upstream commit 662a601aa355 ] The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension. Let us detect Zicond extension from ISA string available through DT or ACPI. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISC-V: Detect Smstateen extensionMayuresh Chitale2-0/+2
[ Upstream commit 9dbaf381008d ] Extend the ISA string parsing to detect the Smstateen extension. If the extension is enabled then access to certain 'state' such as AIA CSRs in VS mode is controlled by *stateen0 registers. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2024-01-09RISC-V: Enable cbo.zero in usermodeAndrew Jones6-0/+32
[ Upstream commit 43c16d51a19b ] When Zicboz is present, enable its instruction (cbo.zero) in usermode by setting its respective senvcfg bit. We don't bother trying to set this bit per-task, which would also require an interface for tasks to request enabling and/or disabling. Instead, permanently set the bit for each hart which has the extension when bringing it online. This patch also introduces riscv_cpu_has_extension_[un]likely() functions to check a specific hart's ISA bitmap for extensions. Prior to checking the specific hart's bitmap in these functions we try the bitmap which represents the LCD of extensions, but only when we know it will use its optimized, alternatives path by gating its call on CONFIG_RISCV_ALTERNATIVE. When alternatives are used, the compiler ensures that the invocation of the LCD search becomes a constant true or false. When it's true, even the new functions will completely vanish from their callsites. OTOH, when the LCD check is false, we need to do a search of the hart's ISA bitmap. Had we also checked the LCD bitmap without the use of alternatives, then we would have ended up with two bitmap searches instead of one. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230918131518.56803-10-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-09RISC-V: Make zicbom/zicboz errors consistentAndrew Jones1-2/+2
[ Upstream commit 181f2a28d688 ] commit c818fea83de4 ("riscv: say disabling zicbom if no or bad riscv,cbom-block-size found") improved the error messages for zicbom but zicboz was missed since its patches were in flight at the same time. Get 'em now. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230918131518.56803-9-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-09Revert "arch: riscv: kvm: Temporarily comment out henvcfg-related code"Ji Sheng Teoh1-2/+1
This reverts commit d181fd3d146844db2d5095ae208b8664160e4eb0. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-09Revert "riscv: kvm: Fix compilation warning for unused ↵Ji Sheng Teoh1-2/+0
kvm_riscv_vcpu_update_config()" This reverts commit 081a4205bbea5784e9815e6fd11d7b865cd6b9ff. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2024-01-08RISC-V: hwprobe: Expose Zicboz extension and its block sizeAndrew Jones4-15/+41
[ Upstream commit 9c7646d5ffd2b8bf720a0b77897f6c5095dfc53b ] Expose Zicboz through hwprobe and also provide a key to extract its respective block size. Opportunistically add a macro and apply it to current extensions in order to avoid duplicating code. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Evan Green <evan@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230918131518.56803-11-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-08riscv: dts: starfive: dubhe: Move pmu DT node out of soc nodeLey Foon Tan1-41/+40
PMU hardware is in the CPU core, move the pmu DT node out of the soc node. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2024-01-08riscv: dts: starfive: dubhe: Add cpu-map DT nodeLey Foon Tan1-0/+12
Add cpu-map DT node. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2024-01-08riscv: dts: starfive: dubhe: Update Dubhe CPU compatible stringsLey Foon Tan3-1/+4
Change to "starfive,dubhe-80" and "starfive,dubhe-90" compatible strings. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2024-01-08dt-bindings: riscv: Update StarFive Dubhe-80 and Dubhe-90 compatiblesLey Foon Tan1-1/+2
Change to use starfive,dubhe-80 and starfive,dubhe-90 compatible strings. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-21 00:33:16 +0300