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2023-12-04net: phylink: Assign link config in phylink_create()Genevieve Chan1-4/+4
This patch parse the following config to a struct phylink: * speed = 10Mbps * duplex = full * pause = RX on, TX on Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Set ip in boot args and enable gmacGenevieve Chan1-1/+2
Set ip at kernel bootargs with the following parameters: * Client IP Address: autoconfg using DHCP * Server IP Address: not defined * Gateway IP Address: 192.168.152.1 * Netmask: 255.255.255.0 * Network device to use: eth0 * Autoconfiguration: dhcp Enable gmac driver. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04net: phy: marvell: Set autonegotiation to OFF by default upon initGenevieve Chan1-0/+2
This patch set AUTONEG_DISABLE during init to disable autonegotiation by default. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: configs: Dubhe: Add configs for initramfs sourceGenevieve Chan1-0/+2
The Dubhe ace_20221130 bitfile does not support GMAC. This patch re-enabled booting kernel through initramfs source "rootfs.cpio" Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Disable GMAC and remove NFSGenevieve Chan1-2/+1
The ace_20221130 version does not have GMAC support. Disable GMAC driver and remove NFS in the bootargs. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Enable NFSGenevieve Chan1-1/+1
This patch adds NFS configuration in the bootargs. The bootargs for NFS is set with the following parameters: * Client IP Address: 192.168.152.100 * Server IP Address: 192.168.153.221 * Gateway IP Address: 192.168.152.1 * Netmask: 255.255.255.0 * Network device to use: eth0 * Autoconfiguration: off * NFS root dir: /home/nfsroot Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Fix ethernet max-speed to 10Mb/sLey Foon Tan1-0/+11
Fix ethernet max-speed to 10Mb/s for FPGA. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: starfive: Add DMA non-coherent supportLey Foon Tan2-0/+56
Enable arch_*dma* implementation. Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2023-12-04riscv: sbi: Add support for sbi_cache_flush and sbi_cache_invalidateLey Foon Tan2-0/+38
This patch introduces the support for GMAC drivers to perform flush and invalidate of L2 Cache: * sbi_cache_invalidate(): Invalidate L2 cache for data passed from GMAC to CPU * sbi_cache_flush(): Flush L2 cache for data passed from CPU to GMAC Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: configs: Dubhe: Add configs for GMAC driver in StarFive DubheLey Foon Tan1-5/+31
This patch add configs for StarFive Dubhe GMAC driver Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Add GMAC DT nodeLey Foon Tan2-0/+58
This patch adds GMAC device tree node. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04dt-bindings: net: Add bindings for StarFive dwmactanchunhau1-0/+104
Add StarFive dwmac dt-binding doc. Signed-off-by: Chun Hau Tan <chunhau.tan@starfivetech.com>
2023-12-04net: stmmac: Add StarFive dwmac supportLey Foon Tan3-0/+162
Add StarFive dwmac support. Signed-off-by: Tan Chun Hau <chunhau.tan@starfivetech.com> Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2023-12-04riscv: starfive: dubhe: Enable CONFIG_HZ_10Ley Foon Tan1-0/+1
Dubhe FPGA platform is running at lower frequency, changes to use 10 Hz. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04kernel: Fix 'mult' overflow if using 10 HzLey Foon Tan5-6/+7
Change 'mult' to 64-bit (u64) to fix overflow warning if using 10 Hz jiffies. ./include/vdso/jiffies.h:9:19: warning: unsigned conversion from 'long int' to 'unsigned int' changes value from '6400000000' to '2105032704' [-Woverflow] 9 | #define TICK_NSEC ((NSEC_PER_SEC+HZ/2)/HZ) | ^ kernel/time/jiffies.c:38:35: note: in expansion of macro 'TICK_NSEC' 38 | .mult = TICK_NSEC << JIFFIES_SHIFT, /* details above */ | ^~~~~~~~~ Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04kernel: Add 10 Hz supportLey Foon Tan2-1/+8
Add 10 Hz support for FPGA system that run on lower frequency. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: defconfig: Add defconfigs for perf annotateGenevieve Chan1-0/+3
Include configs for perf annotate Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04mtd: spi-nor: macronix: Add support for MX66U1G45GLey Foon Tan1-0/+3
The Macronix MX66U1G45G is a 1.8V, 1Gbit (128MB) flash device that supports x1, x2, or x4 operation. The MX66U1G45G is the smaller sibling of the mx66u2g45g that is already supported. Tested on StarFive Dubhe hardware on FPGA with a SiFive SPI controller. Validated by erase, read back, write and read back. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04arch: riscv: starfive: Increase RCU stall timeout and remove watchdog configGenevieve Chan1-2/+1
This patch increases RCU stall timeout to max value of 300s and removes the watchdog work queue stall. This is done to increase the timeout of stalls. This allows fpga design with lower frequency to have more time to load finish the design. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Added device tree for dual fpgaLey Foon Tan2-1/+52
This patch adds the device tree for dual core fpga to compile Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Update Dubhe compatible stringLey Foon Tan1-2/+2
Change Dubhe CPU compatible string to "starfive,dubhe". Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2023-12-04dt-bindings: riscv: Add compatible string for StarFive Dubhe CPULey Foon Tan1-0/+1
Add compatible string "starfive,dubhe" for StarFive Dubhe CPU. Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2023-12-04perf vendor events riscv: Redirect the path of sys to riscv cpu IDGenevieve Chan1-1/+1
This patch renamed the riscv CPU ID path location Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04perf vendor events riscv: Add JSON metrics for Starfive Dubhe PerfGenevieve Chan8-0/+826
This patch adds PMU event mapping for Starfive Dubhe hardware performance unit Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04perf vendor events riscv: Added Dubhe mapfileGenevieve Chan1-0/+1
This patch added the mapfile for riscv Dubhe to support for custom events. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Added vector PMU events to dtsGenevieve Chan1-0/+5
This patch includes the vector PMU events using many-many events mapping Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Use many-many mapping of raw PMU eventsGenevieve Chan1-140/+27
This patch replaces one-one mapping of raw event to many-many mapping bitmap encoding Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04RISC-V: Added HiFive Unmatched PMU eventsJoão Mário Domingos4-0/+182
This patch contains all the available events for the HiFive Unmatched performance monitoring unit. Depends on patch [3], for the base mapfile.csv file. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
2023-12-04RISC-V: Added generic pmu-events mapfileJoão Mário Domingos2-0/+34
The pmu-events now supports custom events for RISC-V, plus the cycle, time and instret events were defined. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
2023-12-04RISC-V: Support CPUID for risc-v in perfJoão Mário Domingos3-0/+85
This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
2023-12-04RISC-V: Create unique identification for SoC PMUJoão Mário Domingos2-0/+50
The SBI PMU platform driver did not provide any identification for perf events matching. This patch introduces a new sysfs file inside the platform device (soc:pmu/id) for pmu identification. The identification is a 64-bit value generated as: [63-32]: mvendorid; [31]: marchid[MSB]; [30-16]: marchid[15-0]; [15-0]: mimpid[15MSBs]; The CSRs are detailed in the RISC-V privileged spec [1]. The marchid is split in MSB + 15LSBs, due to the MSB being used for open-source architecture identification. [1] https://github.com/riscv/riscv-isa-manual Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
2023-12-04riscv: dts: starfive: dubhe: Add pmu device tree nodeGenevieve Chan1-1/+174
Include pmu device tree node for pre-defined and raw events mapping to Dubhe dts Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: config: Enable Perf configs in Starfive Dubhe defconfigGenevieve Chan1-0/+1
Add config for perf in dubhe FPGA defconfig Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Add cpu1 device tree nodeLey Foon Tan1-2/+28
Add cpu1 device tree node to Dubhe dts. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: config: Add Starfive Dubhe defconfigLey Foon Tan1-0/+114
Add Dubhe FPGA defconfig. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: Add StarFive Dubhe SoC supportLey Foon Tan1-0/+8
Add StarFive Dubhe Kconfig option which selects SoC specific and common drivers that is required for this SoC. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: Add Dubhe FPGA device treeLey Foon Tan3-0/+150
Add Dubhe FPGA device tree support. Dubhe is a RISC-V CPU with ISA rv64imafdcbhnv. Dubhe FPGA consists of one Dubhe CPU, PLIC, CLINT, SPI, UART and 8GB memory in hardware. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: Implement non-coherent DMA support via SiFive cache flushingEmil Renner Berthing2-4/+39
This variant is used on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-12-04riscv: optimized memsetMatteo Croce7-138/+44
The generic memset is defined as a byte at time write. This is always safe, but it's slower than a 4 byte or even 8 byte write. Write a generic memset which fills the data one byte at time until the destination is aligned, then fills using the largest size allowed, and finally fills the remaining data one byte at time. Signed-off-by: Matteo Croce <mcroce@microsoft.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-12-04riscv: optimized memmoveMatteo Croce5-322/+26
When the destination buffer is before the source one, or when the buffers doesn't overlap, it's safe to use memcpy() instead, which is optimized to use a bigger data size possible. Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2023-12-04riscv: optimized memcpyMatteo Croce6-116/+104
Write a C version of memcpy() which uses the biggest data size allowed, without generating unaligned accesses. The procedure is made of three steps: First copy data one byte at time until the destination buffer is aligned to a long boundary. Then copy the data one long at time shifting the current and the next u8 to compose a long at every cycle. Finally, copy the remainder one byte at time. On a BeagleV, the TCP RX throughput increased by 45%: before: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44840 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 76.4 MBytes 641 Mbits/sec 27 624 KBytes [ 5] 1.00-2.00 sec 72.5 MBytes 608 Mbits/sec 0 708 KBytes [ 5] 2.00-3.00 sec 73.8 MBytes 619 Mbits/sec 10 451 KBytes [ 5] 3.00-4.00 sec 72.5 MBytes 608 Mbits/sec 0 564 KBytes [ 5] 4.00-5.00 sec 73.8 MBytes 619 Mbits/sec 0 658 KBytes [ 5] 5.00-6.00 sec 73.8 MBytes 619 Mbits/sec 14 522 KBytes [ 5] 6.00-7.00 sec 73.8 MBytes 619 Mbits/sec 0 621 KBytes [ 5] 7.00-8.00 sec 72.5 MBytes 608 Mbits/sec 0 706 KBytes [ 5] 8.00-9.00 sec 73.8 MBytes 619 Mbits/sec 20 580 KBytes [ 5] 9.00-10.00 sec 73.8 MBytes 619 Mbits/sec 0 672 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 736 MBytes 618 Mbits/sec 71 sender [ 5] 0.00-10.01 sec 733 MBytes 615 Mbits/sec receiver after: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44864 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 109 MBytes 912 Mbits/sec 48 559 KBytes [ 5] 1.00-2.00 sec 108 MBytes 902 Mbits/sec 0 690 KBytes [ 5] 2.00-3.00 sec 106 MBytes 891 Mbits/sec 36 396 KBytes [ 5] 3.00-4.00 sec 108 MBytes 902 Mbits/sec 0 567 KBytes [ 5] 4.00-5.00 sec 106 MBytes 891 Mbits/sec 0 699 KBytes [ 5] 5.00-6.00 sec 106 MBytes 891 Mbits/sec 32 414 KBytes [ 5] 6.00-7.00 sec 106 MBytes 891 Mbits/sec 0 583 KBytes [ 5] 7.00-8.00 sec 106 MBytes 891 Mbits/sec 0 708 KBytes [ 5] 8.00-9.00 sec 106 MBytes 891 Mbits/sec 28 433 KBytes [ 5] 9.00-10.00 sec 108 MBytes 902 Mbits/sec 0 591 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 1.04 GBytes 897 Mbits/sec 144 sender [ 5] 0.00-10.01 sec 1.04 GBytes 894 Mbits/sec receiver And the decreased CPU time of the memcpy() is observable with perf top. This is the `perf top -Ue task-clock` output when doing the test: before: Overhead Shared O Symbol 42.22% [kernel] [k] memcpy 35.00% [kernel] [k] __asm_copy_to_user 3.50% [kernel] [k] sifive_l2_flush64_range 2.30% [kernel] [k] stmmac_napi_poll_rx 1.11% [kernel] [k] memset after: Overhead Shared O Symbol 45.69% [kernel] [k] __asm_copy_to_user 29.06% [kernel] [k] memcpy 4.09% [kernel] [k] sifive_l2_flush64_range 2.77% [kernel] [k] stmmac_napi_poll_rx 1.24% [kernel] [k] memset Signed-off-by: Matteo Croce <mcroce@microsoft.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-12-03Linux 6.1.65Greg Kroah-Hartman1-1/+1
Link: https://lore.kernel.org/r/20231130162135.977485944@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Shuah Khan <skhan@linuxfoundation.org> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: SeongJae Park <sj@kernel.org> Tested-by: Ron Economos <re@w6rz.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03io_uring: fix off-by one bvec indexKeith Busch1-1/+1
commit d6fef34ee4d102be448146f24caf96d7b4a05401 upstream. If the offset equals the bv_len of the first registered bvec, then the request does not include any of that first bvec. Skip it so that drivers don't have to deal with a zero length bvec, which was observed to break NVMe's PRP list creation. Cc: stable@vger.kernel.org Fixes: bd11b3a391e3 ("io_uring: don't use iov_iter_advance() for fixed buffers") Signed-off-by: Keith Busch <kbusch@kernel.org> Link: https://lore.kernel.org/r/20231120221831.2646460-1-kbusch@meta.com Signed-off-by: Jens Axboe <axboe@kernel.dk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03USB: dwc3: qcom: fix wakeup after probe deferralJohan Hovold1-4/+4
commit 41f5a0973259db9e4e3c9963d36505f80107d1a0 upstream. The Qualcomm glue driver is overriding the interrupt trigger types defined by firmware when requesting the wakeup interrupts during probe. This can lead to a failure to map the DP/DM wakeup interrupts after a probe deferral as the firmware defined trigger types do not match the type used for the initial mapping: irq: type mismatch, failed to map hwirq-14 for interrupt-controller@b220000! irq: type mismatch, failed to map hwirq-15 for interrupt-controller@b220000! Fix this by not overriding the firmware provided trigger types when requesting the wakeup interrupts. Fixes: a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver") Cc: stable@vger.kernel.org # 4.18 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20231120161607.7405-3-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03USB: dwc3: qcom: fix software node leak on probe errorsJohan Hovold1-5/+8
commit 9feefbf57d92e8ee293dad67585d351c7d0b6e37 upstream. Make sure to remove the software node also on (ACPI) probe errors to avoid leaking the underlying resources. Note that the software node is only used for ACPI probe so the driver unbind tear down is updated to match probe. Fixes: 8dc6e6dd1bee ("usb: dwc3: qcom: Constify the software node") Cc: stable@vger.kernel.org # 5.12 Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20231117173650.21161-3-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03usb: dwc3: set the dma max_seg_sizeRicardo Ribalda1-0/+2
commit 8bbae288a85abed6a1cf7d185d8b9dc2f5dcb12c upstream. Allow devices to have dma operations beyond 4K, and avoid warnings such as: DMA-API: dwc3 a600000.usb: mapping sg segment longer than device claims to support [len=86016] [max=65536] Cc: stable@vger.kernel.org Fixes: 72246da40f37 ("usb: Introduce DesignWare USB3 DRD Driver") Reported-by: Zubin Mithra <zsm@chromium.org> Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Link: https://lore.kernel.org/r/20231026-dwc3-v2-1-1d4fd5c3e067@chromium.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03usb: dwc3: Fix default mode initializationAlexander Stein1-1/+1
commit 10d510abd096d620b9fda2dd3e0047c5efc4ad2b upstream. The default mode, configurable by DT, shall be set before usb role switch driver is registered. Otherwise there is a race between default mode and mode set by usb role switch driver. Fixes: 98ed256a4dbad ("usb: dwc3: Add support for role-switch-default-mode binding") Cc: stable <stable@kernel.org> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Link: https://lore.kernel.org/r/20231025095110.2405281-1-alexander.stein@ew.tq-group.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03USB: dwc2: write HCINT with INTMASK appliedOliver Neukum1-8/+7
commit 0583bc776ca5b5a3f5752869fc31cf7322df2b35 upstream. dwc2_hc_n_intr() writes back INTMASK as read but evaluates it with intmask applied. In stress testing this causes spurious interrupts like this: [Mon Aug 14 10:51:07 2023] dwc2 3f980000.usb: dwc2_hc_chhltd_intr_dma: Channel 7 - ChHltd set, but reason is unknown [Mon Aug 14 10:51:07 2023] dwc2 3f980000.usb: hcint 0x00000002, intsts 0x04600001 [Mon Aug 14 10:51:08 2023] dwc2 3f980000.usb: dwc2_hc_chhltd_intr_dma: Channel 0 - ChHltd set, but reason is unknown [Mon Aug 14 10:51:08 2023] dwc2 3f980000.usb: hcint 0x00000002, intsts 0x04600001 [Mon Aug 14 10:51:08 2023] dwc2 3f980000.usb: dwc2_hc_chhltd_intr_dma: Channel 4 - ChHltd set, but reason is unknown [Mon Aug 14 10:51:08 2023] dwc2 3f980000.usb: hcint 0x00000002, intsts 0x04600001 [Mon Aug 14 10:51:08 2023] dwc2 3f980000.usb: dwc2_update_urb_state_abn(): trimming xfer length Applying INTMASK prevents this. The issue exists in all versions of the driver. Signed-off-by: Oliver Neukum <oneukum@suse.com> Tested-by: Ivan Ivanov <ivan.ivanov@suse.com> Tested-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/20231115144514.15248-1-oneukum@suse.com Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03usb: typec: tcpm: Skip hard reset when in error recoveryBadhri Jagan Sridharan1-0/+9
commit a6fe37f428c19dd164c2111157d4a1029bd853aa upstream. Hard reset queued prior to error recovery (or) received during error recovery will make TCPM to prematurely exit error recovery sequence. Ignore hard resets received during error recovery (or) port reset sequence. ``` [46505.459688] state change SNK_READY -> ERROR_RECOVERY [rev3 NONE_AMS] [46505.459706] state change ERROR_RECOVERY -> PORT_RESET [rev3 NONE_AMS] [46505.460433] disable vbus discharge ret:0 [46505.461226] Setting usb_comm capable false [46505.467244] Setting voltage/current limit 0 mV 0 mA [46505.467262] polarity 0 [46505.470695] Requesting mux state 0, usb-role 0, orientation 0 [46505.475621] cc:=0 [46505.476012] pending state change PORT_RESET -> PORT_RESET_WAIT_OFF @ 100 ms [rev3 NONE_AMS] [46505.476020] Received hard reset [46505.476024] state change PORT_RESET -> HARD_RESET_START [rev3 HARD_RESET] ``` Cc: stable@vger.kernel.org Fixes: f0690a25a140 ("staging: typec: USB Type-C Port Manager (tcpm)") Signed-off-by: Badhri Jagan Sridharan <badhri@google.com> Acked-by: Heikki Krogeus <heikki.krogerus@linux.intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20231101021909.2962679-1-badhri@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-12-03USB: serial: option: don't claim interface 4 for ZTE MF290Lech Perczak1-1/+2
commit 8771127e25d6c20d458ad27cf32f7fcfc1755e05 upstream. Interface 4 is used by for QMI interface in stock firmware of MF28D, the router which uses MF290 modem. Free the interface up, to rebind it to qmi_wwan driver. The proper configuration is: Interface mapping is: 0: QCDM, 1: (unknown), 2: AT (PCUI), 2: AT (Modem), 4: QMI T: Bus=01 Lev=02 Prnt=02 Port=00 Cnt=01 Dev#= 4 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=19d2 ProdID=0189 Rev= 0.00 S: Manufacturer=ZTE, Incorporated S: Product=ZTE LTE Technologies MSM C:* #Ifs= 5 Cfg#= 1 Atr=e0 MxPwr=500mA I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=4ms I:* If#= 1 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=4ms I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=4ms I:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option E: Ad=84(I) Atr=03(Int.) MxPS= 64 Ivl=2ms E: Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=4ms I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan E: Ad=86(I) Atr=03(Int.) MxPS= 64 Ivl=2ms E: Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=4ms Cc: Bjørn Mork <bjorn@mork.no> Signed-off-by: Lech Perczak <lech.perczak@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-16 22:22:36 +0300