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2023-10-19Merge branch 'dev/update_qspi_flash' into 'starfive-6.1-dubhe'REL_DUBHE_SEPT2023starfive-6.1-dubheleyfoon.tan1-5/+22
riscv: dts: starfive: dubhe: Increase QSPI rootfs flash size See merge request starfive-tech/linux!196
2023-10-19riscv: dts: starfive: dubhe: Update QSPI partitionJi Sheng Teoh1-5/+22
This patch updates QSPI partition to allow MTD util to update the content inside the QSPI flash. The QSPI partition are arranged as follow: QSPI Flash content | Start Addr | End Addr | Size | -------------------------------------------------------- Boot Copier(RO) | 0x00000000 | 0x00000fff | 4KB | Boot Jump Code(RO) | 0x00001000 | 0x00001fff | 4KB | U-Boot SPL | 0x00002000 | 0x00041fff | 256KB | U-Boot FIT Image | 0x00042000 | 0x00141fff | 1MB | Linux + Rootfs | 0x00142000 | 0x07ffffff | 126MB | Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2023-09-26Merge branch 'starfive-6.1-dubhe-kvmtool-networking' into 'starfive-6.1-dubhe'leyfoon.tan1-0/+2
riscv: configs: dubhe: Enable bridge networking and TUN/TAP driver See merge request starfive-tech/linux!187
2023-09-23riscv: configs: dubhe: Enable bridge networking and TUN/TAP driverTan En De1-0/+2
So that we can create virtual network consisting of bridge and TAP interface attached to the bridge as a port. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-08-30riscv: dts: starfive: dubhe: Add Dubhe 80 supportLey Foon Tan3-1/+36
Add Dubhe 80 DT support. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-08-30riscv: dts: starfive: dubhe: Move fpga common to *common.dtsiLey Foon Tan2-109/+112
Move Dubhe FPGA common DT to *common.dtsi file, in preparation for Dubhe 80. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-08-30riscv: dts: starfive: dubhe: Update Dubhe90 cpu DT nodeLey Foon Tan2-8/+12
- Add cpu0 and cpu1 label - Update D cache and I cache settings - Update "riscv,isa", remove unused 'n'. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-08-30riscv: dts: starfive: dubhe: Restructure Dubhe device treeLey Foon Tan5-21/+33
Restructure the Dubhe device tree in preparation for Dubhe 80 support. Rename existing Dubhe to Dubhe 90. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-08-17Merge branch 'starfive-6.1-dubhe-perf-sscofpmf' into 'starfive-6.1-dubhe'leyfoon.tan1-2/+4
riscv: dts: starfive: Enable sscofpmf extension support See merge request starfive-tech/linux!170
2023-08-16riscv: dts: starfive: Enable sscofpmf extension supportGenevieve Chan1-2/+4
Add sscofpmf extension support and interrupt register. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-08-07riscv: kvm: Fix compilation warning for unused kvm_riscv_vcpu_update_config()Ley Foon Tan1-0/+2
Commit 338a93e3aea9 ("arch: riscv: kvm: Temporarily comment out henvcfg-related code") has commented out calling to kvm_riscv_vcpu_update_config() function. So, comment out kvm_riscv_vcpu_update_config() function to resolve unused function warning. arch/riscv/kvm/vcpu.c:807:13: warning: 'kvm_riscv_vcpu_update_config' defined but not used [-Wunused-function] 807 | static void kvm_riscv_vcpu_update_config(const unsigned long *isa) | Fixes: 338a93e3aea9 ("arch: riscv: kvm: Temporarily comment out henvcfg-related code") Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-08-04riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=ySamuel Holland2-18/+10
[ upstream commit 0b1d60d6dd9e2e867cc6e4277d73ea5a7ff2d4d0 ] commit 8eb060e10185 ("arch/riscv: add Zihintpause support") broke building with CONFIG_CC_OPTIMIZE_FOR_SIZE enabled (gcc 11.1.0): CC arch/riscv/kernel/vdso/vgettimeofday.o In file included from <command-line>: ./arch/riscv/include/asm/jump_label.h: In function 'cpu_relax': ././include/linux/compiler_types.h:285:33: warning: 'asm' operand 0 probably does not match constraints 285 | #define asm_volatile_goto(x...) asm goto(x) | ^~~ ./arch/riscv/include/asm/jump_label.h:41:9: note: in expansion of macro 'asm_volatile_goto' 41 | asm_volatile_goto( | ^~~~~~~~~~~~~~~~~ ././include/linux/compiler_types.h:285:33: error: impossible constraint in 'asm' 285 | #define asm_volatile_goto(x...) asm goto(x) | ^~~ ./arch/riscv/include/asm/jump_label.h:41:9: note: in expansion of macro 'asm_volatile_goto' 41 | asm_volatile_goto( | ^~~~~~~~~~~~~~~~~ make[1]: *** [scripts/Makefile.build:249: arch/riscv/kernel/vdso/vgettimeofday.o] Error 1 make: *** [arch/riscv/Makefile:128: vdso_prepare] Error 2 Having a static branch in cpu_relax() is problematic because that function is widely inlined, including in some quite complex functions like in the VDSO. A quick measurement shows this static branch is responsible by itself for around 40% of the jump table. Drop the static branch, which ends up being the same number of instructions anyway. If Zihintpause is supported, we trade the nop from the static branch for a div. If Zihintpause is unsupported, we trade the jump from the static branch for (what gets interpreted as) a nop. Fixes: 8eb060e10185 ("arch/riscv: add Zihintpause support") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-08-04Merge branch 'starfive-6.1-dubhe-emu' into 'starfive-6.1-dubhe'leyfoon.tan1-0/+3
riscv: configs: dubhe: Add SBI console support See merge request starfive-tech/linux!159
2023-08-04riscv: configs: dubhe: Add SBI console supportEnDe Tan1-0/+3
2023-07-04Merge branch 'starfive-6.1-dubhe-q2' into 'starfive-6.1-dubhe'leyfoon.tan10-878/+198
perf vendor events riscv: Update JSON metrics for StarFive Dubhe Perf See merge request starfive-tech/linux!134
2023-07-04riscv: dts: starfive: dubhe: Update PMU event mappingGenevieve Chan1-52/+26
Change PMU event mapping based on updated Dubhe Q2 2023 release Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-07-04perf vendor events riscv: Update JSON metrics for StarFive Dubhe PerfGenevieve Chan9-826/+172
Add common perf event support for StarFive Dubhe. Remove unsupported events for StarFive Dubhe. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-06-26Merge branch 'starfive-6.1-dubhe-q2' into 'starfive-6.1-dubhe'leyfoon.tan3-26/+40
riscv: invalidate cache when DMA_BIDIRECTIONAL case in arch_sync_dma_for_cpu() See merge request starfive-tech/linux!130
2023-06-26page_pool: fix inconsistency for page_pool_ring_[un]lock()Yunsheng Lin2-20/+26
[ Upstream commit 368d3cb406cdd074d1df2ad9ec06d1bfcb664882 ] page_pool_ring_[un]lock() use in_softirq() to decide which spin lock variant to use, and when they are called in the context with in_softirq() being false, spin_lock_bh() is called in page_pool_ring_lock() while spin_unlock() is called in page_pool_ring_unlock(), because spin_lock_bh() has disabled the softirq in page_pool_ring_lock(), which causes inconsistency for spin lock pair calling. This patch fixes it by returning in_softirq state from page_pool_producer_lock(), and use it to decide which spin lock variant to use in page_pool_producer_unlock(). As pool->ring has both producer and consumer lock, so rename it to page_pool_producer_[un]lock() to reflect the actual usage. Also move them to page_pool.c as they are only used there, and remove the 'inline' as the compiler may have better idea to do inlining or not. Fixes: 7886244736a4 ("net: page_pool: Add bulk support for ptr_ring") Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Link: https://lore.kernel.org/r/20230522031714.5089-1-linyunsheng@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-06-26net: page_pool: use in_softirq() insteadQingfang DENG2-5/+5
[ Upstream commit 542bcea4be866b14b3a5c8e90773329066656c43 ] We use BH context only for synchronization, so we don't care if it's actually serving softirq or not. As a side node, in case of threaded NAPI, in_serving_softirq() will return false because it's in process context with BH off, making page_pool_recycle_in_cache() unreachable. Signed-off-by: Qingfang DENG <qingfang.deng@siflower.com.cn> Tested-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: David S. Miller <davem@davemloft.net>
2023-06-22riscv: Update arch_sync_dma_for_device() functionLey Foon Tan1-1/+11
Handle different DMA directions. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-06-22riscv: invalidate cache when DMA_BIDIRECTIONAL case in arch_sync_dma_for_cpu()Ley Foon Tan1-2/+0
DMA_BIDIRECTIONAL cases also use invalidate. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-05-25Merge branch 'starfive-6.1-dubhe-tftpissue-without-mdio-netlink' into ↵leyfoon.tan4-9/+11
'starfive-6.1-dubhe' Dubhe TFTP Issue Patch Redmine#4834 See merge request starfive-tech/linux!119
2023-05-25net: phy: Fix genphy_config_advert to advertise PAUSE and 10M Full duplex modeGenevieve Chan1-2/+1
This patch ensure that only 10M Full Duplex and PAUSE are enabled for StarFive Dubhe FPGA Platform Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-05-25riscv: dts: dubhe: Add PHY register settings in marvell,reg-init nodeGenevieve Chan1-0/+5
Use marvell,reg-init node in mdio PHY to update the PHY settings for StarFive Dubhe platform. The following settings are enabled: PAUSE+ ADVERTISED SPEED 10MBPS + COPPER MODE+ AUTONEGOTIATION+ Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-05-25Revert "net: phy: marvell: Set autonegotiation to OFF by default upon init"Genevieve Chan1-2/+0
This reverts commit 057202b6b0f0e9265d6e374f959f715bc3232227. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-05-25Revert "net: phylink: Assign link config in phylink_create()"Genevieve Chan1-4/+4
This reverts commit dbe28bc438226acf5b9523bf0a156433470e417d. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-05-19riscv: dts: dubhe: Remove server ip address from bootargsGenevieve Chan1-1/+1
Removes server ip address field from bootargs ip. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-24Merge branch 'starfive-6.1-dubhe' into 'starfive-6.1-dubhe'leyfoon.tan1-3/+3
riscv: dts: starfive: dubhe: Update flash partition patch See merge request starfive-tech/linux!98
2023-03-24riscv: dts: starfive: dubhe: Update flash partition patchYang Lee1-3/+3
This patch includes flash partition changes. Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-03-22Merge branch 'starfive-6.1-dubhe' into 'starfive-6.1-dubhe'leyfoon.tan8-178/+178
perf vendor events riscv: Update JSON array syntax for Starfive Dubhe Perf See merge request starfive-tech/linux!96
2023-03-21perf vendor events riscv: Update JSON array syntax for Starfive Dubhe PerfYang Lee8-178/+178
This patch updates pmu-events json array syntax. Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-03-20riscv: configs: Dubhe: Enable virtualization and kvmTan En De1-0/+2
These two configs are needed to run KVM guest. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-03-20riscv: dts: dubhe: Disable vectorTan En De1-2/+2
Dubhe doesn't yet support vector extension. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-03-20riscv: asid: Fixup stale TLB entry cause application crashGuo Ren1-10/+20
[ Upstream commit 82dd33fde0268cc622d3d1ac64971f3f61634142 ] After use_asid_allocator is enabled, the userspace application will crash by stale TLB entries. Because only using cpumask_clear_cpu without local_flush_tlb_all couldn't guarantee CPU's TLB entries were fresh. Then set_mm_asid would cause the user space application to get a stale value by stale TLB entry, but set_mm_noasid is okay. Here is the symptom of the bug: unhandled signal 11 code 0x1 (coredump) 0x0000003fd6d22524 <+4>: auipc s0,0x70 0x0000003fd6d22528 <+8>: ld s0,-148(s0) # 0x3fd6d92490 => 0x0000003fd6d2252c <+12>: ld a5,0(s0) (gdb) i r s0 s0 0x8082ed1cc3198b21 0x8082ed1cc3198b21 (gdb) x /2x 0x3fd6d92490 0x3fd6d92490: 0xd80ac8a8 0x0000003f The core dump file shows that register s0 is wrong, but the value in memory is correct. Because 'ld s0, -148(s0)' used a stale mapping entry in TLB and got a wrong result from an incorrect physical address. When the task ran on CPU0, which loaded/speculative-loaded the value of address(0x3fd6d92490), then the first version of the mapping entry was PTWed into CPU0's TLB. When the task switched from CPU0 to CPU1 (No local_tlb_flush_all here by asid), it happened to write a value on the address (0x3fd6d92490). It caused do_page_fault -> wp_page_copy -> ptep_clear_flush -> ptep_get_and_clear & flush_tlb_page. The flush_tlb_page used mm_cpumask(mm) to determine which CPUs need TLB flush, but CPU0 had cleared the CPU0's mm_cpumask in the previous switch_mm. So we only flushed the CPU1 TLB and set the second version mapping of the PTE. When the task switched from CPU1 to CPU0 again, CPU0 still used a stale TLB mapping entry which contained a wrong target physical address. It raised a bug when the task happened to read that value. CPU0 CPU1 - switch 'task' in - read addr (Fill stale mapping entry into TLB) - switch 'task' out (no tlb_flush) - switch 'task' in (no tlb_flush) - write addr cause pagefault do_page_fault() (change to new addr mapping) wp_page_copy() ptep_clear_flush() ptep_get_and_clear() & flush_tlb_page() write new value into addr - switch 'task' out (no tlb_flush) - switch 'task' in (no tlb_flush) - read addr again (Use stale mapping entry in TLB) get wrong value from old phyical addr, BUG! The solution is to keep all CPUs' footmarks of cpumask(mm) in switch_mm, which could guarantee to invalidate all stale TLB entries during TLB flush. Fixes: 65d4b9c53017 ("RISC-V: Implement ASID allocator") Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Zong Li <zong.li@sifive.com> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Cc: Anup Patel <apatel@ventanamicro.com> Cc: Palmer Dabbelt <palmer@rivosinc.com> Cc: stable@vger.kernel.org Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20230226150137.1919750-3-geomatsi@gmail.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-20Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich4-41/+17
[ Upstream commit e921050022f1f12d5029d1487a7dfc46cde15523 ] This reverts the remaining bits of commit 4bd1d80efb5a ("riscv: mm: notify remote harts harts about mmu cache updates"). According to bug reports, suggested approach to fix stale TLB entries is not sufficient. It needs to be replaced by a more robust solution. Fixes: 4bd1d80efb5a ("riscv: mm: notify remote harts about mmu cache updates") Reported-by: Zong Li <zong.li@sifive.com> Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Cc: stable@vger.kernel.org Reviewed-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20230226150137.1919750-2-geomatsi@gmail.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-20random: Cater for low CONFIG_HZ when evaluating cycle counter for jitter ↵Tan En De1-1/+1
entropy generation MAX_SAMPLES_PER_BIT is defined as HZ / 15. However, because of the use of integer division, when HZ < 15, MAX_SAMPLES_BIT_PER_BIT becomes 0. On Linux with CONFIG_HZ < 15, this causes kernel to always assume cycle counter is not suitable for generating jitter entropy. Empirically, this assumption is not true on Dubhe FPGA with CONFIG_HZ_10, because regardless of the low CONFIG_HZ, Dubhe’s cycle counter is still able to produce entropy very fast, such that stack.samples_per_bit = 1. Thus, this commit uses round-up when computing MAX_SAMPLES_PER_BIT: MAX_SAMPLES_PER_BIT = DIV_ROUND_UP(HZ, 15) instead of simply HZ / 15. This way, on Dubhe FPGA with CONFIG_HZ_10, we get MAX_SAMPLES_PER_BIT = 1, and the speed check in try_to_generate_entropy() will pass, which then allows the use of cycle counter to generate jitter entropy. With this commit, Dubhe is now able to reach “crng init done” quickly whenever entropy is needed by a program during boot (ssh-keygen used by Buildroot's sshd). Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-03-20riscv: starfive: Add DMA non-coherent support in StarFive DubheGenevieve Chan2-0/+2
This patch adds the dma non-coherent node in device tree. Sets noncoherent_supported to true for CONFIG_SOC_STARFIVE_DUBHE Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-20riscv: configs: dubhe: Add configs for mtdYang Lee1-3/+14
This patch includes mtd configs Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-03-20riscv: dts: starfive: dubhe: Add flash partition patchYang Lee1-0/+25
This patch includes flash partition changes. Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-03-20arch: riscv: kvm: Temporarily comment out henvcfg-related codeTan En De1-1/+2
Comment out kvm_riscv_vcpu_update_config since it touches currently non-existent henvcfg CSR on Dubhe, because Dubhe is still using hypervisor ISA v0.6.1. Uncommenting is needed once Dubhe is upgraded with hypervisor ISA v1.0. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-03-20riscv: configs: Dubhe: Add ext4 filesystem configTan En De1-0/+1
Needed to use ext4 filesystem. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-03-20net: phylink: Assign link config in phylink_create()Genevieve Chan1-4/+4
This patch parse the following config to a struct phylink: * speed = 10Mbps * duplex = full * pause = RX on, TX on Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-20riscv: dts: dubhe: Set ip in boot args and enable gmacGenevieve Chan1-1/+2
Set ip at kernel bootargs with the following parameters: * Client IP Address: autoconfg using DHCP * Server IP Address: not defined * Gateway IP Address: 192.168.152.1 * Netmask: 255.255.255.0 * Network device to use: eth0 * Autoconfiguration: dhcp Enable gmac driver. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-20net: phy: marvell: Set autonegotiation to OFF by default upon initGenevieve Chan1-0/+2
This patch set AUTONEG_DISABLE during init to disable autonegotiation by default. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-20riscv: configs: Dubhe: Add configs for initramfs sourceGenevieve Chan1-0/+2
The Dubhe ace_20221130 bitfile does not support GMAC. This patch re-enabled booting kernel through initramfs source "rootfs.cpio" Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-20riscv: dts: dubhe: Disable GMAC and remove NFSGenevieve Chan1-2/+1
The ace_20221130 version does not have GMAC support. Disable GMAC driver and remove NFS in the bootargs. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-20riscv: dts: dubhe: Enable NFSGenevieve Chan1-1/+1
This patch adds NFS configuration in the bootargs. The bootargs for NFS is set with the following parameters: * Client IP Address: 192.168.152.100 * Server IP Address: 192.168.153.221 * Gateway IP Address: 192.168.152.1 * Netmask: 255.255.255.0 * Network device to use: eth0 * Autoconfiguration: off * NFS root dir: /home/nfsroot Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-03-20riscv: dts: dubhe: Fix ethernet max-speed to 10Mb/sLey Foon Tan1-0/+11
Fix ethernet max-speed to 10Mb/s for FPGA. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-03-20net: Revert: "net: stmmac: use GFP_DMA32"Ley Foon Tan1-2/+2
This reverts commit 4a75f8889870a8b461c4f0afb6588a3729017490. GMAC supports 64-bit DMA addressing in Dubhe, revert this commit. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-04 01:32:46 +0300