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Dubhe Jan 2023 release MR
See merge request starfive-tech/linux!85
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[ Upstream commit cc3d2b5fc0d6f8ad8a52da5ea679e5c2ec2adbd4 ]
Currently, pause frame register GMAC_RX_FLOW_CTRL_RFE is not updated
correctly when 'ethtool -A <IFACE> autoneg off rx off tx off' command
is issued. This fix ensures the flow control change is reflected directly
in the GMAC_RX_FLOW_CTRL_RFE register.
Fixes: 46f69ded988d ("net: stmmac: Use resolved link config in mac_link_up()")
Cc: <stable@vger.kernel.org> # 5.10.x
Signed-off-by: Goh, Wei Sheng <wei.sheng.goh@intel.com>
Signed-off-by: Noor Azura Ahmad Tarmizi <noor.azura.ahmad.tarmizi@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch parse the following config to a struct phylink:
* speed = 10Mbps
* duplex = full
* pause = RX on, TX on
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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Set ip at kernel bootargs with the following parameters:
* Client IP Address: autoconfg using DHCP
* Server IP Address: not defined
* Gateway IP Address: 192.168.152.1
* Netmask: 255.255.255.0
* Network device to use: eth0
* Autoconfiguration: dhcp
Enable gmac driver.
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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net: phy: marvell: Set autonegotiation to OFF by default upon init
See merge request starfive-tech/linux!82
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This patch set AUTONEG_DISABLE during init to disable autonegotiation
by default.
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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[ Upstream commit 4bd1d80efb5af640f99157f39b50fb11326ce641 ]
Current implementation of update_mmu_cache function performs local TLB
flush. It does not take into account ASID information. Besides, it does
not take into account other harts currently running the same mm context
or possible migration of the running context to other harts. Meanwhile
TLB flush is not performed for every context switch if ASID support
is enabled.
Patch [1] proposed to add ASID support to update_mmu_cache to avoid
flushing local TLB entirely. This patch takes into account other
harts currently running the same mm context as well as possible
migration of this context to other harts.
For this purpose the approach from flush_icache_mm is reused. Remote
harts currently running the same mm context are informed via SBI calls
that they need to flush their local TLBs. All the other harts are marked
as needing a deferred TLB flush when this mm context runs on them.
[1] https://lore.kernel.org/linux-riscv/20220821013926.8968-1-tjytimi@163.com/
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Fixes: 65d4b9c53017 ("RISC-V: Implement ASID allocator")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/#t
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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riscv: dts: dubhe: Disable GMAC and remove NFS
See merge request starfive-tech/linux!80
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The Dubhe ace_20221130 bitfile does not support GMAC. This patch
re-enabled booting kernel through initramfs source "rootfs.cpio"
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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The ace_20221130 version does not have GMAC support. Disable GMAC driver
and remove NFS in the bootargs.
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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riscv: configs: Dubhe: Remove vector configs
See merge request starfive-tech/linux!78
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This patch removes the CONFIG_VECTOR=y for dubhe nov 2022 release
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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'starfive-5.15-dubhe'
net: stmmac: Add StarFive dwmac support
See merge request starfive-tech/linux!74
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This patch adds NFS configuration in the bootargs. The bootargs
for NFS is set with the following parameters:
* Client IP Address: 192.168.152.100
* Server IP Address: 192.168.153.221
* Gateway IP Address: 192.168.152.1
* Netmask: 255.255.255.0
* Network device to use: eth0
* Autoconfiguration: off
* NFS root dir: /home/nfsroot
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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Fix ethernet max-speed to 10Mb/s for FPGA.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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[ upstream commit 449b7a15200a15af8affefdd80ac567c40898dce ]
Use the newly introduced mii_bmcr_encode_fixed() for the xpcs driver.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
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[ upstream commit e62dbaff4bc2540393cfc31a7438ed833da7c43c ]
Make use of the newly introduced mii_bmcr_encode_fixed() to get the
BMCR value when setting loopback mode for the 88e1510.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
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[ upstream commit f28a602b285eab953879688f030f53b966a63f50 ]
phylib can make use of the newly introduced mii_bmcr_encode_fixed()
macro, so let's convert it over.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
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[ upstream commit bdb6cfe7512f7a214815a3092f0be50963dcacbc ]
Add a function to encode a fixed speed/duplex to a BMCR value.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
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[ upstream commit 65a9dedc11d615d8f104a48d38b4fa226967b4ed ]
As per Errata Section 5.1, if EEE is intended to be used, some register
writes must be done once after every hardware reset. This patch now adds
the necessary register writes as listed in the Marvell errata.
Without this fix we experience ethernet problems on some of our boards
equipped with a new version of this ethernet PHY (different supplier).
The fix applies to Marvell Alaska 88E1510/88E1518/88E1512/88E1514
Rev. A0.
Signed-off-by: Leszek Polak <lpolak@arri.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Behún <kabel@kernel.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: David S. Miller <davem@davemloft.net>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220516070859.549170-1-sr@denx.de
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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[ upstream commit fe4f57bf7b585dca58f1496c4e2481ecbae1812 ]
It is mandatory for a software to issue a reset upon modifying RGMII
Receive Timing Control and RGMII Transmit Timing Control bit fields of MAC
Specific Control register 2 (page 2, register 21) otherwise the changes
won't be perceived by the PHY (the same is applicable for a lot of other
registers). Not setting the RGMII delays on the platforms that imply it'
being done on the PHY side will consequently cause the traffic loss. We
discovered that the denoted soft-reset is missing in the
m88e1121_config_aneg() method for the case if the RGMII delays are
modified but the MDIx polarity isn't changed or the auto-negotiation is
left enabled, thus causing the traffic loss on our platform with Marvell
Alaska 88E1510 installed. Let's fix that by issuing the soft-reset if the
delays have been actually set in the m88e1121_config_aneg_rgmii_delays()
method.
Cc: stable@vger.kernel.org
Fixes: d6ab93364734 ("net: phy: marvell: Avoid unnecessary soft reset")
Signed-off-by: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20220205203932.26899-1-Pavel.Parkhomenko@baikalelectronics.ru
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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[ upstream commit 020a45aff1190c32b1087cd75b57fbf6bff46ea6 ]
Existing genphy_loopback() is not applicable for Marvell PHY. Besides
configuring bit-6 and bit-13 in Page 0 Register 0 (Copper Control
Register), it is also required to configure same bits in Page 2
Register 21 (MAC Specific Control Register 2) according to speed of
the loopback is operating.
Tested working on Marvell88E1510 PHY for all speeds (1000/100/10Mbps).
FIXME: Based on trial and error test, it seem 1G need to have delay between
soft reset and loopback enablement.
Fixes: 014068dcb5b1 ("net: phy: genphy_loopback: add link speed configuration")
Cc: <stable@vger.kernel.org> # 5.15.x
Signed-off-by: Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This reverts commit 4a75f8889870a8b461c4f0afb6588a3729017490.
GMAC supports 64-bit DMA addressing in Dubhe, revert this commit.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Enable arch_*dma* implementation.
Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
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This patch introduces the support for GMAC drivers to perform flush
and invalidate of L2 Cache:
* sbi_cache_invalidate(): Invalidate L2 cache for data passed from GMAC
to CPU
* sbi_cache_flush(): Flush L2 cache for data passed from CPU to GMAC
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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This patch add configs for StarFive Dubhe GMAC driver
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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This patch adds GMAC device tree node.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Add StarFive dwmac support.
Signed-off-by: Tan Chun Hau <chunhau.tan@starfivetech.com>
Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
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[ upstream commit 5a5294fbe0200d1327f0e089135dad77b45aa2ee ]
These counters were part of the ISA when we froze the uABI, removing
them breaks userspace.
Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/
Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220928131807.30386-1-palmer@rivosinc.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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[ Upstream commit 2618a0dae09ef37728dab89ff60418cbe25ae6bd]
With GCC 12, -Wstringop-overread was warning about an implicit cast from
char[6] to char[8]. However, the extra 2 bytes are always thrown away,
alignment doesn't matter, and the risk of hitting the edge of unallocated
memory has been accepted, so this prototype can just be converted to a
regular char *. Silences:
net/core/dev.c: In function ‘bpf_prog_run_generic_xdp’: net/core/dev.c:4618:21: warning: ‘ether_addr_equal_64bits’ reading 8 bytes from a region of size 6 [-Wstringop-overread]
4618 | orig_host = ether_addr_equal_64bits(eth->h_dest, > skb->dev->dev_addr);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
net/core/dev.c:4618:21: note: referencing argument 1 of type ‘const u8[8]’ {aka ‘const unsigned char[8]’}
net/core/dev.c:4618:21: note: referencing argument 2 of type ‘const u8[8]’ {aka ‘const unsigned char[8]’}
In file included from net/core/dev.c:91: include/linux/etherdevice.h:375:20: note: in a call to function ‘ether_addr_equal_64bits’
375 | static inline bool ether_addr_equal_64bits(const u8 addr1[6+2],
| ^~~~~~~~~~~~~~~~~~~~~~~
Reported-by: Marc Kleine-Budde <mkl@pengutronix.de>
Tested-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/netdev/20220212090811.uuzk6d76agw2vv73@pengutronix.de
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: netdev@vger.kernel.org
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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[ Upstream commit ca831f29f8f25c97182e726429b38c0802200c8f ]
Arthur Marsh reported we would hit the error below when building kernel
with gcc-12:
CC mm/page_alloc.o
mm/page_alloc.c: In function `mem_init_print_info':
mm/page_alloc.c:8173:27: error: comparison between two arrays [-Werror=array-compare]
8173 | if (start <= pos && pos < end && size > adj) \
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In C++20, the comparision between arrays should be warned.
Link: https://lkml.kernel.org/r/20211125130928.32465-1-sxwjean@me.com
Signed-off-by: Xiongwei Song <sxwjean@gmail.com>
Reported-by: Arthur Marsh <arthur.marsh@internode.on.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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[ upstream commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 ]
From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
CC arch/riscv/kernel/vdso/vgettimeofday.o
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
The fix is to specify those extensions explicitely in -march. However as
older binutils version do not support this, we first need to detect
that.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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This reverts commit bbe28549b2be81cf5da4f541f756cea38b721dfb.
Latest version patch series drop this patch.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Dubhe FPGA platform is running at lower frequency, changes to use 10 Hz.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Change 'mult' to 64-bit (u64) to fix overflow warning if using 10 Hz jiffies.
./include/vdso/jiffies.h:9:19: warning: unsigned conversion from 'long int' to 'unsigned int' changes value from '6400000000' to '2105032704' [-Woverflow]
9 | #define TICK_NSEC ((NSEC_PER_SEC+HZ/2)/HZ)
| ^
kernel/time/jiffies.c:38:35: note: in expansion of macro 'TICK_NSEC'
38 | .mult = TICK_NSEC << JIFFIES_SHIFT, /* details above */
| ^~~~~~~~~
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Add 10 Hz support for FPGA system that run on lower frequency.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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'starfive-5.15-dubhe'
Starfive 5.15 dubhe perf report record annotate
See merge request starfive-tech/linux!57
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Include configs for perf annotate
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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commit c5e4d5e99162ba8025d58a3af7ad103f155d2df7 upstream
This patch adds basic arch initialization and instruction associate
support for the riscv64 CPU architecture.
Example output:
$ perf annotate --stdio2
Samples: 122K of event 'task-clock:u', 4000 Hz, Event count (approx.): 30637250000, [percent: local period]
strcmp() /usr/lib64/libc-2.32.so
Percent
Disassembly of section .text:
0000000000069a30 <strcmp>:
__GI_strcmp():
const unsigned char *s2 = (const unsigned char *) p2;
unsigned char c1, c2;
do
{
c1 = (unsigned char) *s1++;
37.30 lbu a5,0(a0)
c2 = (unsigned char) *s2++;
1.23 addi a1,a1,1
c1 = (unsigned char) *s1++;
18.68 addi a0,a0,1
c2 = (unsigned char) *s2++;
1.37 lbu a4,-1(a1)
if (c1 == '\0')
18.71 ↓ beqz a5,18
return c1 - c2;
}
Signed-off-by: William Cohen <wcohen@redhat.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-riscv@lists.infradead.org
Link: http://lore.kernel.org/lkml/20210927005115.610264-1-wcohen@redhat.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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Starfive 5.15 dubhe SV48
See merge request starfive-tech/linux!58
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Upstream commit 26b8f69edda85a7942fa580360690c2d5c74f765
With the arrival of sv48 and its large address space, it would be
cumbersome to statically define the unit size to use to print the different
portions of the virtual memory layout: instead, determine it dynamically.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit 35d33c76d68dfacc330a8eb477b51cc647c5a847
Because of the stack canary feature that reads from the current task
structure the stack canary value, the thread pointer register "tp" must
be set before calling any C function from head.S: by chance, setup_vm
and all the functions that it calls does not seem to be part of the
functions where the canary check is done, but in the following commits,
some functions will.
Fixes: f2c9699f65557a31 ("riscv: Add STACKPROTECTOR supported")
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit 9d19f2b5256ef6cdd4947b48fab4032d0060e916
sv48 was just introduced, so add its virtual memory layout to the
documentation.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit c774de22c430733487f70d755067d9ea55dbe6de
Define precisely the size of the user accessible virtual space size
for sv32/39/48 mmu types and explain why the whole virtual address
space is split into 2 equal chunks between kernel and user space.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit 73c7c8f68e7266bd558227bd9c598cb90b1673cc
Now that the mmu type is determined at runtime using SATP
characteristic, use the global variable pgtable_l4_enabled to output
mmu type of the processor through /proc/cpuinfo instead of relying on
device tree infos.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit e8a62cc26ddf53a3c6ba2a8d33036cf7b84f3923
By adding a new 4th level of page table, give the possibility to 64bit
kernel to address 2^48 bytes of virtual address: in practice, that offers
128TB of virtual address space to userspace and allows up to 64TB of
physical memory.
If the underlying hardware does not support sv48, we will automatically
fallback to a standard 3-level page table by folding the new PUD level into
PGDIR level. In order to detect HW capabilities at runtime, we
use SATP feature that ignores writes with an unsupported mode.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit 60639f74c2f4fcc3ffa2ac0b120eaa874ccc713f
In the following commits, riscv will almost use the generic versions of
pud_alloc_one and pud_free but an additional check is required since those
functions are only relevant when using at least a 4-level page table, which
will be determined at runtime on riscv.
So move the content of those functions into other functions that riscv
can use without duplicating code.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit 3270bfdb9e4a01bb15d018612a6354c1837b5f97
With 4-level page table folding at runtime, we don't know at compile time
the size of the virtual address space so we must set VA_BITS dynamically
so that sparsemem reserves the right amount of memory for struct pages.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Upstream commit 840125a97abc7e676d839adc2743e8f703a156b3
This simply gathers the different pt_ops initialization in functions
where a comment was added to explain why the page table operations must
be changed along the boot process.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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