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2023-01-09input: touchscreen: tinker_ft5406: Enable multipoint functionChanghuang Liang1-1/+1
Enable multipoint function. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2023-01-09input: touchscreen: tinker_ft5406: Delete unused code.Changhuang Liang1-2/+0
Delete unused code avoid warning. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2023-01-09pinctrl: starfive: Move pm ops to pinctrl-starfive-jh7110.cHal Feng3-20/+19
Because different SoCs have their own registers. We want to save all registers in the pm suspend function and restore them in the pm resume function. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-01-07Merge tag 'JH7110_515_SDK_v4.0.0-rc1' into vf2-515-develAndy Hu48-921/+2766
version JH7110_515_SDK_v4.0.0-rc1 for JH7110 EVB board 1. #2828 support linux perf tool 2. #3049 merge hibernation branch to SDK 3. #2708 uboot support vout clk driver 4. #3006 uboot handle OTP return value 5. #2969, #3039 venc jpu fix futex issue
2023-01-07Merge branch 'CR_2828_vf2_perf_support_minda' into 'vf2-515-devel'andy.hu1-0/+1
vf2: config: add perf events config See merge request sbc/linux!53
2023-01-06Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-5.15.y-devel'andy.hu24-71/+702
CR_3049 Add hibernation feature See merge request sdk/linux!658
2023-01-06riscv: starfive: sdio: modify and add sd card configWilliam Qiu8-23/+25
modify and add sd card config, sush as 'max-frequency' 'pinctrl-names'. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-01-06Merge branch 'CR_2828_perf_support_minda' into 'jh7110-5.15.y-devel'andy.hu27-850/+2064
CR_2828 add perf_patch See merge request sdk/linux!641
2023-01-06Hibernation: canfd: Add system PM API for can/canfdWilliam Qiu1-3/+43
Add system PM API for can/canfd. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-01-06riscv: defconfig: Enable GT9xxChanghuang Liang1-0/+1
Enable GT9xx. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2023-01-06riscv: dts: starfive: Add gt9xx touchscreen supportChanghuang Liang2-0/+10
Add gt9xx touchscreen support. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2023-01-06input: touchscreen: Add gt9xx driver supportChanghuang Liang3-0/+1974
Add gt9xx touchscreen driver support in jh7110 platform. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2023-01-05irqchip/irq-sifive-plic: Add syscore callbacks for hibernationmason.huo1-2/+91
The priority and enable registers of plic will be reset during hibernation power cycle in poweroff mode, add the syscore callbacks to save/restore those registers. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2023-01-05RISCV: Support pmd_leaf() in the function kernel_page_present()Sia Jee Heng1-0/+2
Update kernel_page_present() function to support pmd_leaf(). Function kernel_page_present() will be invoked when hibernation is started. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
2023-01-05timer-starfive:add pm ops for timerziv.xu2-38/+113
add system pm ops for timer Signed-off-by: ziv.xu <ziv.xu@starfive.com>
2023-01-05rsicv: deconfig: Add hibernation and swap partitionmason.huo1-0/+2
Enable the hibernation feature, and config the default hibernation swap partition by partition label. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2023-01-05riscv: kernel: Support hibernation resume for JH7110Sia Jee Heng7-17/+245
Further expand the support for hibernation resume so that the hibernated image can be restore from the disk. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
2023-01-05riscv: kernel: Expand functionlity of swsusp_arch_suspend for JH7110Sia Jee Heng3-3/+32
Futher expand the functionality of the swsusp_arch_suspend so that the hibernated image can be written to the disk and resume from the hibernated image. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
2023-01-05riscv: kernel: Add support for hibernate/suspend to diskSia Jee Heng5-1/+165
The implementation assumes that exactly the same kernel is booted on the same hardware. We save the build number and date to the swap header so that we guarantee not to resume with a different kernel upon booted up the hibernated image. swsusp_arch_resume() and swsusp_arch_suspend() are coded as dummy functions for now and shall complete in the subsequent patches. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
2023-01-05riscv: deconfig: Enable system suspend and pm testmason.huo1-1/+1
Config the system suspend feature, enable pm test feature. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2023-01-03vf2: config: add perf events configminda.chen1-0/+1
add perf events support in vf2. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03dts: configs: add perf events configminda.chen1-0/+1
add 7110 perf support Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03RISC-V: Added HiFive Unmatched PMU eventsJoão Mário Domingos4-0/+182
This patch contains all the available events for the HiFive Unmatched performance monitoring unit. Depends on patch [3], for the base mapfile.csv file. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
2023-01-03RISC-V: Added generic pmu-events mapfileJoão Mário Domingos2-0/+34
The pmu-events now supports custom events for RISC-V, plus the cycle, time and instret events were defined. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
2023-01-03RISC-V: Support CPUID for risc-v in perfJoão Mário Domingos3-0/+85
This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03RISC-V: Create unique identification for SoC PMUJoão Mário Domingos2-0/+50
The SBI PMU platform driver did not provide any identification for perf events matching. This patch introduces a new sysfs file inside the platform device (soc:pmu/id) for pmu identification. The identification is a 64-bit value generated as: [63-32]: mvendorid; [31]: marchid[MSB]; [30-16]: marchid[15-0]; [15-0]: mimpid[15MSBs]; The CSRs are detailed in the RISC-V privileged spec [1]. The marchid is split in MSB + 15LSBs, due to the MSB being used for open-source architecture identification. [1] https://github.com/riscv/riscv-isa-manual Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
2023-01-03MAINTAINERS: Add entry for RISC-V PMU driversAtish Patra1-0/+9
Add myself and Anup as maintainer for RISC-V PMU drivers. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03Documentation: riscv: Remove the old documentationAtish Patra1-255/+0
The existing pmu documentation describes the limitation of perf infrastructure in RISC-V ISA and limited feature set of perf in RISC-V. However, SBI PMU extension and sscofpmf extension(ISA extension) allows to implement most of the required features of perf. Remove the old documentation which is not accurate anymore. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add sscofpmf extension supportAtish Patra6-6/+230
The sscofpmf extension allows counter overflow and filtering for programmable counters. Enable the perf driver to handle the overflow interrupt. The overflow interrupt is a hart local interrupt. Thus, per cpu overflow interrupts are setup as a child under the root INTC irq domain. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Improve /proc/cpuinfo output for ISA extensionsAtish Patra2-2/+51
Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Parse only the enabled ISA extension and print them in a separate row. Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Do no continue isa string parsing without correct XLENAtish Patra1-0/+5
The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Implement multi-letter ISA extension probing frameworkAtish Patra2-6/+36
Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Extract multi-letter extension names from "riscv, isa"Tsukasa OI1-8/+27
Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> [Improved commit text and comments] Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Minimal parser for "riscv, isa" stringsTsukasa OI1-11/+56
Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: Atish Patra <atishp@rivosinc.com> [Fixed workaround for QEMU] Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Tested-by: Heiko Stuebner <heiko@sntech.de>
2023-01-03RISC-V: Correctly print supported extensionsTsukasa OI1-3/+5
This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add perf platform driver based on SBI PMU extensionAtish Patra6-2/+596
RISC-V SBI specification added a PMU extension that allows to configure start/stop any pmu counter. The RISC-V perf can use most of the generic perf features except interrupt overflow and event filtering based on privilege mode which will be added in future. It also allows to monitor a handful of firmware counters that can provide insights into firmware activity during a performance analysis. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add RISC-V SBI PMU extension definitionsAtish Patra1-0/+96
This patch adds all the definitions defined by the SBI PMU extension. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add a simple platform driver for RISC-V legacy perfAtish Patra4-0/+159
The old RISC-V perf implementation allowed counting of only cycle/instruction counters using perf. Restore that feature by implementing a simple platform driver under a separate config to provide backward compatibility. Any existing software stack will continue to work as it is. However, it provides an easy way out in future where we can remove the legacy driver. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add a perf core library for pmu driversAtish Patra4-0/+398
Implement a perf core library that can support all the essential perf features in future. It can also accommodate any type of PMU implementation in future. Currently, both SBI based perf driver and legacy driver implemented uses the library. Most of the common perf functionalities are kept in this core library wile PMU specific driver can implement PMU specific features. For example, the SBI specific functionality will be implemented in the SBI specific driver. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add CSR encodings for all HPMCOUNTERSAtish Patra1-0/+58
Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are accessible in S-mode. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Remove the current perf implementationAtish Patra4-571/+0
The current perf implementation in RISC-V is not very useful as it can not count any events other than cycle/instructions. Moreover, perf record can not be used or the events can not be started or stopped. Remove the implementation now for a better platform driver in future that will implement most of the missing functionality. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2022-12-30Merge branch 'CR_2861_vf2_ts_515_changhuang.liang' into 'vf2-515-devel'VF2_v2.6.0andy.hu2-0/+7
CR_2861_vf2_ts_515_changhuang.liang riscv: dts: starfive: Add touchscreen node support See merge request sbc/linux!52
2022-12-30riscv: defconfig: Enable touchscreenChanghuang Liang1-0/+2
Enable touchscreen TINKER FT5406 Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2022-12-30riscv: dts: starfive: Add touchscreen node supportChanghuang Liang1-0/+5
Add touchscreen node support. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2022-12-30Merge tag 'JH7110_515_SDK_v3.6.0' into vf2-515-develAndy Hu7-37/+426
version JH7110_515_SDK_v3.6.0 for JH7110 EVB board
2022-12-30Merge branch 'CR_2506_515_usb_wifi_jianlong' into 'vf2-515-devel'andy.hu110-0/+52822
CR_2506_515 net:wireless:Support eswin usb wifi ECR6600U See merge request sbc/linux!45
2022-12-30Merge branch 'CR_2936_MMC_515_william.qiu' into 'vf2-515-devel'andy.hu1-29/+1
CR_2936_515: mmc: starfive: resolving warning logs See merge request sbc/linux!49
2022-12-30configs:starfive:Enable usb wifi ECR6600UJianlong Huang1-0/+2
Enable usb wifi ECR6600U Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-12-30net:wireless:Support eswin usb wifi ECR6600UJianlong Huang109-0/+52820
Add usb wifi ECR6600U driver Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-12-29Merge branch 'CR_2861_ts_515_changhuang.liang' into 'jh7110-5.15.y-devel'andy.hu5-0/+426
CR_2861_ts_515_changhuang.liang input: touchscreen: Add tinker_ft5406 driver support See merge request sdk/linux!654
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-22 19:36:35 +0300