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2022-01-12v4l2: add mipi pipeline suppport and ov13850 sensorchanghuang.liang9-57/+2238
2022-01-06[v4l2][update kernel5.15]david.li5-36/+33
2022-01-05reset: starfive-jh7110: Add isp/vout reset support.samin1-2/+30
Add isp/vout reset support for jh7110. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-01-05reset: starfive-jh7110: use platform_ioremap_iomem_byname.samin1-3/+17
The reset module is scattered in several domains, and each address segment may be located in the module device management. Using devm_platform_get_and_ioremap_resource->devm_ioremap_resource will cause the address of this segment to be occupied by the reset driver, and other modules cannot be used, so use ioremap that can be mapped multiple times instead. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-01-05dt-bingings:reset:jh7110: Add isp/vout reg reset node.samin2-5/+9
Add isp/vout reg reset node for jh7110. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-01-05dt-bingings:reset:jh7110: Add isp/vout domain reset define.samin1-1/+31
isp/vout domain are independent of other CRGS. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-01-05[v4l2] [add vin path]david.li7-161/+108
2021-12-23open pciedavid.li1-1/+0
2021-12-22dt-bingings:reset: Add reset node for vdec&&jpeg.samin1-0/+16
Add reset bindings for the vdec&jpeg. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-12-22dt-bingings:reset: Add Starfive JH7110 reset bindingssamin2-2/+47
Add bindings for the reset controller on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-12-22reset: starfive-jh7110: Add StarFive JH7110 reset driversamin6-0/+457
Add a driver for the StarFive JH7110 reset controller. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-12-20[pwm] Add jh7110 pwm driver code“jenny.zhang”4-0/+337
2021-12-16[can] Add jh7110 can driver code“jenny.zhang”4-0/+1527
2021-12-16[trng] Add jh7110 trng driver code“jenny.zhang”5-0/+571
2021-12-16[alsa] Add jh7110 audio module driver code“jenny.zhang”25-3/+8061
2021-12-15v4l2 add dvp modifydavid.li1-2/+2
2021-12-14[add v4l2 driver && close pcie]david.li33-1/+17084
2021-12-13modified dts file for jh7110 i2cHuan.Feng1-1/+17
2021-12-10modified gpio driver for jh7110Huan.Feng1-3/+7
2021-12-10modified i2c driver for jh7110Huan.Feng2-2/+30
2021-12-10remove IMG-rogue and null-disp and drm_legacyvincent.zhang1-2/+1
Signed-off-by: vincent.zhang <vincent.zhang@starfivetech.com>
2021-12-10add IMG-rogue, DRM, GEM & KMS, enable DRM legacy for default configvincent.zhang1-3/+5
2021-12-10change the IRQ number of GPUvincent.zhang1-1/+1
Signed-off-by: vincent.zhang <vincent.zhang@starfivetech.com>
2021-12-03Merge branch 'jh7110_dev_5.15' of ↵Huan.Feng1-1/+7
http://192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15
2021-12-03modify jh7110 gpio driver irq register functionHuan.Feng1-2/+52
2021-12-03Merge branch 'jh7110_dev_5.15' of ↵ke.zhu1-96/+48
http://192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15
2021-12-03modify jh7110 gpio driverHuan.Feng1-96/+48
2021-12-03PLIC cannot EOI masked interrupts，so Re-enable the interrupt before ↵ke.zhu1-1/+7
completion if it has been masked during the handling and remask it afterwards.
2021-12-01Kconfig/dw-axi-dmac-starfive: selected by SOC_STARFIVEsamin1-1/+1
Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-26clocksource: add starfive hw-timer driverSamin Guo5-0/+521
This driver applies to JH7100|JH7110 Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-26watchdog: add starfive watchdog driverSamin Guo4-0/+794
This driver applies to JH7100|JH7110 Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-26dt-bingings: Add dt-bingings support for StarFive JH7110 Timers.SaminGuo1-0/+10
Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-26dt-bingings: Add dt-bingings support for StarFive JH71xx WatchDogSaminGuo1-0/+11
Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-251.Add plda pcie host controller driver.ke.zhu5-28/+792
2.Add PCIe host controller DT bingdings of starfive JH7110.
2021-11-25spi: support spi-pl022.ke.zhu3-0/+24
2021-11-25Merge branch 'jh7110_dev_5.15' of ↵ke.zhu2-4/+16
http://192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15
2021-11-23dt-bingings: Update dt-bingings for jh7110 jpu/vdec.samin1-4/+9
1) rename jpu/vdec match strings. 2) add axi/apb clock-names define for jpu/vdec. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-23dma: Added DMA misc driver interface for data transfersamin5-0/+546
1)add async_memcpy api kernel space. 2)add dma-misc driver for user space. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-23dma: Added DMA misc driver interface for data transfersamin4-0/+539
1)add async_memcpy api kernel space. 2)add dma-misc driver for user space. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-23dmaengine: dw-axi-dmac: Add support for StarFive ALSA device.samin2-12/+37
Solve the problem of audio DMA transmission and playback failure. Signed-off-by: jenny.zhang <jenny.zhang@starfivetech.com> Signed-off-by: michael.yan <michael.yan@starfivetech.com> Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-23dmaengine: dw-axi-dmac: add burst_trans_len support.samin2-2/+18
Different peripherals may require different burst_trans_len. Some ALSA devices may require BURST_TRANS_LEN_16, but this parameter may not work properly on some peripherals (spi, etc.). This patch will allow BURST_TRANS_LEN to be passed in from DTS. dmas = <&dma hs_nu burst_trans_len> burst_trans_len: <-1> defalut <0> BURST_TRANS_LEN_1 <1> BURST_TRANS_LEN_4 /*defalut value*/ <2> BURST_TRANS_LEN_8 <3> BURST_TRANS_LEN_16 <4> BURST_TRANS_LEN_32 <5> BURST_TRANS_LEN_64 <6> BURST_TRANS_LEN_128 <7> BURST_TRANS_LEN_256 Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-23dmaengine: dw-axi-dmac: Add StarFive JHxxx AxiDMA supportsamin2-1/+20
Add support for StarFive AxiDMA to the .compatible field. The AxiDMA Apb region will be accessible if the compatible string matches the "starfive,axi-dma". Add "starfive_flush_dcache" due to VIC7100 Cache Coherency issues. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-23dmaengine: dw-axi-dmac: Supports channels > 8 or hardware handshakes > 16.samin2-29/+177
1)Different num of chan/hw-handshakes have different register offsets. When the channel > 8, DMA uses DMAC_CHENREG2 instead of DMAC_CHENREG. When the channel > 8 or hw-handshake > 16, DMA uses CHx_CFG2 instead of CHx_CFG. 2)add OSR(Outstanding Request Limit) configuration OSR can greatly improve performance in dma-memcpy. Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-23dt-bingings: Add dt-bingings support for StarFive JH7110 DMA.samin1-1/+18
Signed-off-by: samin <samin.guo@starfivetech.com>
2021-11-19dt-bingings: Adjust the line feed to be more intuitiveSaminGuo1-2/+10
Signed-off-by: SaminGuo <samin.guo@starfivetech.com>
2021-11-19rtc: starfive-rtc: Add RTC support for StarFive JH7110.SaminGuo4-0/+679
1)32.768k-RTC device. 2)sw/hw calibration support; 3)alarm support; 4)5.15 Use "devm_rtc_register_device" instead of "rtc_register_device" Signed-off-by: SaminGuo <samin.guo@starfivetech.com>
2021-11-19dt-bingings: Add dt-bingings support for StarFive JH7110 RTC.SaminGuo2-0/+17
RTC fixed operating frequency is 32.768KHz, refclk for hardware calibration Signed-off-by: SaminGuo <samin.guo@starfivetech.com>
2021-11-19[config]:Update default configyanhong.wang1-0/+2
2021-11-18[board]:Init board config for JH7110yanhong.wang20-1/+2287
2021-11-17Merge branch 'worklym' into jh7110_dev_5.15yanhong.wang73614-0/+31812176
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