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2022-04-25dt-bingings:mailbox: Add clk/rst single.shanlong.li1-0/+4
Add clk/rst single for mailbox. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-25Merge branch 'CR_854_RTC_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu2-30/+65
rtc: starfive: Use stardand clock and reset apis for initialization See merge request sdk/sft-riscvpi-linux-5.10!30
2022-04-25Merge branch 'CR_853_TRNG_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu2-81/+98
Cr 853 trng hal.feng See merge request sdk/sft-riscvpi-linux-5.10!29
2022-04-25Merge branch 'CR_871_PWM_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu3-130/+162
Cr 871 pwm hal.feng See merge request sdk/sft-riscvpi-linux-5.10!28
2022-04-25rtc: starfive: Use stardand clock and reset apis for initializationHal Feng2-30/+65
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-25Merge branch 'CR_786_CAN_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu5-132/+103
Cr 786 can clivia.cai See merge request sdk/sft-riscvpi-linux-5.10!24
2022-04-25Merge branch 'CR_886_I2C_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu2-0/+18
riscv: dts: starfive: Add clock and reset for i2c See merge request sdk/sft-riscvpi-linux-5.10!27
2022-04-25riscv: dts: starfive: Add clock and reset for i2cHal Feng2-0/+18
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24hw_random: starfive-trng: Use stardand clock and reset apis for initializationHal Feng2-11/+48
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24hw_random: starfive-trng: Follow linux coding styleHal Feng1-70/+50
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24Merge branch 'CR_877_Timer_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu5-9/+33
risv:dts:starfive:Add timer clocktree See merge request sdk/sft-riscvpi-linux-5.10!26
2022-04-24pwm: pwm-starfive-ptc: Use standard clock, reset, pinctrl framework for ↵Hal Feng3-13/+47
initialization Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24riscv: dts: starfive: Fix string mismatch problem of ptc (pwm)Hal Feng1-2/+2
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24pwm: pwm-starfive-ptc: Follow linux coding styleHal Feng1-121/+119
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24risv:dts:starfive:Add timer clocktreexingyu.wu5-9/+33
1.Modify the clock tree driver to make timer clock ignore disabled_unused. 2.Add different 'clock-frequency' node in fpga, evb and visionfive dts file. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-04-24Update ipms-can.yamlsamin.guo1-2/+0
2022-04-24Merge branch 'CR_865_GMAC_yanhong.wang' into 'jh7110_fpga_dev_5.15'andy.hu4-26/+192
Cr 865 gmac yanhong.wang See merge request sdk/sft-riscvpi-linux-5.10!23
2022-04-24Merge branch 'CR_872_PCIE_mason.huo' into 'jh7110_fpga_dev_5.15'andy.hu2-31/+167
Cr 872 pcie mason.huo See merge request sdk/sft-riscvpi-linux-5.10!15
2022-04-24Merge branch 'CR_785_PCIE_mason.huo' into 'jh7110_fpga_dev_5.15'andy.hu2-152/+174
Cr 785 pcie mason.huo See merge request sdk/sft-riscvpi-linux-5.10!13
2022-04-24dt-bingings:can:Add syscon register configClivia.Cai1-16/+12
Add the syscon register config for can/canfd dt-bindings. In addition, Redefine some attribute names. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24dt-bingings:can:Modify referenceClivia.Cai2-5/+5
Modify the reference of ipmscanx to canx Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24dt-bindings:net:can:ipms-can: update ipms-can.yaml referencesClivia.Cai1-33/+25
Update CAN/CANFD binding documentation for jh7110 SoC. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24can:ipms_can: Driver code optimizationClivia.Cai1-77/+62
Use the syscon framework to manage the syscon registers. In addition, Use devm_reset_control_array_get_exclusive API to manage a list of reset controllers Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24riscv: dts: jh7110: Fix syscon indentation issuemason.huo1-6/+6
Remove additional tabs of syscon configurations. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Add syscon register configmason.huo2-29/+93
Add the syscon register config when plda hw initializes. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Add pcie clk & rstmason.huo2-3/+75
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Add port1 supportmason.huo1-3/+27
Add configuration to support plda pcie port1. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Optimize plda pcie host drivermason.huo1-149/+147
Fix the hardcoded ATR setting. Fix some kernel coding standard issues. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24net:stmmac:dwc-qos: Add jh7110 supportyanhong.wang1-1/+130
The StarFive JH7110 SoC contains an instance of the Synopsys DWC ethernet QOS IP core.The binding that it uses is slightly different from existing ones because of the integration (clocks, resets, ...). Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-24dt-bingings:gmac:jh7110: add clk and reset signals for gmacyanhong.wang2-7/+62
Gmac uses the Clock and reset framework API. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-24net:stmmac: remove DWMAC_CORE_5_20 hw configyanhong.wang1-18/+0
The version DWMAC_CORE_5_20 and DWMAC_CORE_5_10 would use the same configuration,so remove the DWMAC_CORE_5_20 configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-24Merge branch 'CR_881_DMA_curry.zhang' into 'jh7110_fpga_dev_5.15'andy.hu3-1/+23
[DMA] : Add standard system clock tree & reset API See merge request sdk/sft-riscvpi-linux-5.10!22
2022-04-24Merge branch 'CR_876_BoardTypeDef_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu3-24/+3
Cr 876 board type def xingyu.wu See merge request sdk/sft-riscvpi-linux-5.10!18
2022-04-24Merge branch 'CR_863_UART_yanhong.wang' into 'jh7110_fpga_dev_5.15'andy.hu2-11/+16
dt-bingings:uart:jh7110: add clks and reset signals to uarts See merge request sdk/sft-riscvpi-linux-5.10!21
2022-04-24[DMA] : Add standard system clock tree & reset APIcurry.zhang3-1/+23
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-04-24dt-bingings:uart:jh7110: add clks and reset signals to uartsyanhong.wang2-11/+16
Uart uses the clock and reset framework API. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-22Merge branch 'CR_834_VENC_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu2-10/+22
Cr 834 venc samin.guo See merge request sdk/sft-riscvpi-linux-5.10!20
2022-04-22dt-bingings:clk: remove venc_rootclk fixed clk define.samin1-6/+0
The clktree is ready. The Venc uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-22dt-bingings:venc:jh7110: Add CLK signals to Venc.samin1-4/+22
Venc uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-22Merge branch 'CR_835_JPU_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu2-11/+5
Cr 835 jpu samin.guo See merge request sdk/sft-riscvpi-linux-5.10!14
2022-04-22Merge branch 'CR_884_syscon_mason.huo' into 'jh7110_fpga_dev_5.15'andy.hu1-0/+15
riscv: dts: jh7110: Add syscon support See merge request sdk/sft-riscvpi-linux-5.10!19
2022-04-22riscv: dts: jh7110: Add syscon supportmason.huo1-0/+15
Add 'stg', 'sys', 'aon' system control register support, access these registers through syscon framework. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-21dt-bingings:clk: remove jpu_rootclk fixed clk define.samin1-6/+0
The clktree is ready. The JPU uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-21dt-bingings:jpu:jh7110: Add CLK signals to JPU.samin1-5/+5
Jpu uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-21Merge branch 'CR_866_SDIO_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu1-1/+4
dt-bingings:sd:update jh7110 sd dt-bingings See merge request sdk/sft-riscvpi-linux-5.10!17
2022-04-21Merge branch 'CR_867_eMMC_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu1-1/+5
dt-bingings:emmc:update jh7110 emmc dt-bingings See merge request sdk/sft-riscvpi-linux-5.10!16
2022-04-21Makefile: Add Board Type Definition with MODULExingyu.wu1-0/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-21arch:riscv:modify Kconfig.socsxingyu.wu2-24/+1
Kconfig.socs: remove the definitions like 'STARFIVE_BOARD_FPGA'. drivers:watchdog: change the definition. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-21Makefile: Add Board Type Definitionxingyu.wu1-0/+1
Add some definition about 'HWBOARD_FPGA', 'HWBOARD_EVB' or 'HWBOARD_VISIONFIVE' in kernel. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-20dt-bingings:emmc:update jh7110 emmc dt-bingingsClivia.Cai1-1/+5
Add clock and reset for sdio0 nodes in device tree Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-17 11:07:37 +0300