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2022-05-05Merge branch 'CR_850_TDM_Walker.Chen' into 'jh7110_fpga_dev_5.15'andy.hu4-187/+316
Cr 850 tdm walker.chen See merge request sdk/sft-riscvpi-linux-5.10!43
2022-05-05[Audio: PWMDAC] Add standard system clock tree apicurry.zhang6-90/+174
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-05-05Audio:tdm: Add clock/reset/pinctrl initializationWalkerChenL4-187/+316
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-05-05Merge branch 'CR_878_SBI_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu3-9/+35
spi: Add clock, reset and pinctrl See merge request sdk/sft-riscvpi-linux-5.10!41
2022-05-05Merge branch 'CR_868_USB-HOST_yanhong.wang' into 'jh7110_fpga_dev_5.15'andy.hu5-13/+266
Cr 868 usb host yanhong.wang See merge request sdk/sft-riscvpi-linux-5.10!44
2022-05-05Merge branch 'CR_849_PDM_Walker.Chen' into 'jh7110_fpga_dev_5.15'andy.hu4-132/+267
Cr 849 pdm walker.chen See merge request sdk/sft-riscvpi-linux-5.10!45
2022-05-05Audio pdm: add clock/reset/pinctrl initializationWalker Chen4-132/+267
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-05-05usb:cdns3:cdns3-starfive: Add StarFive wrapper driver for CDNS USB3 controlleryanhong.wang3-0/+236
Add driver to handle StarFive specific wrapper for Cadence USB3 controller present on JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-05-05dt-bingings:usb: Add usb device nodeyanhong.wang2-13/+30
Add usb device node configuration for JH7110 SoC platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-05-05[Audio: SPDIF] Add standard system clock tree APIcurry.zhang3-4/+97
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-05-05spi: Add clock, reset and pinctrlxingyu.wu3-9/+35
driver:spi: Add reset handle. dts:starfive:dtsi: Add clock and reset node. dts:starfive:pinctrl: Modify spi gpio and Add pinctrl. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-05-04[Audio] I2S and WM8960curry.zhang8-25/+432
1) Add standard system clock tree API 2) Modify wm8960 and I2S drivers Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-04-29Merge branch 'CR_833_VDEC_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu2-52/+55
pmu:starfive:jh7110: Fix some errors and standardize variable naming See merge request sdk/sft-riscvpi-linux-5.10!38
2022-04-29pmu:starfive:jh7110: Fix some errors and standardize variable namingsamin2-52/+55
Fixed interrupt enabler logic error, fixed PMU_HARD_EVENT definition error, changed some variable names, for better code style. Note: This is an interim version of the pmu driver that provides the power_domian switch function. It can be used in modules such as VPU/JPU/GPU/ISP/VOUT. /* do not upstram */ Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-28Merge branch 'CR_907_GPU_shanlong.li' into 'jh7110_fpga_dev_5.15'andy.hu586-3/+264833
Cr 907 gpu shanlong.li See merge request sdk/sft-riscvpi-linux-5.10!37
2022-04-28Merge branch 'CR_873_HIFI4_henry.qin' into 'jh7110_fpga_dev_5.15'andy.hu4-0/+33
Cr 873 hifi4 henry.qin See merge request sdk/sft-riscvpi-linux-5.10!31
2022-04-28Merge branch 'CR_845_FPGA-V1.0-VIN_update_changhuang.liang' into ↵andy.hu10-271/+391
'jh7110_fpga_dev_5.15' Cr 845 fpga v1.0 vin update changhuang.liang See merge request sdk/sft-riscvpi-linux-5.10!35
2022-04-28Merge branch 'CR_737_CLOCK_TREE_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu9-188/+582
clk:starfive: Add isp clock tree driver See merge request sdk/sft-riscvpi-linux-5.10!32
2022-04-28driver:GPU: add gpu drivershanlong.li581-0/+264808
add gpu driver use clk/rst api and pmu api Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-28driver:pmu : add turn off mask apishanlong.li2-1/+9
add turn off mask api Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-28Merge branch 'CR_858_SEC_william.qiu' into 'jh7110_fpga_dev_5.15'andy.hu1-0/+1
disable sec drvier See merge request sdk/sft-riscvpi-linux-5.10!36
2022-04-28HIFI4: Add hifi4 clk and rst, del unused code, resolve code reviewhenry.qin4-0/+33
problems, change file access mode. Signed-off-by: henry.qin <henry.qin@starfivetech.com>
2022-04-28crypto:starfive: disable crypto default on fpga.william.qiu1-0/+1
For most fpga bitfile has no crypto, so disable it for better linux boot. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28clk:starfive: Add definition instead of numbersxingyu.wu5-195/+230
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-28clk:starfive: Add isp clock tree driverxingyu.wu6-0/+359
Clock references refer to include/dt-bindings/clock/starfive-jh7110-isp.h Enable the isp clock tree driver in dts file if use it. If the fpga is not connetted with isp board, the isp clock tree must be disabled. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-28driver:GPU: add gpu configshanlong.li2-0/+3
add gpu config Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-28dt-bingings:GPU: add clk/rst singleshanlong.li1-2/+13
add clk/rst single Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-28Merge branch 'CR_846_FPGA-V1.0-VOUT_update_keith.zhao' into ↵andy.hu37-1258/+1716
'jh7110_fpga_dev_5.15' riscv:linux:driver:DC8200 See merge request sdk/sft-riscvpi-linux-5.10!33
2022-04-28Merge branch 'CR_858_SEC_william.qiu' into 'jh7110_fpga_dev_5.15'andy.hu26-80/+9754
Cr 858 sec william.qiu See merge request sdk/sft-riscvpi-linux-5.10!34
2022-04-28crypto:starfive:jh7110: add crypto driver for starfive jh7110 soc.william.qiu15-0/+9198
add crypto driver for starfive jh7110 soc. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28crypto:starfive: Write the security clock tree and reset description filewilliam.qiu1-0/+81
Write the security clock tree and reset description file Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28defconfig: add crypto defconfig support.william.qiu1-0/+3
add defconfig for jh7110 crypto. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28dt-bingings:crypto: add crypto node for jh7110 soc.william.qiu1-0/+34
add support for jh7110 crypto. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28dmaengine:pl080: add support for starfive jh7110 soc sec.william.qiu3-1/+139
dd support for starfive jh7110 soc sec. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28crypto: add patch for 5.15william.qiu6-79/+299
crypto need this patch to work. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28Merge branch 'CR_880_MBX_shanlong.li' into 'jh7110_fpga_dev_5.15'andy.hu6-528/+556
Cr 880 mbx shanlong.li See merge request sdk/sft-riscvpi-linux-5.10!25
2022-04-27v4l2: add isp clk tree supportchanghuang.liang7-236/+97
v4l2: delete isp top clk configure riscv:dts:starfive: vin add isp clk handle Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-04-27riscv:linux:driver:DC8200keith.zhao37-1258/+1716
for DC8200 drm driver,update clk reset pinctrl and syscon api Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
2022-04-26V4L2: clk and reset use bulk getchanghuang.liang4-80/+55
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-04-26v4l2: mipi channel add reset control suppurtchanghuang.liang5-90/+71
2022-04-26v4l2: external modules resource use ioremapchanghuang.liang2-38/+51
2022-04-26v4l2: sc2235 sensor use pinctrl set powerchanghuang.liang3-27/+162
2022-04-26v4l2: add sys clk tree supportchanghuang.liang4-12/+65
2022-04-26v4l2: add reset control supportchanghuang.liang4-18/+113
2022-04-26dts: modify sc2235 namechanghuang.liang1-1/+1
2022-04-26v4l2: add pinctrl supportchanghuang.liang3-3/+12
2022-04-26v4l2: fixed sys_crg ioremap error!changhuang.liang2-6/+5
2022-04-26e24:driver: add e24 drever , use clk/rst api ,syscon spishanlong.li2-0/+3
add e24 drever, use clk/rst api, syscon spi Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-26dt-bingings:e24: add e24 devicetree, use clk/rst/syscon.shanlong.li2-0/+33
add e24 devicetree, use clk/rst/syscon. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-26mailbox:starfive: use clk/rst API.shanlong.li2-528/+516
1) use clk/rst api 2) fix coding style. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-17 03:46:11 +0300