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2024-01-11dt-bindings: power: Add starfive,jh7110-pmuWalker Chen2-0/+62
Add bindings for the Power Management Unit on the StarFive JH7110 SoC. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2024-01-11clk: starfive: jh7110-sys: Modify PLL clocks sourceXingyu Wu2-25/+7
Modify PLL clocks source to be got from dts instead of the fixed factor clocks. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11dt-bindings: clock: jh7110-syscrg: Add PLL clock inputsXingyu Wu1-2/+18
Add PLL clock inputs from PLL clock generator. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11clk: starfive: Add StarFive JH7110 PLL clock driverXingyu Wu5-0/+735
Add driver for the StarFive JH7110 PLL clock controller and they work by reading and setting syscon registers. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11dt-bindings: clock: Add StarFive JH7110 PLL clock generatorXingyu Wu2-0/+52
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11config: add jh7110 defconfig for test minishanlong.li1-0/+212
add jh7110 defconfig for test mini Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2024-01-11pinctrl: starfive: Add StarFive JH7110 aon controller driverJianlong Huang3-0/+190
Add pinctrl driver for StarFive JH7110 SoC aon pinctrl controller. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-01-11pinctrl: starfive: Add StarFive JH7110 sys controller driverJianlong Huang6-1/+1526
Add pinctrl driver for StarFive JH7110 SoC sys pinctrl controller. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-01-11dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrlJianlong Huang2-0/+146
Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-01-11dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrlJianlong Huang3-2/+261
Add pinctrl bindings for StarFive JH7110 SoC sys pinctrl controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-01-11riscv: dts: starfive: Add common DT for JH7100 based boardsCristian Ciocaltea2-152/+162
In preparation for adding initial device tree support for the StarFive VisionFive board, which is similar with BeagleV Starlight, move most of the content from jh7100-beaglev-starlight.dts to a new file, to be shared between the two boards. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11riscv: dts: starfive: Add StarFive VisionFive V1 device treeCristian Ciocaltea1-0/+20
Add initial device tree for the StarFive VisionFive V1 SBC, which is similar with the already supported BeagleV Starlight Beta board, both being based on the StarFive JH7100 SoC. Link: https://github.com/starfive-tech/VisionFive Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device treeEmil Renner Berthing4-1/+246
Add a minimal device tree for StarFive JH7110 VisionFive 2 board which has version A and version B. Support booting and basic clock/reset/pinctrl/uart drivers. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11riscv: dts: starfive: Add StarFive JH7110 pin function definitionsJianlong Huang1-0/+308
Add pin function definitions for StarFive JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11riscv: dts: starfive: Add initial StarFive JH7110 device treeEmil Renner Berthing2-0/+505
Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> [conor: squashed in the removal of the S7's non-existent mmu] Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11dt-bindings: riscv: Add SiFive S7 compatibleHal Feng1-0/+1
Add a new compatible string in cpu.yaml for SiFive S7 CPU core which is used on SiFive U74-MC core complex etc. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11dt-bindings: interrupt-controller: Add StarFive JH7110 plicEmil Renner Berthing1-0/+1
Add compatible string for StarFive JH7110 plic. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11dt-bindings: timer: Add StarFive JH7110 clintEmil Renner Berthing1-0/+1
Add compatible string for the StarFive JH7110 clint. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11clk: starfive: Avoid casting iomem pointersStephen Boyd3-6/+35
Let's use a wrapper struct for the auxiliary_device made in jh7110_reset_controller_register() so that we can stop casting iomem pointers. The casts trip up tools like sparse, and make for some awkward casts that are largely unnecessary. While we're here, change the allocation from devm and actually free the auxiliary_device memory in the release function. This avoids any use after free problems where the parent device driver is unbound from the device but the auxiliuary_device is still in use accessing devm freed memory. Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cc: Hal Feng <hal.feng@starfivetech.com> Cc: Conor Dooley <conor.dooley@microchip.com> Cc: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230413205528.4044216-1-sboyd@kernel.org
2024-01-11MAINTAINERS: generalise StarFive clk/reset entriesshanlong.li1-7/+9
Update the MAINTAINERS entry for StarFive's clock and reset drivers to account for the addition of JH7110 support and Hal's role in that. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2024-01-11reset: starfive: Add StarFive JH7110 reset driverHal Feng3-0/+79
Add auxiliary driver to support StarFive JH7110 system and always-on resets. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11clk: starfive: Add StarFive JH7110 always-on clock driverEmil Renner Berthing3-0/+168
Add driver for the StarFive JH7110 always-on clock controller and register an auxiliary device for always-on reset controller which is named as "rst-aon". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11clk: starfive: Add StarFive JH7110 system clock driverEmil Renner Berthing4-0/+514
Add driver for the StarFive JH7110 system clock controller and register an auxiliary device for system reset controller which is named as "rst-sys". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11reset: starfive: jh71x0: Use 32bit I/O on 32bit registersEmil Renner Berthing3-24/+23
We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11reset: starfive: Rename "jh7100" to "jh71x0" for the common codeEmil Renner Berthing3-27/+27
For the common code will be shared with the StarFive JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11reset: starfive: Extract the common JH71X0 reset codeEmil Renner Berthing3-54/+76
Extract the common JH71X0 reset code for reusing them to support JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11reset: starfive: Factor out common JH71X0 reset codeEmil Renner Berthing5-149/+180
The StarFive JH7100 SoC has additional reset controllers for audio and video, but the registers follow the same structure. On the JH7110 the reset registers don't get their own memory range, but instead follow the clock control registers. The registers still follow the same structure though, so let's factor out the common code to handle all these cases. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11reset: Create subdirectory for StarFive driversEmil Renner Berthing5-8/+12
This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEHal Feng1-2/+2
Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11clk: starfive: Rename "jh7100" to "jh71x0" for the common codeEmil Renner Berthing4-406/+418
Rename some variables from "jh7100" or "JH7100" to "jh71x0" or "JH71X0". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.hEmil Renner Berthing4-3/+3
Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making the code to be common. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11clk: starfive: Factor out common JH7100 and JH7110 codeEmil Renner Berthing5-326/+342
The clock control registers on the StarFive JH7100 and JH7110 work identically, so factor out the code then drivers for the two SoCs can share it without depending on each other. No functional change. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEHal Feng2-4/+4
Using ARCH_FOO symbol is preferred than SOC_FOO. Set obj-y for starfive/ in Makefile, so the StarFive drivers can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generatorEmil Renner Berthing3-0/+137
Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-11dt-bindings: clock: Add StarFive JH7110 system clock and reset generatorEmil Renner Berthing3-0/+449
Add bindings for the system clock and reset generator (SYSCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-16Linux 6.1.46v6.1.46Greg Kroah-Hartman1-1/+1
Link: https://lore.kernel.org/r/20230813211718.757428827@linuxfoundation.org Tested-by: Bagas Sanjaya <bagasdotme@gmail.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: SeongJae Park <sj@kernel.org> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Shuah Khan <skhan@linuxfoundation.org> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Allen Pais <apais@linux.microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16drm/amd/pm/smu7: move variables to where they are usedAlex Deucher1-6/+8
commit 63a9ab264a8c030482ab9e7e20b6c4c162299531 upstream. Move variable declarations to where they are used. Fixes a segfault on smu7 V0 structures where some tables don't exist. Cc: Evan Quan <evan.quan@amd.com> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2388 Fixes: b1a9557a7d00 ("drm/amd/pm: fulfill powerplay peak profiling mode shader/memory clock settings") Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16sch_netem: fix issues in netem_change() vs get_dist_table()Eric Dumazet1-34/+25
commit 11b73313c12403f617b47752db0ab3deef201af7 upstream. In blamed commit, I missed that get_dist_table() was allocating memory using GFP_KERNEL, and acquiring qdisc lock to perform the swap of newly allocated table with current one. In this patch, get_dist_table() is allocating memory and copy user data before we acquire the qdisc lock. Then we perform swap operations while being protected by the lock. Note that after this patch netem_change() no longer can do partial changes. If an error is returned, qdisc conf is left unchanged. Fixes: 2174a08db80d ("sch_netem: acquire qdisc lock in netem_change()") Reported-by: syzbot <syzkaller@googlegroups.com> Signed-off-by: Eric Dumazet <edumazet@google.com> Cc: Stephen Hemminger <stephen@networkplumber.org> Acked-by: Jamal Hadi Salim <jhs@mojatatu.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Link: https://lore.kernel.org/r/20230622181503.2327695-1-edumazet@google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Fedor Pchelkin <pchelkin@ispras.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16alpha: remove __init annotation from exported page_is_ram()Masahiro Yamada1-2/+1
commit 6ccbd7fd474674654019a20177c943359469103a upstream. EXPORT_SYMBOL and __init is a bad combination because the .init.text section is freed up after the initialization. Commit c5a130325f13 ("ACPI/APEI: Add parameter check before error injection") exported page_is_ram(), hence the __init annotation should be removed. This fixes the modpost warning in ARCH=alpha builds: WARNING: modpost: vmlinux: page_is_ram: EXPORT_SYMBOL used for init symbol. Remove __init or EXPORT_SYMBOL. Fixes: c5a130325f13 ("ACPI/APEI: Add parameter check before error injection") Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16ACPI: scan: Create platform device for CS35L56Simon Trimmer2-0/+15
commit 1cd0302be5645420f73090aee26fa787287e1096 upstream. The ACPI device CSC3556 is a Cirrus Logic CS35L56 mono amplifier which is used in multiples, and can be connected either to I2C or SPI. There will be multiple instances under the same Device() node. Add it to ignore_serial_bus_ids and handle it in the serial-multi-instantiate driver. There can be a 5th I2cSerialBusV2, but this is an alias address and doesn't represent a real device. Ignore this by having a dummy 5th entry in the serial-multi-instantiate instance list with the name of a non-existent driver, on the same pattern as done for bsg2150. Signed-off-by: Simon Trimmer <simont@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://lore.kernel.org/r/20230728111345.7224-1-rf@opensource.cirrus.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16platform/x86: serial-multi-instantiate: Auto detect IRQ resource for CSC3551David Xu1-4/+17
commit 676b7c5ecab36274442887ceadd6dee8248a244f upstream. The current code assumes that the CSC3551(multiple cs35l41) always have its interrupt pin connected to GPIO thus the IRQ can be acquired with acpi_dev_gpio_irq_get. However on some newer laptop models this is no longer the case as they have the CSC3551's interrupt pin connected to APIC. This causes smi_i2c_probe to fail on these machines. To support these machines, a new macro IRQ_RESOURCE_AUTO was introduced for cs35l41 smi_node, and smi_get_irq function was modified so it tries to get GPIO irq resource first and if failed, tries to get APIC irq resource for cs35l41. This patch affects only the cs35l41's probing and brings no negative influence on machines that indeed have the cs35l41's interrupt pin connected to GPIO. Signed-off-by: David Xu <xuwd1@hotmail.com> Link: https://lore.kernel.org/r/SY4P282MB18350CD8288687B87FFD2243E037A@SY4P282MB1835.AUSP282.PROD.OUTLOOK.COM Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: qedf: Fix firmware halt over suspend and resumeNilesh Javali1-0/+18
commit ef222f551e7c4e2008fc442ffc9edcd1a7fd8f63 upstream. While performing certain power-off sequences, PCI drivers are called to suspend and resume their underlying devices through PCI PM (power management) interface. However the hardware does not support PCI PM suspend/resume operations so system wide suspend/resume leads to bad MFW (management firmware) state which causes various follow-up errors in driver when communicating with the device/firmware. To fix this driver implements PCI PM suspend handler to indicate unsupported operation to the PCI subsystem explicitly, thus avoiding system to go into suspended/standby mode. Fixes: 61d8658b4a43 ("scsi: qedf: Add QLogic FastLinQ offload FCoE driver framework.") Signed-off-by: Saurav Kashyap <skashyap@marvell.com> Signed-off-by: Nilesh Javali <njavali@marvell.com> Link: https://lore.kernel.org/r/20230807093725.46829-1-njavali@marvell.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: qedi: Fix firmware halt over suspend and resumeNilesh Javali1-0/+18
commit 1516ee035df32115197cd93ae3619dba7b020986 upstream. While performing certain power-off sequences, PCI drivers are called to suspend and resume their underlying devices through PCI PM (power management) interface. However the hardware does not support PCI PM suspend/resume operations so system wide suspend/resume leads to bad MFW (management firmware) state which causes various follow-up errors in driver when communicating with the device/firmware. To fix this driver implements PCI PM suspend handler to indicate unsupported operation to the PCI subsystem explicitly, thus avoiding system to go into suspended/standby mode. Fixes: ace7f46ba5fd ("scsi: qedi: Add QLogic FastLinQ offload iSCSI driver framework.") Signed-off-by: Nilesh Javali <njavali@marvell.com> Link: https://lore.kernel.org/r/20230807093725.46829-2-njavali@marvell.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: fnic: Replace return codes in fnic_clean_pending_aborts()Karan Tilak Kumar2-3/+5
commit 5a43b07a87835660f91d88a4db11abfea8c523b7 upstream. fnic_clean_pending_aborts() was returning a non-zero value irrespective of failure or success. This caused the caller of this function to assume that the device reset had failed, even though it would succeed in most cases. As a consequence, a successful device reset would escalate to host reset. Reviewed-by: Sesidhar Baddela <sebaddel@cisco.com> Tested-by: Karan Tilak Kumar <kartilak@cisco.com> Signed-off-by: Karan Tilak Kumar <kartilak@cisco.com> Link: https://lore.kernel.org/r/20230727193919.2519-1-kartilak@cisco.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: core: Fix possible memory leak if device_add() failsZhu Wang1-0/+1
commit 04b5b5cb0136ce970333a9c6cec7e46adba1ea3a upstream. If device_add() returns error, the name allocated by dev_set_name() needs be freed. As the comment of device_add() says, put_device() should be used to decrease the reference count in the error path. So fix this by calling put_device(), then the name can be freed in kobject_cleanp(). Fixes: ee959b00c335 ("SCSI: convert struct class_device to struct device") Signed-off-by: Zhu Wang <wangzhu9@huawei.com> Link: https://lore.kernel.org/r/20230803020230.226903-1-wangzhu9@huawei.com Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: snic: Fix possible memory leak if device_add() failsZhu Wang1-0/+1
commit 41320b18a0e0dfb236dba4edb9be12dba1878156 upstream. If device_add() returns error, the name allocated by dev_set_name() needs be freed. As the comment of device_add() says, put_device() should be used to give up the reference in the error path. So fix this by calling put_device(), then the name can be freed in kobject_cleanp(). Fixes: c8806b6c9e82 ("snic: driver for Cisco SCSI HBA") Signed-off-by: Zhu Wang <wangzhu9@huawei.com> Acked-by: Narsimhulu Musini <nmusini@cisco.com> Link: https://lore.kernel.org/r/20230801111421.63651-1-wangzhu9@huawei.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: 53c700: Check that command slot is not NULLAlexandra Diupina1-1/+1
commit 8366d1f1249a0d0bba41d0bd1298d63e5d34c7f7 upstream. Add a check for the command slot value to avoid dereferencing a NULL pointer. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Co-developed-by: Vladimir Telezhnikov <vtelezhnikov@astralinux.ru> Signed-off-by: Vladimir Telezhnikov <vtelezhnikov@astralinux.ru> Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru> Link: https://lore.kernel.org/r/20230728123521.18293-1-adiupina@astralinux.ru Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: ufs: renesas: Fix private allocationYoshihiro Shimoda1-1/+1
commit b6d128f89a85771433a004e8656090ccbe1fb969 upstream. Should use devm_kzalloc() for struct ufs_renesas_priv because the .initialized should be false as default. Fixes: d69520288efd ("scsi: ufs: ufs-renesas: Add support for Renesas R-Car UFS controller") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20230803081812.1446282-1-yoshihiro.shimoda.uh@renesas.com Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: storvsc: Fix handling of virtual Fibre Channel timeoutsMichael Kelley1-4/+0
commit 175544ad48cbf56affeef2a679c6a4d4fb1e2881 upstream. Hyper-V provides the ability to connect Fibre Channel LUNs to the host system and present them in a guest VM as a SCSI device. I/O to the vFC device is handled by the storvsc driver. The storvsc driver includes a partial integration with the FC transport implemented in the generic portion of the Linux SCSI subsystem so that FC attributes can be displayed in /sys. However, the partial integration means that some aspects of vFC don't work properly. Unfortunately, a full and correct integration isn't practical because of limitations in what Hyper-V provides to the guest. In particular, in the context of Hyper-V storvsc, the FC transport timeout function fc_eh_timed_out() causes a kernel panic because it can't find the rport and dereferences a NULL pointer. The original patch that added the call from storvsc_eh_timed_out() to fc_eh_timed_out() is faulty in this regard. In many cases a timeout is due to a transient condition, so the situation can be improved by just continuing to wait like with other I/O requests issued by storvsc, and avoiding the guaranteed panic. For a permanent failure, continuing to wait may result in a hung thread instead of a panic, which again may be better. So fix the panic by removing the storvsc call to fc_eh_timed_out(). This allows storvsc to keep waiting for a response. The change has been tested by users who experienced a panic in fc_eh_timed_out() due to transient timeouts, and it solves their problem. In the future we may want to deprecate the vFC functionality in storvsc since it can't be fully fixed. But it has current users for whom it is working well enough, so it should probably stay for a while longer. Fixes: 3930d7309807 ("scsi: storvsc: use default I/O timeout handler for FC devices") Cc: stable@vger.kernel.org Signed-off-by: Michael Kelley <mikelley@microsoft.com> Link: https://lore.kernel.org/r/1690606764-79669-1-git-send-email-mikelley@microsoft.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-16scsi: core: Fix legacy /proc parsing buffer overflowTony Battersby1-13/+17
commit 9426d3cef5000824e5f24f80ed5f42fb935f2488 upstream. (lightly modified commit message mostly by Linus Torvalds) The parsing code for /proc/scsi/scsi is disgusting and broken. We should have just used 'sscanf()' or something simple like that, but the logic may actually predate our kernel sscanf library routine for all I know. It certainly predates both git and BK histories. And we can't change it to be something sane like that now, because the string matching at the start is done case-insensitively, and the separator parsing between numbers isn't done at all, so *any* separator will work, including a possible terminating NUL character. This interface is root-only, and entirely for legacy use, so there is absolutely no point in trying to tighten up the parsing. Because any separator has traditionally worked, it's entirely possible that people have used random characters rather than the suggested space. So don't bother to try to pretty it up, and let's just make a minimal patch that can be back-ported and we can forget about this whole sorry thing for another two decades. Just make it at least not read past the end of the supplied data. Link: https://lore.kernel.org/linux-scsi/b570f5fe-cb7c-863a-6ed9-f6774c219b88@cybernetics.com/ Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Martin K Petersen <martin.petersen@oracle.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Willy Tarreau <w@1wt.eu> Cc: stable@kernel.org Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Tony Battersby <tonyb@cybernetics.com> Signed-off-by: Martin K Petersen <martin.petersen@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>