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2010-09-18drm/i915: use GMBUS to manage i2c linksChris Wilson21-419/+441
Use the GMBUS interface rather than direct bit banging to grab the EDID over DDC (and for other forms of auxiliary communication with external display controllers). The hope is that this method will be much faster and more reliable than bit banging for fetching EDIDs from buggy monitors or through switches, though we still preserve the bit banging as a fallback in case GMBUS fails. Based on an original patch by Jesse Barnes. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915: call drm_encoder_init firstChris Wilson4-12/+18
Later initialisation of the encoder often requires that drm_encoder_init() has already been called, for instance, initialiasing the DDC buses. Yet another recent regression, as 819f3fb7 depended upon these fixes which I missed when cherry-picking. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915/sdvo: Mark the status as unknown if attached with EDIDChris Wilson1-1/+1
One problem with devices that share the DDC bus between the VGA and DVI-I connectors is that with two devices attached we cannot know if there is truly a monitor attached to the DVI connector. In this case, it is preferrrable to mark the status as unknown, so that the user can supply the known set of modes and continue to use the output. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915/sdvo: Only create the analog encoder as requiredChris Wilson1-28/+41
We only need to use the analog encoder for rare devices which share the DDC between the DVI-I and VGA connectors, so only create as needed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15agp/intel: Fix resume regression from 2d2430cfChris Wilson1-4/+10
On i915 [EeePCs] something scribles over the registers during suspend and resume so we must save a copy of the PGETBL_CTL register programmed by the BIOS and restore that upon resume. Reported-by: Sitsofe Wheeler <sitsofe@yahoo.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15agp/intel: Remove redundant setting of gtt_mappable_entriesChris Wilson1-9/+6
Two calls enter, only one will leave. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915/sdvo: Propagate i2c error from switching DDC control bus.Chris Wilson1-9/+18
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915/sdvo: Tidy intel_sdvo_hdmi_sink_detectChris Wilson1-31/+24
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915: Remove unused intel_ringbuffer->ring_flagChris Wilson3-6/+2
This can always be re-added should somebody find a use... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915/i2c: Track the parent encoder rather than just the devChris Wilson7-65/+67
The SDVO proxy i2c adapter wants to be able to use information stored in the encoder, so pass that through intel_i2c rather than iterate over all known encoders every time. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915: Allow get_fence_reg() to be uninterruptibleChris Wilson4-22/+31
As we currently may need to acquire a fence register during a modeset, we need to be able to do so in an uninterruptible manner. So expose that parameter to the callers of the fence management code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-15drm/i915: Push pipelining of display plane flushes to the callerChris Wilson5-29/+43
This ensures that we do wait upon the flushes to complete if necessary and avoid the visual tears, whilst enabling pipelined page-flips. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14agp/intel: Use macro to set the count of the size arrayChris Wilson1-14/+14
It's a fixed size array so let the compiler do the hard work of updating all the call sites. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14drm/i915: Fix regression in ba3d8d749bChris Wilson1-2/+6
I pulled the wrong version of the patch from Daniel Vetter which was missing the read barriers -- and the one that was causing all the trouble was from i915_gem_object_put_fence_reg(), leading to GPU hangs on gen3. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14drm/i915: Consolidate flushing the display planeChris Wilson4-50/+17
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14drm/i915: Reduce hangcheck frequencyChris Wilson3-6/+11
By reducing the hangcheck frequency we check less often, conserving resources, and still detect a lock up quickly. On a fast machine with a slow GPU (like a Core2 paired with a 945G) it is easy for the hangcheck to misfire as we check too fast. Also once hung and if we fail to completely reset the chip, we have a nasty habit of proclaming a hang many times a second and generating a strobe-like display. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13drm/i915: Remove redundant initialisation of crtc->pipeChris Wilson1-4/+2
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13drm/i915: Initialize intel_crtc->activeChris Wilson1-0/+1
Fix a regression in the previous regression fix... In order to turn off the pipes entirely upon the first modeset, we pretend that BIOS (or earlier module incarnation) left them active. The first task performed by setup_initial_configuration() is to disable all pipes and so to avoid skipping that step and so to ensure a known configuration we need to mark all the crtcs as active. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13drm/i915: Fix an overlay regression from 7e7d76cChris Wilson3-6/+21
When separating out the prepare/commit into its own separate functions we overlooked that the intel_crtc->dpms_mode was being used elsewhere to check on the actual status of the pipe. Track that bit of logic separately from the actual dpms mode, so there is no confusion should we be able to handle multiple dpms modes, nor any semantic conflict between prepare/commit and dpms. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13drm/i915: Share crtc setup and teardown between dpms and disable/enableChris Wilson2-81/+46
This closes a couple of corner cases where we introduced and forgot about a couple of routines that need to be called when disabling the crtc and then re-enabling it. The code needs to be moved again so that the common bits are shared across generations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13drm/i915/lvds: Move private data to the connector from the device.Chris Wilson2-79/+78
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13drm/i915/lvds: Remove incorrect mode lockingChris Wilson1-7/+0
One doesn't need to hold the mode lock in order to duplicate a mode. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13drm/i915/lvds: Ensure panel is unlocked for Ironlake or the panel fitterChris Wilson4-63/+105
Commit 77d07fd9d73ef28689737c0952dbd5d6a5017743 introduced a regression where by not waiting for the panel to be turned off, left the panel and PLL registers locked across the modeset. Thus the panel remaining blank. As pointed out by Daniel Vetter, when testing LVDS it helps to open the laptop and look at the actual panel you are purporting to test. A second issue with the patch was that in order to modify the panel fitter before gen5, the pipe and the panel must have be completely powered down. So we wait. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12drm/i915/bios: Prevent NULL dereference after allocation failureChris Wilson1-0/+2
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12drm/i915/sdvo: Poll command status 5 times without delay on readChris Wilson1-35/+36
The documentation says that an SDVO command takes a maximum of 15us to be processed by the device, and that it is sufficient to read the status byte 3 times (whilst the command is still in the PENDING state) for the driver to be confident that sufficient time has elapsed. We err on the safe side and try 5 times before giving up. The only question that remains: was the old behaviour derived by experiments with real hardware? A look into the murky history of UMS, implies that the behaviour was accidental and the current retry mechanism was solely designed to catch the status byte indicating PENDING with no reference to hardware behaviour. (commit ac9181c014638dbeb334b40b4029d0ccb2b7a0fc in xf86-video-intel) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12drm/i915: Use msleep instead of mdelay during wait_vblank_offChris Wilson2-6/+14
Avoid a potentially long busy-wait if we not in the process of atomically switching to the kdb console. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12drm/i915/lvds: Remove busy wait for powering up the panel.Chris Wilson1-5/+1
We just assume that it will happen in a timely manner. A variant of this patch was first written and tested by Arjan van de Van. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12drm/i915/lvds: Remove busy wait for powering down the panelChris Wilson1-9/+2
Just assume that it will turn off... Reported-by: Sitsofe Wheeler <sitsofe@yahoo.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12drm/i915/i2c: The bit-banging interface controls the delay, drop oursChris Wilson1-19/+15
Remove our redundant udelay() as the timings are already handled by the i2c-algo-bit controller. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12drm/i915/dp: Convert a udelay(17000) to a sleep during link-offChris Wilson1-3/+2
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: Use macros to switch between equivalent pipe registersChris Wilson5-546/+507
The purpose is to make the code much easier to read and therefore reduce the possibility for bugs. A side effect is that it also makes it much easier for the compiler, reducing the object size by 4k -- from just a few functions! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: Tidy Ironlake watermark computationChris Wilson2-115/+99
Refactor the common code into seperate functions and use the MIN(large, small) buffer calculation for self-refresh watermarks. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: Fix updating FBCChris Wilson3-68/+90
We need to track different state on each generation in order to detect when we need to refresh the FBC registers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: enable thermal reporting for IPSJesse Barnes2-0/+8
Thermal reporting may not be enabled by default on some machines, so enable the appropriate bits to allow IPS to get the data it needs from the CPU thermal device. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson3-9/+27
2010-09-11drm/i915: Use the real FDI frequency for determining b/wChris Wilson3-1/+20
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: Only call udelay() when waiting for clocks to stabiliseChris Wilson1-3/+1
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: Ensure all PLL registers are flushed before a udelay()Chris Wilson1-0/+5
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: set FDI RX TU size to match transmit sizeJesse Barnes1-0/+6
This allows FDI error checking to work. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: don't write TU size to N1 regJesse Barnes1-1/+1
TU size is only part of the M1 and M2 regs, not the N regs. This keeps us from overwriting a reserved field. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: split Ironlake FDI enable functionJesse Barnes1-27/+45
Easier to read, and will pair up with a disable function. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: enable PCH PLL, FDI training and transcoder even for eDPJesse Barnes1-123/+119
eDP panels require these to be set up prior to panel power sequencing, or they'll fail to power on due to an "asset not ready" check. And of course, eDP panels attached to anything other than DP_A need them enabled regardless, since they'll be driven from the CPU through FDI out to the PCH. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: use i915 and Ironlake CRTC enable/disable functions in prepare/commitJesse Barnes1-9/+60
This will allow us to optimize our prepare/commit paths a bit better. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: minor tweak to handle the cursor across pipe resizing] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: don't unlock panel regsJesse Barnes1-1/+1
This was just a workaround for some broken Ironlake CRTC code. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: split i9xx CRTC enable/disable codeJesse Barnes1-82/+103
So we can use it for CRTC prepare/commit. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11drm/i915: split Ironlake CRTC enable/disable codeJesse Barnes1-281/+310
This way we can also use it in CRTC prepare/commit. Also makes it easier to split out FDI and other code. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10drm/i915: Adapt workqueue to new alloc_workqueue interfaceChris Wilson1-1/+16
create_singlethreaded_workqueue() is being phased out for a new concurrency managed task infrastructure. Adapt our workqueue constructor to explicitly create a domain that only allows the execution of a single task at any time. All the tasks are expected to require the dev->struct_mutex, so would block concurrency of other tasks if we allow more than a single i915 task to be run at once. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10drm/i915: don't enable self-refresh on IronlakeJesse Barnes2-2/+12
We don't know how to enable it safely, especially as outputs turn on and off. When disabling LP1 we also need to make sure LP2 and 3 are already disabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29173 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29082 Reported-by: Chris Lord <chris@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-09drm/i915/debug: Include Ironlake in self-refresh statusChris Wilson1-3/+5
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-09drm/i915: Make the connector->encoder relationship explicitChris Wilson9-127/+130
Currently we have a exact mapping of a connector onto an encoder for its whole lifetime. Make this an explicit property of the structure and so simplify the code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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