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2017-12-21drm/tegra: dc: Link DC1 to DC0 on Tegra20Dmitry Osipenko2-31/+65
Hardware reset isn't actually broken on Tegra20, but there is a dependency on the first display controller to be taken out of reset for the second to be enabled successfully. Model this dependency using a PM device link. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [treding@nvidia.com: minor cleanups, extend commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: Fix non-debugfs buildsArnd Bergmann1-1/+7
The new debugfs registration fails to build when CONFIG_DEBUGFS is disabled, because the drm_crtc structure is lacking a member in that configuration: drivers/gpu/drm/tegra/dc.c: In function 'tegra_dc_late_register': drivers/gpu/drm/tegra/dc.c:1204:28: error: 'struct drm_crtc' has no member named 'debugfs_entry' Without CONFIG_DEBUGFS, the rest of the function already degrades into nothing, so we just avoid the one assignment. Fixes: b95800eeef09 ("drm/tegra: dc: Register debugfs in ->late_register()") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dpaux: Keep reset defaults for hybrid pad parametersThierry Reding1-0/+3
Keep the reset values for the common mode voltage, output driver impedance control and output driver current control parameters. This fixes errors seen during SCDC communication with HDMI sinks. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: Mark Tegra186 display hub PM functions __maybe_unusedArnd Bergmann1-2/+2
The newly introduced driver has optional suspend/resume functions, causing a warning when CONFIG_PM is disabled: drivers/gpu/drm/tegra/hub.c:749:12: error: 'tegra_display_hub_resume' defined but not used [-Werror=unused-function] drivers/gpu/drm/tegra/hub.c:733:12: error: 'tegra_display_hub_suspend' defined but not used [-Werror=unused-function] This marks them __maybe_unused to shut up the warnings. Fixes: c4755fb9064f ("drm/tegra: Add Tegra186 display hub support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: Use IOMMU groupsThierry Reding3-18/+28
In order to support IOMMUs more generically and transparently handle the ARM SMMU on Tegra186, move to using groups instead of devices for domain attachment. An IOMMU group is a set of devices that share the same IOMMU domain and is therefore a good match to represent what Tegra DRM needs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21gpu: host1x: Use IOMMU groupsThierry Reding2-7/+16
Use IOMMU groups to attach the host1x device to its IOMMU domain. This is not strictly necessary because the domain isn't shared with any other device, but it makes the code consistent with how IOMMU is handled in other drivers and provides an easy way to detect when no IOMMU has been attached via device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: Implement zpos propertyThierry Reding5-32/+95
Implement the standard zpos property for planes on Tegra124 and later. Earlier generations have a different blending unit that needs different programming. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Remove redundant spinlockThierry Reding2-12/+2
The spinlock is only used to serialize accesses to the DC_CMD_INT_MASK register. However, this register is accesses either with interrupts masked (in tegra_crtc_atomic_enable()) or protected by the vbl_lock and vblank_time_lock spinlocks of the DRM device. Therefore, these accesses don't need any extra serialization and the lock can be removed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Use direct offset to plane registersThierry Reding5-107/+116
Traditionally, windows were accessed indirectly, through a register selection window that required a global register to be programmed with the index of the window to access. Since the global register could be written from modesetting functions as well as the interrupt handler concurrently, accesses had to be serialized using a lock. Using direct accesses to the window registers the lock can be avoided. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Support more formatsThierry Reding4-22/+235
Also, split up formats into per-SoC lists because not all generations support all of them. Note that the list is now exhaustive for all RGB formats, but not for YUV and indexed formats. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: fb: Force alpha formatsThierry Reding1-0/+13
Tegra20 and Tegra30 don't actually support the 24-bit RGB formats that don't have an alpha component. In order to allow the fbdev emulation to run on those chips, force the 32-bit RGBA formats. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dpaux: Add Tegra186 supportThierry Reding1-0/+1
DPAUX is the same as on previous generations. Supporting it is as simple as adding the compatible string so that the driver will bind to any of the devices. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dpaux: Implement runtime PMThierry Reding1-40/+76
Move clock and reset management into runtime PM callbacks and hook them up. This cleans up the code structure so that power management code does not clutter up the rest. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Support HDMI 2.0 modesThierry Reding2-6/+119
In addition to using the SCDC helpers to enable support for scrambling for HDMI 2.0 modes, take into account the high pixel clocks when programming some of the registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Add Tegra186 supportThierry Reding7-123/+422
The SOR found on Tegra186 is very similar to the one found on Tegra210 and earlier. However, due to some changes in the display architecture, some programming sequences have changed and some register have moved around. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Parameterize register offsetsThierry Reding1-76/+127
Future Tegra generations have an increased number of display controllers that can drive individual SORs. In order to support that, the offset and layout of some registers has changed in backwards-incompatible ways. Use parameterized register offsets to support this. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Support ARGB and ABGR formatsThierry Reding3-0/+14
These formats can easily be supported on all generations of Tegra. Note that the XRGB and XBGR formats that we supported were in fact using the ARGB and ABGR Tegra formats. This happened to work in cases where no alpha was being considered. This change is also a fix for those formats. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Add Tegra186 supportThierry Reding3-82/+267
The display architecture has changed in several signifcant ways with the new Tegra186 SoC. Display controllers are a completely different design, but have been given a frontend that simulates the register interface for earlier chips. Unfortunately the frontend isn't completely backwards compatible, so the driver needs parameterization to take the changes into account. One big change is that the total number of display controllers has been increased to three. At the same time the number of planes available has remained constant. However, planes can now be freely assigned between the display controllers, giving applications more flexibility in making the best use of the available resources. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Add Tegra186 display hub supportThierry Reding8-3/+1103
The display architecture has changed in several significant ways with the new Tegra186 SoC. Shared between all display controllers is a set of common resources referred to as the display hub. The hub generates accesses to memory and feeds them into various composition pipelines, each of which being a window that can be assigned to arbitrary heads. Atomic state is subclassed in order to track the global bandwidth requirements and select and adjust the hub clocks appropriately. The plane code is shared to a large degree with earlier SoC generations, except where the programming differs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Move common plane code to separate fileThierry Reding4-194/+245
Subsequent patches will add support for Tegra186 which has a different architecture and needs different plane code but which can share a lot of code with earlier Tegra support. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Move state definition to headerThierry Reding2-18/+18
Move the display controller state definition to the header file so that it can be referenced by other files. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove duplicate plane funcsThierry Reding1-10/+1
Both tegra_overlay_plane_funcs is identical to tegra_plane_funcs. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove tegra_overlay_plane_destroy()Thierry Reding1-6/+1
This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove duplicate plane funcsThierry Reding1-12/+3
Both tegra_primary_plane_funcs and tegra_cursor_plane_funcs are identical. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove tegra_primary_plane_destroy()Thierry Reding1-6/+1
This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Remove custom page-flip handlerThierry Reding2-48/+17
Tegra display hardware has GO bits and meets all the requirements to use drm_crtc_arm_vblank_event(). Use it instead and get rid of the hand- rolled implementation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Use atomic commit helpersThierry Reding4-107/+27
There's no reason not to use them, and they already get all the semantics right, so rip out all of the custom code and replace it by the helpers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Support background colorThierry Reding2-7/+15
Starting with Tegra124, the interface to set the background color (the value generated for pixels that are not sourced from any window) is via a different register. Earlier generations called this the border color. Reverse the feature flag and assume that IP revisions that don't have support for background color will support border color instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: vic: Properly align argumentsThierry Reding1-1/+1
Properly align function arguments on subsequent lines with the first argument on the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Do not wrap lines unnecessarilyThierry Reding1-2/+1
The tegra_drm_alloc() function signature fits on a single line, no need to wrap it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Register debugfs in ->late_register()Thierry Reding1-34/+19
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Root debugfs files at the connectorThierry Reding1-11/+6
Rather create new files within the top-level DRM device's debugfs node, add the SOR specific files to the connector's debugfs node. This avoids the need to come up with subdirectory names and is also more intuitive. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: hdmi: Register debugfs in ->late_register()Thierry Reding1-265/+245
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dsi: Register debugfs in ->late_register()Thierry Reding1-40/+18
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Register debugfs in ->late_register()Thierry Reding2-365/+335
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Reshuffle some codeThierry Reding1-76/+76
Reshuffle some code so that functions are defined closer to where they are used. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Move register definitions into a tableThierry Reding1-120/+126
After commit 932f6529139e ("drm/tegra: sor: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: hdmi: Move register definitions into a tableThierry Reding1-170/+176
After commit 07a8aab89927 ("drm/tegra: hdmi: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dsi: Move register definitions into a tableThierry Reding1-87/+83
After commit 75af8fa7fd47 ("drm/tegra: dsi: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Move register definitions into a tableThierry Reding1-218/+224
After commit 67e04d1ab19b ("drm/tegra: dc: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13dt-bindings: display: tegra: Update SOR for Tegra186Thierry Reding1-1/+13
Update the SOR bindings for Tegra186, in which a new property is required to identify the instance of the SOR interface and the clock tree has slightly changed as well. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13gpu: host1x: Cleanup on initialization failureThierry Reding1-2/+9
When an error happens during the initialization of one of the sub- devices, make sure to properly cleanup all sub-devices that have been initialized up to that point. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13gpu: host1x: Rewrite conditional for better readabilityThierry Reding1-5/+7
The current check is slightly difficult to read, rewrite it to improve that a little. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Sanitize format modifiersThierry Reding2-23/+48
The existing format modifier definitions were merged prematurely, and recent work has unveiled that the definitions are suboptimal in several ways: - The format specifiers, except for one, are not Tegra specific, but the names don't reflect that. - The number space is split into two, reserving 32 bits for some "parameter" which most of the modifiers are not going to have. - Symbolic names for the modifiers are not using the standard DRM_FORMAT_MOD_* prefix, which makes them awkward to use. - The vendor prefix NV is somewhat ambiguous. Fortunately, nobody's started using these modifiers, so we can still fix the above issues. Do so by using the standard prefix. Also, remove TEGRA from the name of those modifiers that exist on NVIDIA GPUs as well. In case of the block linear modifiers, make the "parameter" smaller (4 bits, though only 6 values are valid) and don't let that leak into any of the other modifiers. Finally, also use the more canonical NVIDIA instead of the ambiguous NV prefix. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/fourcc: Fix fourcc_mod_code() definitionThierry Reding1-1/+1
Avoid a compiler warnings when the val parameter is an expression. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-08drm/qxl: reapply cursor after resetting primaryRay Strode2-0/+61
QXL associates mouse state with its primary plane. Destroying a primary plane and putting a new one in place has the side effect of destroying the cursor as well. This commit changes the driver to reapply the cursor any time a new primary is created. It achieves this by keeping a reference to the cursor bo on the qxl_crtc struct. This fix is very similar to commit 4532b241a4b7 ("drm/qxl: reapply cursor after SetCrtc calls") which got implicitly reverted as part of implementing the atomic modeset feature. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Dave Airlie <airlied@redhat.com> Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1512097 Fixes: 1277eed5fecb ("drm: qxl: Atomic phase 1: convert cursor to universal plane") Cc: stable@vger.kernel.org Signed-off-by: Ray Strode <rstrode@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-08drm/qxl: unref cursor bo when finished with itRay Strode1-1/+3
qxl_cursor_atomic_update allocs a bo for the cursor that it never frees up at the end of the function. This commit fixes that. Signed-off-by: Ray Strode <rstrode@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-08Merge tag 'drm-intel-next-2017-12-01' of ↵Dave Airlie61-2057/+2839
git://anongit.freedesktop.org/drm/drm-intel into drm-next [airlied: fix conflict in intel_dsi.c] drm-intel-next-2017-12-01: - Init clock gate fix (Ville) - Execlists event handling corrections (Chris, Michel) - Improvements on GPU Cache invalidation and context switch (Chris) - More perf OA changes (Lionel) - More selftests improvements and fixes (Chris, Matthew) - Clean-up on modules parameters (Chris) - Clean-up around old ringbuffer submission and hw semaphore on old platforms (Chris) - More Cannonlake stabilization effort (David, James) - Display planes clean-up and improvements (Ville) - New PMU interface for perf queries... (Tvrtko) - ... and other subsequent PMU changes and fixes (Tvrtko, Chris) - Remove success dmesg noise from rotation (Chris) - New DMC for Kabylake (Anusha) - Fixes around atomic commits (Daniel) - GuC updates and fixes (Sagar, Michal, Chris) - Couple gmbus/i2c fixes (Ville) - Use exponential backoff for all our wait_for() (Chris) - Fixes for i915/fbdev (Chris) - Backlight fixes (Arnd) - Updates on shrinker (Chris) - Make Hotplug enable more robuts (Chris) - Disable huge pages (TPH) on lack of a needed workaround (Joonas) - New GuC images for SKL, KBL, BXT (Sagar) - Add HW Workaround for Geminilake performance (Valtteri) - Fixes for PPS timings (Imre) - More IPS fixes (Maarten) - Many fixes for Display Port on gen2-gen4 (Ville) - Retry GPU reset making the recover from hang more robust (Chris) * tag 'drm-intel-next-2017-12-01' of git://anongit.freedesktop.org/drm/drm-intel: (101 commits) drm/i915: Update DRIVER_DATE to 20171201 drm/i915/cnl: Mask previous DDI - PLL mapping drm/i915: Remove unsafe i915.enable_rc6 drm/i915: Sleep and retry a GPU reset if at first we don't succeed drm/i915: Interlaced DP output doesn't work on VLV/CHV drm/i915: Pass crtc state to intel_pipe_{enable,disable}() drm/i915: Wait for pipe to start on i830 as well drm/i915: Fix vblank timestamp/frame counter jumps on gen2 drm/i915: Fix deadlock in i830_disable_pipe() drm/i915: Fix has_audio readout for DDI A drm/i915: Don't add the "force audio" property to DP connectors that don't support audio drm/i915: Disable DP audio for g4x drm/i915/selftests: Wake the device before executing requests on the GPU drm/i915: Set fake_vma.size as well as fake_vma.node.size for capture drm/i915: Tidy up signed/unsigned comparison drm/i915: Enable IPS with only sprite plane visible too, v4. drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3. drm/i915: Avoid PPS HW/SW state mismatch due to rounding drm/i915: Skip switch-to-kernel-context on suspend when wedged drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too ...
2017-12-08Merge tag 'drm-misc-next-2017-12-07' of ↵Dave Airlie89-663/+3661
git://anongit.freedesktop.org/drm/drm-misc into drm-next UAPI Changes: - Add "panel orientation" property to DRM to indicate orientation of the panel vs the device's casing (Hans de Goede) Core Changes: - misc doc and bug fixes Driver Changes: - sun4i: Many improvements to the DE driver like multi-plane support and YUV formats (Jernej Skrabec) * tag 'drm-misc-next-2017-12-07' of git://anongit.freedesktop.org/drm/drm-misc: (50 commits) drm/sun4i: Fix uninitialized variables in vi layer drm/fb-helper: Fix potential NULL pointer dereference gpu: drm: stm: Adopt SPDX identifiers gpu: drm: sti: Adopt SPDX identifiers drm/fsl-dcu: Use drm_mode_config_helper_suspend/resume() drm/sun4i: Wire in DE2 YUV support drm/sun4i: Expand DE2 scaler lib with YUV support drm/sun4i: Add DE2 definitions for YUV formats drm/sun4i: Add DE2 CSC library drm/sun4i: Add CCSC property to DE2 configuration drm/sun4i: Add support for HW scaling to DE2 drm/sun4i: Add scaler configuration to DE2 mixers drm/sun4i: Add support for DE2 VI planes drm/sun4i: Reorganize UI layer code in DE2 drm/sun4i: Add support for all HW supported DE2 RGB formats drm/sun4i: Add multi plane support to DE2 driver drm/sun4i: Move interlace related code in DE2 drm/sun4i: Move channel size related code in DE2 drm/sun4i: Move line width setting in DE2 drm/sun4i: Use values calculated by atomic check ...
2017-12-07drm/sun4i: Fix uninitialized variables in vi layerJernej Skrabec1-0/+3
min_scale and max_scale in sun8i_vi_layer_atomic_check() can be used without initialization. Fix that. Fixes: b862a648de3b ("drm/sun4i: Add support for HW scaling to DE2") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171206152603.25937-1-jernej.skrabec@siol.net
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