summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2017-04-19Merge tag 'v4.12-rockchip-dts32-2' of ↵Olof Johansson5-0/+821
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Support for the usb-sata controller on the rock2 and another new rk3288 board, the phyCORE som and its PCM-947 carrier board from Phytec. * tag 'v4.12-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Add support for PCM-947 carrier board dt-bindings: Document Phytec phyCORE-RK3288 RDK ARM: dts: rockchip: Add support for phyCORE-RK3288 SoM ARM: dts: rockchip: Enable sata support on rock2 square Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'samsung-dt-4.12' of ↵Olof Johansson15-44/+77
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt Samsung DeviceTree ARM update for v4.12: 1. Enhancements to PCIe nodes on Exynos5440. 2. Fix thermal values on some of Exynos5420 boards like Odroid XU3. 3. Add proper clock frequency properties to DSI nodes. 4. Fix watchdog reset on Exynos4412. 5. Fix watchdog infinite interrupt in soft mode on Exynos4210, Exynos5440, S3C64xx and S5Pv210. 6. Enable watchdog on Exynos4 and S3C SoCs. * tag 'samsung-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: add HDMI controller phandle to exynos4.dtsi ARM: dts: s5pv210: Fix infinite interrupt in soft mode ARM: dts: s3c64xx: Fix infinite interrupt in soft mode ARM: dts: exynos: Fix infinite interrupt in soft mode on Exynos4210 and Exynos5440 ARM: dts: exynos: Enable watchdog on all Exynos4 boards ARM: dts: s3c64xx: Enable watchdog on all S3C64xx boards ARM: dts: exynos: Fix watchdog reset on Exynos4412 ARM: dts: exynos: Add the burst and esc clock frequency properties to DSI node ARM: dts: exynos: Do not ignore real-world fuse values for thermal zone 0 on Exynos5420 ARM: dts: exynos: Add phy-pcie node for pcie to Exynos5440 Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'mvebu-dt-4.12-2' of git://git.infradead.org/linux-mvebu into next/dtOlof Johansson4-21/+20
mvebu dt for 4.12 (part 2) Use disk-activity trigger for armada-385-linksys Keep dts alphabetically ordered for clearfog (Armada 388) * tag 'mvebu-dt-4.12-2' of git://git.infradead.org/linux-mvebu: ARM: dts: armada-385-linksys: disk-activity trigger for all ARM: dts: clearfog: keep dts alphabetically ordered Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'renesas-dt2-for-v4.12' of ↵Olof Johansson16-19/+151
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Second Round of Renesas ARM Based SoC DT Updates for v4.12 Corrections: * Correct clock frequency of X2 DU clock input for r8a7791/koelsch board * Correct Z clock for r8a7792 SoC * Correct parent of SSI[0-9] clocks for r8a779[013] SoCs * Correct ethernet clock parent on r7s72100 SoC * Correct DU clock for r8a7794/silk board Cleanups: * Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs Enhancements: * Enable rtc r7s72100/genmai board * Add Z2 clock for r8a7794 SoC * Add DU clock for r8a7794 SoC * Add power-domains to SDHI for r8a7794 and r7s72100 SoCs * Add reset control properties for r8a774[35] SoCs * tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits) ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name ARM: dts: genmai: Enable rtc and rtc_x1 clock ARM: dts: rskrza1: add rtc DT support ARM: dts: rskrza1: set rtc_x1 clock value ARM: dts: r7s72100: add rtc to device tree ARM: dts: r7s72100: add RTC_X clock inputs to device tree ARM: dts: r7s72100: add rtc clock to device tree ARM: dts: koelsch: Correct clock frequency of X2 DU clock input ARM: dts: r8a7794: Add Z2 clock ARM: dts: r8a7792: Correct Z clock ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks ARM: dts: r7s72100: fix ethernet clock parent ARM: dts: silk: Correct clock of DU1 ARM: dts: alt: Correct clock of DU1 ARM: dts: r8a7794: Correct clock of DU1 ARM: dts: r8a7794: Add DU1 clock to device tree ARM: dts: r7s72100: add power-domains to sdhi ... Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'qcom-dts-for-4.12' of ↵Olof Johansson4-43/+307
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm Device Tree Changes for v4.12 * Add Coresight components for MSM8974 * Fixup MSM8974 ADSP XO clk and add RPMCC node * Fix typo in APQ8060 * Add SDCs on MSM8660 * Revert MSM8974 USB gadget change due to issues * tag 'qcom-dts-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: Revert "ARM: dts: qcom: msm8974: Add USB gadget nodes" ARM: dts: qcom: msm8974: Add RPMCC DT node ARM: dts: fix typo on APQ8060 Dragonboard ARM: dts: add SDC2 and SDC4 to the MSM8660 family ARM: dts: msm8974: Hook up adsp-pil's xo clock ARM: dts: qcom: Add msm8974 CoreSight components Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'tegra-for-4.12-dt-bindings' of ↵Olof Johansson2-2/+31
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt dt-bindings: Updates for v4.12-rc1 This contains an update for the flow controller device tree binding as well as the addition of the binding for the GP10B GPU found on the new Tegra186 (Parker) SoC. * tag 'tegra-for-4.12-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: Add documentation for GP10B GPU dt-bindings: tegra: Update compatible strings for Tegra flowctrl Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'sunxi-dt-h3-for-4.12' of ↵Olof Johansson4-564/+698
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner H3 DT changes for 4.12 H3 patches for 4.12, which are mostly related to reworking the H3 DTSI to be usable on the arm64 H5 DTSI, that shares almost everything with the H3 but the CPU cores. We also have some new device addition (USB, mostly) that would conflict otherwise. * tag 'sunxi-dt-h3-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: sun8i: h2+: enable USB OTG for Orange Pi Zero board ARM: sun8i: h3: enable USB OTG on Orange Pi One ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5 arm: sun8i: h3: split Allwinner H3 .dtsi arm: sun8i: h3: correct the GIC compatible in H3 to gic-400 arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'sunxi-dt-for-4.12' of ↵Olof Johansson88-968/+806
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner DT changes for 4.12 As usual a number of changes, among which: - All the sun5i DTSI has been reworked based on the new documentation and the IPs that are actually found in all those SoCs. Part of that rework also brought the GR8 DTSI to include sun5i.dtsi - Mali devfreq and thermal throttling support on the A33 - AC power supplies for the AXP209 and AXP22X PMIC - CAN support for the A20 - CPUFreq-based thermal throttling for the A33 - New board: NanoPi NEO Air * tag 'sunxi-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (38 commits) ARM: sun8i: sina33: add highest OPP of CPUs ARM: sun8i: a33: Add devfreq-based GPU cooling ARM: sun8i: a33: add CPU thermal throttling ARM: sun8i: a33: add thermal sensor ARM: dts: sun7i: fix device node ordering ARM: dts: sun4i: fix device node ordering ARM: dts: sun7i: Add can0_pins_a pinctrl settings ARM: dts: sun7i: Add CAN node ARM: dts: sun4i: Add can0_pins_a pinctrl settings ARM: dts: sun4i: Add CAN node ARM: sun7i: cubietruck: enable ACIN und USB power supply subnode ARM: dts: sun5i: Add interrupt for display backend dt-bindings: display: sun4i: Add display backend interrupt to device tree binding ARM: dts: sun7i: Use axp209.dtsi on A20-OLinuXino-Micro ARM: dts: sun6i: sina31s: Enable SPDIF out ARM: sun8i: sina33: add cpu-supply ARM: sun8i: a33: add all operating points ARM: sun5i: chip: enable ACIN power supply subnode ARM: dts: sun8i: sina33: enable ACIN power supply subnode ARM: dtsi: axp22x: add AC power supply subnode ... Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'socfpga_dts_for_v4.12' of ↵Olof Johansson13-64/+96
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA DTS updates for v4.12 - Clean-up: - Add clock/memory nodes - Add labels for CPU nodes - Remove unused unit names and reg - Remove unused skeleton.dtsi - Add support for PMU - Add QSPI for sodia board - Add Reset controller for Arria10 * tag 'socfpga_dts_for_v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: Add Devkit A10-SR Reset Controller ARM: dts: socfpga: sodia: enable qspi ARM: dts: socfpga: Add support for PMU ARM: dts: socfpga: Add labels for CPU nodes ARM: dts: socfpga: Do not include skeleton.dtsi ARM: dts: socfpga: Remove unit name for LEDs in EBV SOCrates ARM: dts: socfpga: Remove unneeded reg from stmpe_touchscreen ARM: dts: socfpga: Remove unneeded unit names ARM: dts: socfpga: Add unit name to memory nodes ARM: dts: socfpga: Add unit name to clock nodes Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'davinci-for-v4.12/dt-2' of ↵Olof Johansson2-7/+6
git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt A clean-up device-tree patch to ensure pinmux entry reuse. * tag 'davinci-for-v4.12/dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: dts: da850: move spi0_cs3_pin pinconf node Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge tag 'stm32-dt-for-v4.12-1' of ↵Olof Johansson12-28/+601
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt STM32 DT updates for v4.12, round 1 Highlights: ---------- - ADD RTC support on STM32F746 MCU - Enable RTC on STM32F746 Eval board - Enable clocks on STM32F746 MCU - Enable DMA, pwm1 and pwm3 on STM32F429I Eval - Add support of STM32H743 MCU and his Eval board - Enable USB HS and FS on STM32F469 Disco board * tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: dt-bindings: Document the STM32 USB OTG DWC2 core binding ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-disco ARM: dts: stm32: Enable USB FS on stm32f469-disco ARM: dts: stm32: Add USB FS support for STM32F429 MCU ARM: dts: stm32: Add STM32H743 MCU and STM32H743i-EVAL board ARM: dts: stm32: Enable pwm1 and pwm3 on stm32f429i-eval ARM: dts: stm32: Enable dma by default on stm32f4 adc ARM: dts: stm32: enable RTC on stm32746g-eval ARM: dts: stm32: Add RTC support for STM32F746 MCU ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746 dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file ARM: dts: stm32: Enable clocks for STM32F746 MCU Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19Merge branch 'sti-dt-for-v4.12-round1' of ↵Olof Johansson1-2/+16
git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/dt * 'sti-dt-for-v4.12-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: ARM: dts: STiH407-family: update rproc node names to avoid conflict ARM: dts: STiH407-family: fix spi nodes Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-07Revert "ARM: dts: qcom: msm8974: Add USB gadget nodes"Andy Gross2-47/+0
This reverts commit 769907ae6e6c2871c2ba4f578814d86fbfbe8d91. This change caused issues with people using USB gadget for serial consoles. In addition, with the other USB changes coming in, it makes sense to revert this patch and apply the new set as it becomes ready. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-04-07ARM: dts: rockchip: Add support for PCM-947 carrier boardWadim Egorov2-0/+299
Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination with the phyCORE-RK3288 System on Module. Following interfaces and devices are available on the PCM-947 carrier board: - 2x UART - micro SDMMC - USB host and USB otg - USB 3503 HSIC hub - Ethernet - 2nd alternative KSZ9031 ethernet phy - Display connectors: PHYTEC LVDS, DDG LVDS, parallel signals, HDMI - Parallel Camera CIF - SGTL5000-32QFN audio codec - 4x LEDs connected via PCA9533 - 2 user buttons - Expansion connectors for WiFi and other modules - RTC RV-4162-C7 - Resistive touch STMPE811 - EEPROM M24C32 Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-07dt-bindings: Document Phytec phyCORE-RK3288 RDKWadim Egorov1-0/+4
Add documentation for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-07ARM: dts: rockchip: Add support for phyCORE-RK3288 SoMWadim Egorov1-0/+497
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC. The module can be connected to different carrier boards. It can be also equipped with different RAM, SPI flash and eMMC variants. The Rapid Development Kit option is using the following setup: - 1 GB DDR3 RAM (2 Banks) - 1x 4 KB EEPROM - DP83867 Gigabit Ethernet PHY - 16 MB SPI Flash - 4 GB eMMC Flash Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-05ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node nameGeert Uytterhoeven1-1/+1
The current practice is to not add _clk suffixes to clock node names in DT, as these names are used as the actual clock names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-05ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node nameGeert Uytterhoeven1-1/+1
The current practice is to not add _clk suffixes to clock node names in DT, as these names are used as the actual clock names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-05ARM: dts: genmai: Enable rtc and rtc_x1 clockJacopo Mondi1-0/+8
Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to non-zero and enable the realtime clock. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-05ARM: dts: armada-385-linksys: disk-activity trigger for allRalph Sennhauser3-2/+1
Commit a4ee7e18d808 ("ARM: dts: armada: Add default trigger for sata led") adds the default trigger to individual boards, move it to armada-385-linksys.dtsi which effectively enables the definition for the WRT1900ACS (Shelby) as well as for future boards. Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-05ARM: sun8i: sina33: add highest OPP of CPUsQuentin Schulz1-0/+14
The A33 supports 1.1GHz and 1.2GHz frequencies at 1.32V and the Sinlinx SinA33 has its cpu-supply property set in the cpu DT node. Therefore, CPUfreq knows how to handle the regulator in charge of the CPU and can adjust its voltage to match the OPP. Add these two CPU frequencies to the CPU OPP table of the Sinlinx SinA33. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05ARM: sun8i: a33: Add devfreq-based GPU coolingMaxime Ripard2-0/+25
This adds GPU thermal throttling for the Allwinner A33. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
2017-04-05ARM: sun8i: a33: add CPU thermal throttlingQuentin Schulz1-0/+45
This adds CPU thermal throttling for the Allwinner A33. It uses the thermal sensor present in the SoC's GPADC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05ARM: sun8i: a33: add thermal sensorQuentin Schulz1-0/+12
This adds the DT node for the thermal sensor present in the Allwinner A33 GPADC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05ARM: dts: sun7i: fix device node orderingPatrick Menschel1-15/+16
This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05ARM: dts: sun4i: fix device node orderingPatrick Menschel1-16/+16
This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04ARM: dts: rskrza1: add rtc DT supportChris Brandt1-0/+4
Enable the realtime clock. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-04ARM: dts: rskrza1: set rtc_x1 clock valueChris Brandt1-0/+4
Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to non-zero. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-04ARM: dts: r7s72100: add rtc to device treeChris Brandt1-0/+14
Add the realtime clock device node. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-04ARM: dts: r7s72100: add RTC_X clock inputs to device treeChris Brandt1-0/+14
Add the RTC clocks to device tree. The frequencies must be fixed values according to the hardware manual. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-04ARM: dts: r7s72100: add rtc clock to device treeChris Brandt2-0/+12
Add the realtime clock functional clock source. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-04ARM: dts: koelsch: Correct clock frequency of X2 DU clock inputGeert Uytterhoeven1-1/+1
The X2 crystal oscillator on the Koelsch development board provides a 74.25 MHz clock, not a 148.5 MHz clock. Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel clocks to DT") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-04ARM: dts: sun7i: Add can0_pins_a pinctrl settingsPatrick Menschel1-0/+5
The A20 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04ARM: dts: sun7i: Add CAN nodePatrick Menschel1-0/+9
The A20 SoC has an on-board CAN controller. This patch adds the device node. The CAN controller is inherited from the A10 SoC and uses the same driver. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04ARM: dts: sun4i: Add can0_pins_a pinctrl settingsPatrick Menschel1-0/+5
The A10 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04ARM: dts: sun4i: Add CAN nodePatrick Menschel1-0/+8
The A10 SoC has an on-board CAN controller. This patch adds the device node. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04dt-bindings: Add documentation for GP10B GPUAlexandre Courbot1-1/+24
GP10B's definition is mostly similar to GK20A's and GM20B's. The only noticeable difference is the use of power domains instead of a regulator for power supply. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04dt-bindings: tegra: Update compatible strings for Tegra flowctrlJon Hunter1-1/+7
Update the compatible strings for Tegra Flow Control driver to match the device-tree source files for Tegra. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-03ARM: sun7i: cubietruck: enable ACIN und USB power supply subnodeAlexander Syring1-0/+8
The Cubietruck has an AXP209 PMIC and can be power-supplied by ACIN via the CHG-IN pin or by USB. This enables the ACIN and the USB power supply subnode in the DT. Signed-off-by: Alexander Syring <alex@asyring.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-03ARM: dts: r8a7794: Add Z2 clockGeert Uytterhoeven1-0/+8
Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider, and link the first CPU node to it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-03ARM: dts: r8a7792: Correct Z clockGeert Uytterhoeven2-3/+9
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a fixed divider. This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2. Hence: - Remove the Z clock output from the cpg_clocks node, as this implied a programmable clock, - Add the Z clock as a fixed factor clock, - Let the first CPU node point to the new Z clock, - Remove the Z clock index from the bindings (this definition was used by r8a7792.dtsi only, and was not a contract between DT and driver). Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-03ARM: dts: r8a7793: Correct parent of SSI[0-9] clocksGeert Uytterhoeven1-2/+5
The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: 072d326542e49187 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-03ARM: dts: r8a7791: Correct parent of SSI[0-9] clocksGeert Uytterhoeven1-2/+5
The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: ee9141522dcf13f8 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-03ARM: dts: r8a7790: Correct parent of SSI[0-9] clocksGeert Uytterhoeven1-2/+5
The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-03ARM: dts: r7s72100: fix ethernet clock parentChris Brandt1-1/+1
Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not the 33MHz Peripheral 0 (P0) clock. Fixes: 969244f9c720 ("ARM: dts: r7s72100: add ethernet clock to device tree") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-03dt-bindings: Document the STM32 USB OTG DWC2 core bindingBruno Herrera1-0/+4
This patch adds the documentation for STM32F4x9 USB OTG FS/HS compatible strings. Signed-off-by: Bruno Herrera <bruherrera@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
2017-04-03ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-discoBruno Herrera1-0/+16
This patch enables USB HS working in FS mode on stm32f429-disco with 5V VBUS enable. Signed-off-by: Bruno Herrera <bruherrera@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
2017-04-03ARM: dts: stm32: Enable USB FS on stm32f469-discoBruno Herrera1-0/+16
This patch enables USB FS on stm32f469-disco with 5V VBUS enable. Signed-off-by: Bruno Herrera <bruherrera@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
2017-04-03ARM: dts: stm32: Add USB FS support for STM32F429 MCUBruno Herrera1-0/+31
This patch adds the USB pins and nodes for USB FS core. Signed-off-by: Bruno Herrera <bruherrera@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
2017-03-31Merge tag 'arm-soc/for-4.11/devicetree-fixes' of ↵Arnd Bergmann1-3/+2
http://github.com/Broadcom/stblinux into fixes There was a little conflict between the v4.11 bugfixes and the new changes for 4.12, this merges the fixes into the 4.12 branch to avoid having to resolve it again. * Broadcom fixes in mainline ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags ARM: dts: BCM5301X: Fix memory start address ARM: dts: BCM5301X: Fix UARTs on bcm953012k Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 16:08:13 +0300