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2020-07-11Merge branch 'clk-qcom' into clk-nextStephen Boyd5-0/+241
* clk-qcom: clk: qcom: smd: Add support for MSM8992/4 rpm clocks clk: qcom: ipq8074: Add missing clocks for pcie dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
2020-07-11clk: qcom: smd: Add support for MSM8992/4 rpm clocksKonrad Dybcio3-0/+177
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992, MSM8994 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623230018.303776-1-konradybcio@gmail.com [sboyd@kernel.org: Fixed up binding numbers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11clk: qcom: ipq8074: Add missing clocks for pcieSivaprakash Murugesan1-0/+60
Add missing clocks and resets for pcie port0 of ipq8074 devices. Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1593940680-2363-5-git-send-email-sivaprak@codeaurora.org [sboyd@kernel.org: Make freq table static const] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIeSivaprakash Murugesan1-0/+4
Add missing clock bindings for PCIe port0 of ipq8074. Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1593940680-2363-4-git-send-email-sivaprak@codeaurora.org [sboyd@kernel.org: Clean up commit text subject] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11Merge branch 'clk-renesas' into clk-nextStephen Boyd18-271/+260
* clk-renesas: clk: renesas: rzg2: Mark RWDT clocks as critical clk: renesas: rcar-gen3: Mark RWDT clocks as critical clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot dt-bindings: clock: renesas: cpg: Convert to json-schema
2020-07-11Merge tag 'clk-renesas-for-v5.9-tag1' of ↵Stephen Boyd18-271/+260
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - One more conversion of DT bindings to json-schema - Enhance critical clock handling to only consider clocks that were enabled at boot time, and use it for watchdog clock handling on R-Car Gen3 and RZ/G2 SoCs * tag 'clk-renesas-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rzg2: Mark RWDT clocks as critical clk: renesas: rcar-gen3: Mark RWDT clocks as critical clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot dt-bindings: clock: renesas: cpg: Convert to json-schema
2020-07-11Merge branch 'clk-https' into clk-nextStephen Boyd14-19/+19
* clk-https: Replace HTTP links with HTTPS ones: Common CLK framework
2020-07-11Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov14-19/+19
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Link: https://lore.kernel.org/r/20200703175114.15027-1-grandmaster@al2klimov.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11Merge branch 'clk-qcom' into clk-nextStephen Boyd12-68/+711
- Enable CPU clks on Qualcomm MSM8996 SoCs * clk-qcom: clk: qcom: Add CPU clock driver for msm8996 dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996 soc: qcom: Separate kryo l2 accessors from PMU driver clk: qcom: Fix return value check in apss_ipq6018_probe()
2020-07-11clk: qcom: Add CPU clock driver for msm8996Loic Poulain4-0/+554
Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk ACD stands for Adaptive Clock Distribution and is used to detect voltage droops. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84 Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Ilia Lin: - reworked clock registering - Added clock-tree diagram - non-builtin support - clock notifier on rate change - https://lkml.org/lkml/2018/5/24/123 Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Loic Poulain: - fixed driver remove / clk deregistering - Removed useless memory barriers - devm usage when possible - Fixed Kconfig depends Link: https://lore.kernel.org/r/1593766185-16346-3-git-send-email-loic.poulain@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996Ilia Lin1-0/+56
Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1593766185-16346-4-git-send-email-loic.poulain@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11soc: qcom: Separate kryo l2 accessors from PMU driverIlia Lin6-66/+99
The driver provides kernel level API for other drivers to access the MSM8996 L2 cache registers. Separating the L2 access code from the PMU driver and making it public to allow other drivers use it. The accesses must be separated with a single spinlock, maintained in this driver. Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1593766185-16346-2-git-send-email-loic.poulain@linaro.org Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-30clk: qcom: Fix return value check in apss_ipq6018_probe()Wei Yongjun1-2/+2
In case of error, the function dev_get_regmap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200628023055.50608-1-weiyongjun1@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-26Merge branch 'clk-bcm' into clk-nextStephen Boyd23-256/+1136
- Make defines for bcm63xx-gate clks to use in DT - Support gate clks on BCM6318 SoCs - Add HDMI clks for BCM2711 SoCs - Support BCM2711 SoC firmware clks * clk-bcm: (42 commits) clk: bcm: dvp: Add missing module informations clk: bcm: rpi: Remove the quirks for the CPU clock clk: bcm2835: Don't cache the PLLB rate clk: bcm2835: Allow custom CCF flags for the PLLs Revert "clk: bcm2835: remove pllb" clk: bcm: rpi: Give firmware clocks a name clk: bcm: rpi: Discover the firmware clocks clk: bcm: rpi: Add an enum for the firmware clocks clk: bcm: rpi: Add DT provider for the clocks clk: bcm: rpi: Make the PLLB registration function return a clk_hw clk: bcm: rpi: Split pllb clock hooks clk: bcm: rpi: Rename is_prepared function clk: bcm: rpi: Pass the clocks data to the firmware function clk: bcm: rpi: Add clock id to data clk: bcm: rpi: Create a data structure for the clocks clk: bcm: rpi: Use CCF boundaries instead of rolling our own clk: bcm: rpi: Make sure the clkdev lookup is removed clk: bcm: rpi: Switch to clk_hw_register_clkdev clk: bcm: rpi: Remove pllb_arm_lookup global pointer clk: bcm: rpi: Make sure pllb_arm is removed ...
2020-06-26clk: bcm: dvp: Add missing module informationsMaxime Ripard1-0/+4
The driver for the DVP controller in the BCM2711 was missing the MODULE_* macros resulting in a modpost warning at compilation. Fixes: 1bc95972715a ("clk: bcm: Add BCM2711 DVP driver") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200626112513.90816-1-maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-23Merge branch 'clk-vc5' into clk-nextStephen Boyd3-47/+239
* clk-vc5: clk: vc5: Enable addition output configurations of the Versaclock dt: Add additional option bindings for IDT VersaClock clk: vc5: Allow Versaclock driver to support multiple instances
2020-06-23clk: vc5: Enable addition output configurations of the VersaclockAdam Ford1-0/+156
The existing driver is expecting the Versaclock to be pre-programmed, and only sets the output frequency. Unfortunately, not all devices are pre-programmed, and the Versaclock chip has more options beyond just the frequency. This patch enables the following additional features: - Programmable voltage: 1.8V, 2.5V, or 3.3V​ - Slew Percentage of normal: 85%, 90%, or 100% - Output Type: LVPECL, CMOS, HCSL, or LVDS Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20200603154329.31579-3-aford173@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-23dt: Add additional option bindings for IDT VersaClockAdam Ford2-0/+46
The VersaClock driver now supports some additional bindings to support child nodes which can configure optional settings like mode, voltage and slew. This patch updates the binding document to describe what is available in the driver. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200603154329.31579-2-aford173@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-23clk: vc5: Allow Versaclock driver to support multiple instancesAdam Ford1-47/+37
Currently, the Versaclock driver is only expecting one instance and uses hard-coded names for the various clock names. Unfortunately, this is a problem when there is more than one instance of the driver, because the subsequent instantiations of the driver use the identical name. Each clock after the fist fails to load, because the clock subsystem cannot handle two clocks with identical name. This patch removes the hard-coded name arrays and uses kasprintf to assign clock names based on names of their respective node and parent node which gives each clock a unique identifying name. For a verasaclock node with a name like: versaclock5: versaclock_som@6a The updated clock names would appear like: versaclock_som.mux versaclock_som.out0_sel_i2cb versaclock_som.pfd versaclock_som.pll versaclock_som.fod3 versaclock_som.out4 versaclock_som.fod2 versaclock_som.out3 versaclock_som.fod1 versaclock_som.out2 versaclock_som.fod0 versaclock_som.out1 Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20200603154329.31579-1-aford173@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-23Merge branch 'clk-qcom' into clk-nextStephen Boyd9-1/+394
- Enable CPU clks on Qualcomm IPQ6018 SoCs * clk-qcom: clk: qcom: smd: Add support for MSM8936 rpm clocks dt-bindings: clock: rpmcc: Document MSM8936 compatible clk: qcom: smd: Add support for SDM660 rpm clocks clk: qcom: Add ipq6018 apss clock controller clk: qcom: Add DT bindings for ipq6018 apss clock controller clk: qcom: Add ipq apss pll driver dt-bindings: clock: add ipq6018 a53 pll compatible
2020-06-23clk: qcom: smd: Add support for MSM8936 rpm clocksVincent Knecht2-0/+52
Add missing definition of rpm clk for msm8936 soc (also used by msm8939) Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20200613072745.1249003-2-vincent.knecht@mailoo.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-23dt-bindings: clock: rpmcc: Document MSM8936 compatibleVincent Knecht1-0/+1
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20200613072745.1249003-3-vincent.knecht@mailoo.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22clk: renesas: rzg2: Mark RWDT clocks as criticalUlrich Hecht3-0/+3
Ensures RWDT remains alert throughout the boot process if enabled. This patch applies the change to the following SoCs: r8a774a1, r8a774b1 and r8a774c0. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200616162626.27944-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-22clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht7-5/+7
Ensures RWDT remains alert throughout the boot process if enabled. This patch applies the change to the following SoCs: r8a77950, r8a77951, r8a77960, r8a77961, r8a77965, r8a77970, r8a77980, r8a77990 and r8a77995. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200616162626.27944-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-22clk: renesas: cpg-mssr: Mark clocks as critical only if on at bootUlrich Hecht1-8/+9
This allows us to add the RWDT clock to the list of critical clocks without keeping it enabled needlessly if not used. Changing the semantics of crit_mod_clks in this way is safe for the current user (INTC-AP) because it is never off at boot time. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200616162626.27944-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-22clk: qcom: smd: Add support for SDM660 rpm clocksKonrad Dybcio3-0/+87
Add rpm smd clocks, PMIC and bus clocks which are required on SDM630/660 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200622090252.36568-1-konradybcio@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22Merge branch 'clk-doc' into clk-nextStephen Boyd1-0/+15
* clk-doc: clk: add function documentation for clk_hw_round_rate()
2020-06-22clk: add function documentation for clk_hw_round_rate()Sarang Mairal1-0/+15
Information about usage and prerequisites for this API. Signed-off-by: Sarang Mairal <sarangmairal@gmail.com> Link: https://lore.kernel.org/r/20200611021941.786-2-sarangmairal@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22clk: qcom: Add ipq6018 apss clock controllerSivaprakash Murugesan3-0/+118
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL and xo which are connected to a mux and enable block. Add support for the mux and enable block which feeds the CPU on ipq6018 devices. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592800092-20533-5-git-send-email-sivaprak@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22clk: qcom: Add DT bindings for ipq6018 apss clock controllerSivaprakash Murugesan1-0/+12
Add dt-binding for ipq6018 apss clock controller Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592800092-20533-4-git-send-email-sivaprak@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22clk: qcom: Add ipq apss pll driverSivaprakash Murugesan3-0/+104
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL. Add support for the apss pll found on ipq based devices which can support CPU frequencies above 1Ghz. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592800092-20533-3-git-send-email-sivaprak@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22dt-bindings: clock: add ipq6018 a53 pll compatibleSivaprakash Murugesan1-1/+20
cpus on ipq6018 are clocked by a53 pll, add device compatible for a53 pll found on ipq6018 devices. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592800092-20533-2-git-send-email-sivaprak@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20Merge branch 'clk-socfpga' into clk-nextStephen Boyd2-3/+9
* clk-socfpga: clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
2020-06-20clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen1-1/+1
Preliminary documentation documented the mpu_l2ram_clk, but since then, the mpu_l2ram_clk is no longer documented. It's now referred to as mpu_ccu_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200616202417.14376-3-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen1-1/+5
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main clock that is feeding the NAND IP and correct it's parent to be the l4_mp_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLKDinh Nguyen1-1/+3
Add the NAND_X_CLK and NAND_ECC_CLK clocks. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200616202417.14376-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Remove the quirks for the CPU clockMaxime Ripard1-164/+0
The CPU clock has had so far a bunch of quirks to expose the clock tree properly, but since we reverted to exposing them through the MMIO driver, we can remove that code from the firmware driver. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/acdf820c2f78a25dd7480a0c018b8b387acd013e.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm2835: Don't cache the PLLB rateMaxime Ripard1-2/+3
The PLLB rate will be changed through the firmware clocks drivers and will change behind this drivers' back, so we don't want to cache the rate. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/9864daba2f584ed49aee5ed1d2f4d48507c58197.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm2835: Allow custom CCF flags for the PLLsMaxime Ripard1-1/+2
While some clock types allow for each clock to specify its own custom flags, the PLLs can't. We will need this for the PLLB, so let's add it. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/ae8bd505d8851f6646e244cd76b6b289346973c8.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20Revert "clk: bcm2835: remove pllb"Maxime Ripard1-4/+26
This reverts commit 2256d89333bd17b8b56b42734a7e1046d52f7fc3. Since we will be expanding the firmware clock driver, we'll need to remove the quirks to deal with the PLLB. However, we still want to expose the clock tree properly, so having that clock in the MMIO driver will allow that. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/5d26a4c58248f5be7760a7f2f720a1310baea5dd.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Give firmware clocks a nameMaxime Ripard1-1/+20
We've registered the firmware clocks using their ID as name, but it's much more convenient to register them using their proper name. Since the firmware doesn't provide it, we have to duplicate it. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/a52a5f5768cd33716cdd35237c6613f26ad75013.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Discover the firmware clocksMaxime Ripard1-12/+141
The RaspberryPi4 firmware actually exposes more clocks than are currently handled by the driver and we will need to change some of them directly based on the pixel rate for the display related clocks, or the load for the GPU. Since the firmware implements DVFS, this rate change can have a number of side-effects, including adjusting the various PLL voltages or the PLL parents. The firmware also implements thermal throttling, so even some thermal pressure can change those parameters behind Linux back. DVFS is currently implemented on the arm, core, h264, v3d, isp and hevc clocks, so updating any of them using the MMIO driver (and thus behind the firmware's back) can lead to troubles, the arm clock obviously being the most problematic. In order to make Linux play as nice as possible with those constraints, it makes sense to rely on the firmware clocks as much as possible. However, the firmware doesn't seem to provide some equivalents to their MMIO counterparts, so we can't really replace that driver entirely. Fortunately, the firmware has an interface to discover the clocks it exposes. Let's use it to discover, register the clocks in the clocks framework and then expose them through the device tree for consumers to use them. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/438d73962741a8c5f7c689319b7443b930a87fde.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Add an enum for the firmware clocksMaxime Ripard1-4/+19
While the firmware allows us to discover the available clocks, we need to discriminate those clocks to only register the ones meaningful to Linux. The firmware also doesn't provide a clock name, so having a list of the ID will help us to give clocks a proper name later on. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/4738f77ee7de9b48a3bb1c558ead958d0cc064d9.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Add DT provider for the clocksMaxime Ripard1-0/+16
For the upcoming registration of the clocks provided by the firmware, make sure it's exposed to the device tree providers. Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/4d8dbe4aaae98b3d3812ad7c3dba53d645cadbaf.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Make the PLLB registration function return a clk_hwMaxime Ripard1-22/+24
The raspberrypi_register_pllb has been returning an integer so far to notify whether the functions has exited successfully or not. However, the OF provider functions in the clock framework require access to the clk_hw structure so that we can expose those clocks to device tree consumers. Since we'll want that for the future clocks, let's return a clk_hw pointer instead of the return code. Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/97218559db643e62fdd2b5e3046a2a05b8c2e769.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Split pllb clock hooksMaxime Ripard1-8/+22
The driver only supports the pllb for now and all the clock framework hooks are a mix of the generic firmware interface and the specifics of the pllb. Since we will support more clocks in the future let's split the generic and specific hooks Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/fdc21962fdc7de5c46232f198672d5d5c868ec74.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Rename is_prepared functionMaxime Ripard1-2/+2
The raspberrypi_fw_pll_is_on function doesn't only apply to PLL registered in the driver, but any clock exposed by the firmware. Since we also implement the is_prepared hook, make the function consistent with the other function names. Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/ac93cc4e245316bb7e7426ac5ab0de8f3d919731.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Pass the clocks data to the firmware functionMaxime Ripard1-15/+14
The raspberry_clock_property only takes the clock ID as an argument, but now that we have a clock data structure it makes more sense to just pass that structure instead. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/d7a3b4df3ca23feb6e0d9c7ae2d232bfb913f926.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Add clock id to dataMaxime Ripard1-9/+9
The driver has really only supported one clock so far and has hardcoded the ID used in communications with the firmware in all the functions implementing the clock framework hooks. Let's store that in the clock data structure so that we can support more clocks later on. Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/e23c37961b97b027e21efa3b818578970f88527a.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-20clk: bcm: rpi: Create a data structure for the clocksMaxime Ripard1-10/+21
So far the driver has really only been providing a single clock, and stored both the data associated to that clock in particular with the data associated to the "controller". Since we will change that in the future, let's decouple the clock data from the provider data. Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/ee7f508db226214fab4add7f93a351f4137c86a1.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-29 20:09:42 +0300