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2014-09-03drm/i915: init sprites with univeral plane init functionDerek Foreman1-4/+4
Really just for completeness - old init function ends up making the plane exactly the same way due to the way the enums are set up. Signed-off-by: Derek Foreman <derek.foreman@collabora.co.uk> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcsVille Syrjälä1-2/+2
Check for !HAS_PCH_SPLIT() instead of 'gen < 5' in the PCH transcoder enable functions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting codeVille Syrjälä2-2/+2
A few open coded HAS_GMCH_DISPLAY() remain in the underrun reporting code. Convert them over. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake codeVille Syrjälä1-3/+3
IS_GEN8() is a bad check in the forcewake code due to bdw vs. chv differences. Use IS_BROADWELL() instead. The only actual bug here is that we currently call __gen7_gt_force_wake_mt_reset() on chv. On the other places we have checked for chv before using IS_GEN8(), but change them to use IS_BROADWELL() anyway to reduce the chance of accidents in the future. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't call gen8_fbc_sw_flush() on chvVille Syrjälä1-1/+6
CHV doesn't have FBC, so don't go calling gen8_fbc_sw_flush() on it. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Add a FIXME comment while at it that we should rework this a lot more.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Remove shadowed local variable 'i' from i915_interrupt_infoChris Wilson1-1/+0
Just a stray local variable, begone. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Rename global latency_ns variableChris Wilson1-18/+18
We use the variable name latency_ns in both the local lowlevel wm calculation routines and at the global level. Rename the global value to reduce shadow warnings and future confusion. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't restrict i915_wa_registers to BDWDamien Lespiau1-5/+0
We have CHV code that already makes the test obsolete. Besides, when num_wa_regs is 0 (platforms not gathering that W/A data), we expose something sensible already. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Remove unneeded bracketsDamien Lespiau1-1/+1
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't silently discard workaroundsDamien Lespiau1-1/+1
If we happen to emit more than I915_MAX_WA_REGS workarounds, we will currently discard them, not even emit the LRI. Not really what we want, so warn loudly. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't overrun the intel_wa_regs arrayDamien Lespiau1-1/+1
When entering intel_ring_emit_wa() with num_wa_regs equal to I915_MAX_WA_REGS, we end up indexing the intel_wa_regs array beyond its allocation. Fix the check then. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Rename intel_wa_registers with a i915_ prefixDamien Lespiau1-2/+2
Those debugfs files are prefixed by i915, the name of the kernel module, presumably to make the difference with files exposed by core DRM. Also, add a ',' at the end of the last entry. This is to ease the conflict resolution when rebasing internal patches that add a member at the end of the array. Without it, wiggle can't do its job as we need to modify an existing line (appending the ','). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: change CHV write_eld/global_resources function pointersPaulo Zanoni1-1/+1
Currently, CHV is using the same functions as HSW/BDW instead of the same functions as VLV. This looks wrong, especially since, for example, valleyview_modeset_global_resouces even has an IS_CHERRYVIEW check. This patch has the potential to fix display audio and the CHV CDCLK. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/hdmi: Cache EDID for a detection cycleChris Wilson1-65/+80
As we may query the edid multiple times following a detect, record the EDID found during output discovery and reuse it. This is a separate issue from caching the output EDID across detection cycles. v2: Also hookup the force() callback for audio detection when the user forces the connection status. v3: Ville spots a typo, s/==/!=/ Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/dp: Cache EDID for a detection cycleChris Wilson2-67/+90
As we may query the edid multiple times following a detect, record the EDID found during output discovery and reuse it. This is a separate issue from caching the output EDID across detection cycles. v2: Implement connector->force() callback so that edid is associated with the connector for user overrides as well (Ville) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/dp: Refactor common eDP lid detectionChris Wilson1-21/+17
Both gmch and pch detection routines used the exact same routine for eDP, so de-duplicate. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: : Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm: Remove old defines for vswing and pre-emph valuesSonika Jindal1-8/+0
This is the last patch in the series, so remove old defines Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Renaming DP training vswing pre emph definesSonika Jindal2-105/+105
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/tegra: Renaming DP training vswing pre emph definesSonika Jindal1-2/+2
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/radeon: Renaming DP training vswing pre emph definesSonika Jindal1-2/+2
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (0 << 0) ... Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Acked-by: Alex Deucher <alexdeucher@gmail.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/gma500: Renaming DP training vswing pre emph definesSonika Jindal2-10/+10
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/exynos: Renaming DP training vswing pre emph definesSonika Jindal1-2/+2
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm: Renaming DP training vswing pre emph definesSonika Jindal1-0/+8
Adding new defines, older one will be removed in the last patch in the series. This is to rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Cc: dri-devel@lists.freedesktop.org Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: debug sink dpms aux errors also on enableJani Nikula1-2/+4
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't call intel_plane_restore() when the prop value didn't changeVille Syrjälä1-0/+3
No point in calling intel_plane_restore() in .set_property() if the value didn't change. More importantly this papers over a bug where the current primary plane code forgets to update the user coordinates we store under intel_plane unless the primary plane .update_plane() hook is actually called. This means we have 0 in the coordinates straight after boot and any call to intel_restore_plane() (such as from restore_fbdev_mode()) will actually turn off the primary plane. This mess needs to be fixed properly but that's a bigger task and the first step there is killing off intel_pipe_set_base() and just calling the primary plane .update_plane() hook. For the immediate problem of black screen after boot this small patch is enough to hide it. The problem originates from these two commits: commit 3a5f87c286515c54ff5c52c3e64d0c522b7570c0 Author: Thomas Wood <thomas.wood@intel.com> Date: Wed Aug 20 14:45:00 2014 +0100 drm: fix plane rotation when restoring fbdev configuration commit d91a2cb8e5104233c02bbde539bd4ee455ec12ac Author: Sonika Jindal <sonika.jindal@intel.com> Date: Fri Aug 22 14:06:04 2014 +0530 drm/i915: Add 180 degree primary plane rotation support Cc: Thomas Wood <thomas.wood@intel.com> Cc: Sonika Jindal <sonika.jindal@intel.com> Tested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Tested-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm: i915: reduce memory footprint when debuggingAndy Shevchenko1-5/+1
There is no need to use hex_dump_to_buffer() since we have a kernel helper to dump up to 64 bytes just via printk(). In our case the actual size is 15 bytes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> [danvet: Add cast since %*ph expects and int for the size parameter.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't use WaGsvRC0ResidenncyMethod on chvVille Syrjälä1-2/+2
WaGsvRC0ResidenncyMethod is for vlv, it doesn't deal with chv appropriately (eg. doesn't limit rps values to even numbers). Fix a typo in the w/a name while at it. Cc: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Preserve VGACNTR bits from the BIOSVille Syrjälä2-1/+9
My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from S3 unless VGACNTR has been restore to the original value. The BIOS value in this case was 0x0124008E. Setting the "VGA disable" bit doesn't interfere with the S3 resume fortunately. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Add pipe B force quirk for 830MVille Syrjälä2-12/+28
830M has problems when some of the pipes are disabled. Namely if a plane, DVO port etc. is currently assigned to a disabled pipe, it can't moved to the other pipe until the current pipe is also enabled. To keep things simple just leave both pipes running all the time. Ideally I think should turn the pipes off if neither is active, and when either becomes active we enable both. But that would reuquire proper atomic modeset support, and probably a bit of extra care in the order things get enabled. v2: Reorder wrt. double wide handling changes Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03Revert "drm/i915: Nuke pipe A quirk on i830M"Ville Syrjälä1-0/+3
830 really does want the pipe A quirk. The planes and ports don't react to any register writes unless the pipe currently attached to them is running, so it's impossible to move them to the other pipe unless both pipes are running. Also it's documented that the DPLL must be enabled on both pipes whenever it's needed. This reverts commit ac6696d3236bd61503f89a1a99680fd7894d5d53. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Check pixel clock in ns2501 mode_valid hookVille Syrjälä1-3/+3
The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes, 60Hz and 56Hz. The magic register values we have correspond to the 60Hz mode, and as I don't know how one would trick the VGA BIOS to set up the 56Hz mode we can't get the magic values for the orther mode. So when checking whether a mode is valid also check the pixel clock so that we filter out the 56Hz variant. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Init important ns2501 registersVille Syrjälä1-0/+10
In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Looks like IEGD does a one time init of these three registers. We don't have a good one time init place in the ns2501 driver, so let's just stick them into the .mode_set() hook and see if that helps things along. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Rewrite ns2501 driver a bitVille Syrjälä1-204/+325
Try to use the same programming sequence as used by the IEGD driver. Also shovel the magic register values into a big static const array. The register values are actually the based on what the BIOS programs on the Fujitsu-Siemens Lifebook S6010. IEGD seemed to have hardcoded register values (which also enabled the scaler for 1024x768 mode). However those didn't actually work so well on the S6010. Possibly the pipe timings that got used didn't match the ns2501 configuration. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Kill useless ns2501_dump_regsVille Syrjälä1-17/+0
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't call DVO mode_set hook on DPMS changesVille Syrjälä1-4/+0
Calling the mode_set hook on DPMS changes doesn't seem to be necessary for ns2501. Just drop it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Enable DVO between mode_set and dpms hooksVille Syrjälä1-2/+3
To more closely match the IEGD ns2501 driver behaviour, call the mode_set hook while the DVO port is still disabled, then enable the DVO port, and finally call the dpms hook. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: ns2501 is on DVOBVille Syrjälä1-1/+1
On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead of DVOC. FIXME: Maybe need to dig out the correct DVO port from VBT Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Disable double wide even when leaving the pipe onVille Syrjälä1-6/+14
Disable double wide even if the pipe quirk compels us to leave the pipe running. Double wide has certain implications for the plane assignments so best keep it off. Also helps resuming from S3 on the Fujitsu-Siemens Lifebook S6010 when double wide was enabled prior to suspend. We do leave the pixel clock ticking at the original rate which would require double wide to be enabled. But since the planes are all disabled I'm hoping that the overly fast clock won't cause any problems. Seems to be fine so far. v2: Disable double wide also when turning the pipe off v3: Reorder wrt. force pipe B quirk Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()Ville Syrjälä2-21/+17
Just pass the intel_crtc around instead of dev_priv+pipe. Also make intel_wait_for_pipe_off() static since it's only used in intel_display.c. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Idle unused rings on gen2/3 during init/resumeVille Syrjälä2-0/+42
gen2/3 platforms have a boatload of rings we're not using. On my 830 the BIOS/hw can leave some of those "active" after resume which will prevent c3 entry. The ring is apparently considered active whenever head != tail even if the ring is disabled. Disable and clear all such unused ringbuffers on init/resume. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Disable trickle feed for gen2/3Ville Syrjälä2-0/+14
My 830 is unhappy with trickle feed enabled. The symptom is that the image on the screen shifts a bit to right occasionally. The BIOS initially disables trickle feed, but it gets reset during suspend, so we need to re-disable it ourselves. Juse disable it always. Also disable it for all other gen2/3 platforms since we disable it for all more recent platforms as well (until HSW that is). At least my 855 doesn't seem to mind us doing this. I don't have gen3 hardware to test that. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Fix gen2 planes B and C max watermark valueVille Syrjälä1-4/+20
The max watermark value for gen2 planes B and C is 0x1f, instead of the 0x3f that plane A uses. Also check against the max even if the pipe is disabled since the FIFO size exceeds the plane B and C max watermark value. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: make fbdev initialization asynchronous v2Jesse Barnes3-5/+9
This gets us out of our init code and out to userspace quite a bit faster, but does open us up to some bugs given the state of our init time locking. v2: switch to async_schedule (Chris) check with lockdep, seems happy (Jesse) move hotplug enable flag set to fbdev_initial_config (Jesse) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Rebase on top of the dev_priv->enable_hotplug_processing removal.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Init some CHV workarounds via LRIs in ring->init_context()Ville Syrjälä2-16/+44
Follow the BDW example and apply the workarounds touching registers which are saved in the context image through LRIs in the new ring->init_context() hook. This makes Mesa much happier and eg. glxgears doesn't hang after the first frame. Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Add missing wa table initialization to avoid a functional conflict with Arun's wa table debugfs support.] Reviewed-by: "Barbalho, Rafael" <rafael.barbalho@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: trivial: remove unneed set to NULLGustavo Padovan1-1/+0
At this point of the code the obj var is already NULL, so we don't need to set it again to NULL. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Warn about odd rps values on CHVVille Syrjälä1-0/+11
CHV wants even rps opcodes so print a warning of the min/max/rpe/rp1 values are odd, and warn if an odd value slips through to valleyview_set_rps() and truncate it to an even value. Also add a comment to chv_freq_opcode() to make sure no one changes the code without considering this requirement. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> [danvet: Help git along in applying the patch, somehow it silently ended up in the vlv init_gt_powersave function.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03MAINTAINERS: Update Daniel Vetter's email addressDaniel Vetter1-1/+1
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2014-09-03drm/i915/bdw: Render state init for ExeclistsOscar Mateo6-39/+135
The batchbuffer that sets the render context state is submitted in a different way, and from different places. We needed to make both the render state preparation and free functions outside accesible, and namespace accordingly. This mess is so that all LR, LRC and Execlists functionality can go together in intel_lrc.c: we can fix all of this later on, once the interfaces are clear. v2: Create a separate ctx->rcs_initialized for the Execlists case, as suggested by Chris Wilson. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> v3: Setup ring status page in lr_context_deferred_create when the default context is being created. This means that the render state init for the default context is no longer a special case. Execute deferred creation of the default context at the end of logical_ring_init to allow the render state commands to be submitted. Fix style errors reported by checkpatch. Rebased. Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: BDW Software TurboDaisy Sun5-39/+241
BDW supports GT C0 residency reporting in constant time unit. Driver calculates GT utilization based on C0 residency and adjusts RP frequency up/down accordingly. For offscreen workload specificly, set frequency to RP0. Offscreen task is not restricted by frame rate, it can be executed as soon as possible. Transcoding and serilized workload between CPU and GPU both need high GT performance, RP0 is a good option in this case. RC6 will kick in to compensate power consumption when GT is not active. v2: Rebase on recent drm-intel-nightly v3: Add flip timerout monitor, when no flip is deteced within 100ms, set frequency to RP0. Signed-off-by: Daisy Sun <daisy.sun@intel.com> [torourke: rebased on latest and resolved conflict] Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Populate mem_freq in init_gt_powerwave()Ville Syrjälä2-53/+43
init_clock_gating() is too late to read out the mem_freq. We already want to print out the GPU MHz numbers before it's called. Move the mem_freq setup to init_gt_powersave(). v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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