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2019-12-27arm64: dts: qcom: db820c: Use regulator names from schematicsBjorn Andersson1-70/+143
Update the regulator names in db820c.dtsi to use the names from the schematics, instead of the made up genric names. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsiBjorn Andersson1-1434/+1430
Sort all the nodes by unit address, then name. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: msm8996: Pad addressesBjorn Andersson1-72/+72
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it easier to ensure ordering when adding new nodes. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: db820c: Remove pin specific filesBjorn Andersson3-203/+190
Rather than scattering pinctrl definitions in various files, merge the nodes into db820c.dtsi to make it easier to navigate. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: db820c: Sort all nodesBjorn Andersson1-168/+168
Sort all nodes in db820c.dtsi based on address, then name. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: db820c: Group root nodesBjorn Andersson1-49/+45
Prior refactoring have left a few root nodes scattered throughout db820c.dtsi, group these at the top of the file. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: msm8996: Move regulators to db820cBjorn Andersson2-205/+156
As the definition of available PMICs and the names of their outputs are board specifc move this to db820c.dtsi Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: msm8996: Move regulator consumers to db820cBjorn Andersson2-44/+44
Supplies for the various components in the SoC depends on board layout, so move the supply definitions to db820c.dtsi instead of carrying them in the platform dtsi. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: msm8996: Use node references in db820cBjorn Andersson2-354/+341
Instead of mimicing the structure of the platform, reference nodes by their label in apq8096-db820c.dtsi. Add labels in msm8996.dtsi where necessary. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27arm64: dts: qcom: db820c: Move non-soc entries out of /socBjorn Andersson1-29/+29
The USB id pins and wlan regulator are not platform devices, so move them out of /soc Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-22arm64: dts: qcom: db845c: Enable ath10k 8bit host-cap quirkBjorn Andersson1-0/+2
The WiFi firmware used on db845c implements the 8bit host-capability message, so enable the quirk for this. Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191113232245.4039932-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-21arm64: dts: qcom: sdm845: Rename gic-its node to msi-controllerDouglas Anderson1-1/+1
This is just like commit ac00546a6780 ("arm64: dts: qcom: sc7180: Rename gic-its node to msi-controller") but for sdm845. This fixes all arm64/qcom device trees that I could find. Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191216222021.1.I684f124a05a1c3f0b113c8d06d5f9da5d69b801e@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-20arm64: dts: qcom: msm8998: Add ADSP, MPSS and SLPI nodesSibi Sankar2-0/+132
This patch adds ADSP, MPSS and SLPI nodes for MSM8998 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191218132217.28141-6-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-20arm64: dts: qcom: msm8998: Update reserved memory mapSibi Sankar1-11/+59
Update existing and add missing regions to the reserved memory map, as described in version 7.1 Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191218132217.28141-5-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-20arm64: dts: qcom: sc7180: Add remoteproc enablersSibi Sankar1-0/+126
Add scm, smem, smp2p, aoss-qmp, aoss-cc and pdc-global device nodes to SC7180 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191218143332.29107-1-sibis@codeaurora.org [bjorn: Updated subject] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-20arm64: dts: qcom: sm8150: Add cpufreq HW device nodeSibi Sankar1-0/+21
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8150 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191219120633.20723-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-20arm64: dts: qcom: qcs404: Update the compatible for watchdog timerSai Prakash Ranjan1-1/+1
Update the compatible for QCS404 watchdog timer with proper SoC specific compatible. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/757995875cc12d3f5a8f5fd5659b04653950970a.1576211720.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-18arm64: dts: qcom: sc7180: Fix I2C/UART numbers 2, 4, 7, and 9Douglas Anderson1-8/+8
Commit f4a73f5e2633 ("pinctrl: qcom: sc7180: Add new qup functions") has landed which means that we absolutely need to use the proper names for the pinmuxing for I2C/UART numbers 2, 4, 7, and 9. Let's do it. For reference: - If you get only one of this commit and the pinctrl commit then none of I2C/UART 2, 4, 7, and 9 will work. - If you get neither of these commits then I2C 2, 4, 7, and 9 will work but not UART. ...but despite the above it should be fine for this commit to land in the Qualcomm tree because sc7180.dtsi only exists there (it hasn't made it to mainline). Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191217130352.1.Id8562de45e8441cac34699047e25e7424281e9d4@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-18arm64: dts: msm8998-clamshell: Add pm8005_s1 regulatorJeffrey Hugo1-0/+17
The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU. This should be hooked up to the GPU CPR, but we don't have support for that yet, so until then, just turn on the regulator and keep it on so that we can focus on basic GPU bringup. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191217170249.5280-1-jeffrey.l.hugo@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-18arm64: dts: qcom: sc7180: Add wakeup parent for TLMMMaulik Shah1-0/+1
Specify wakeup parent irqchip for sc7180 TLMM. Reviewed-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: devicetree@vger.kernel.org Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1572419178-5750-3-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-18arm64: dts: qcom: sm8150: Add ADSP, CDSP, MPSS and SLPI remoteprocsSibi Sankar2-0/+150
Add ADSP, CDSP, MPSS and SLPI device tree nodes for SM8150 SoC. Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191217092503.10699-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-18arm64: dts: qcom: sc7180: Fix node orderMatthias Kaehlcke1-37/+37
The SC7180 device tree nodes should be ordered by address. Re-shuffle some nodes which currently don't follow this convention. Since we are already moving it add a missing leading zero to the address in the 'reg' property of the 'interrupt-controller@b220000' node. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191212170824.v2.1.I55198466344789267ed1eb5ec555fd890c9fc6e1@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-18arm64: dts: qcom: msm8998: Fixup uart3 gpio config for bluetoothJeffrey Hugo3-4/+67
It turns out that the wcn3990 can float the gpio lines during bootup, etc which will result in the uart core thinking there is incoming data. This results in the bluetooth stack getting garbage. By applying a bias to match what wcn3990 would drive, the issue is corrected. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191021161921.31825-1-jeffrey.l.hugo@gmail.com [bjorn: Moved board specific pinctrl states to the end] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-17arm64: dts: qcom: sdm845-cheza: Add cr50 spi nodeStephen Boyd1-0/+14
Add the cr50 device to the spi controller it is attached to. This enables /dev/tpm0 and some login things on Cheza. Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20191216234204.190769-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-17arm64: dts: qcom: sm8150: Add ADSP, CDSP, MPSS and SLPI smp2pSibi Sankar1-0/+96
Add the SMP2P nodes for the remoteproc states for ADSP, CDSP, MPSS and SLPI remoteprocs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/0101016e80793dfa-9d0f6e93-01db-4c95-a226-d64bb50238cb-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-13arm64: dts: qcom: sc7180: Avoid "phy" for USB QMP PHY wrapperDouglas Anderson1-2/+2
The bindings for the QMP PHY are truly strange. I believe (?) that they may have originated because with PCIe each lane is treated as a different PHY and the same PHY driver is used for a whole bunch of things (incluidng PCIe). In any case, now that we have "make dtbs_check", we find that having the outer node named "phy" triggers the "schemas/phy/phy-provider.yaml" schema, yelling about: phy@88e9000: '#phy-cells' is a required property Let's call the outer node the "phy-wrapper" and the inner node the "phy" to make dtbs_check happy. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 0b766e7fe5a2 ("arm64: dts: qcom: sc7180: Add USB related nodes") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191212113540.6.Iec10b23bb000186b36b8bacfb6789d8233de04a7@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-13arm64: dts: qcom: pm6150: Remove macro from unit name of adc-chanDouglas Anderson1-1/+1
This is just like commit e77cc85ee390 ("arm64: dts: qcom: sdm845: remove macro from unit name"). It fixes the error in 'make dtbs_check': arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: adc@3100: 'adc-chan@0x06' does not match any of the regexes: ... Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: a727ec1232d9 ("arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191212113540.4.I5f67a5ed7665f658c95447a837cbd0021e1dc689@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-13arm64: dts: qcom: sc7180: Add "#clock-cells" property to usb_1_ssphyDouglas Anderson1-0/+1
Running "dtbs_check" yells: '#clock-cells' is a dependency of 'clock-output-names' ...and sure enough the bindings say we should have "#clock-cells". Add it. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 0b766e7fe5a2 ("arm64: dts: qcom: sc7180: Add USB related nodes") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191212113540.3.Ia530e4065ca81f55ac8f89a400f6a0a084ff6712@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-13arm64: dts: qcom: sc7180: Rename gic-its node to msi-controllerDouglas Anderson1-1/+1
Running `make dtbs_check` yells: arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: interrupt-controller@17a00000: gic-its@17a40000: False schema From "arm,gic-v3.yaml" we can grok that this is explained by the comment "msi-controller is preferred". Switch to the preferred name so that dtbs_check stops yelling. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 90db71e48070 ("arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191212113540.2.Ibad7d3b0bea02957e89047942c61cc6c0aa61715@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-13arm64: dts: qcom: sc7180: Add SoC name to compatibleDouglas Anderson1-1/+1
Running `make dtbs_check` yells because qcom.yaml says that we should have: - items: - enum: - qcom,sc7180-idp - const: qcom,sc7180 ...but we're missing "qcom,sc7180". Add it. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 90db71e48070 ("arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191212113540.1.I158061c65974bf0f653ceb79b442b76a1fd64868@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-12arm64: dts: sm8150: Add rpmh power-domain nodeSibi Sankar1-0/+55
Add the DT node for the rpmhpd power controller. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/0101016e7f99eab9-35efa01f-8ed3-4a77-87e1-09c381173121-000000@us-west-2.amazonses.com [bjorn: Use constant for opp6, until include lands] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-12arm64: dts: sc7180: Add aliases for all i2c and spi devicesRajendra Nayak1-0/+23
Add aliases for all i2c and spi nodes Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/0101016ef3cded0a-f85e1f98-f3be-4f6f-805f-82f8b6a83e14-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-12arm64: dts: sc7180: Remove additional spi chip select muxesRajendra Nayak1-6/+3
remove the additional CS muxes that were added by default for spi so every board using sc7180 does not have to override it. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/0101016ef3cdad4a-cbfbc482-1f74-4cb7-88fc-b4b6ed7e7543-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-12arm: dts: qcom: db410c: Enable USB OTG supportLoic Poulain2-5/+25
The Dragonboard-410c is able to act either as USB Host or Device. The role can be determined at runtime via the USB_HS_ID pin which is derived from the micro-usb port VBUS pin. In Host role, SoC USB D+/D- are routed to the onboard USB 2.0 HUB. In Device role, SoC USB D+/D- are routed to the USB 2.0 micro B port. Routing is selected via USB_SW_SEL_PM gpio. In device role USB HUB can be held in reset. chipidea driver expects two extcon device pointers, one for the EXTCON_USB event and one for the EXTCON_USB_HOST event. Since the extcon-usb-gpio device is capable of generating both these events, point two times to this extcon device. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1576083014-5842-1-git-send-email-loic.poulain@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-12arm64: dts: qcom: pm8916: Add vibration motor nodeStephan Gerhold1-0/+6
PM8916 has one vibration motor driver that is already supported by the pm8xxx-vibrator driver. Add a node describing it to pm8916.dtsi. Keep it disabled by default since not all devices make use of it. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191211192906.56638-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: sc7180: Add USB related nodesSandeep Maheswaram2-0/+130
Add nodes for DWC3 USB controller, QMP and QUSB PHYs. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1573795421-13989-2-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: sc7180: Add device node support for TSENS in SC7180Rajeshwari1-0/+527
Add TSENS node and user thermal zone for TSENS sensors in SC7180. Signed-off-by: Rajeshwari <rkambl@codeaurora.org> Link: https://lore.kernel.org/r/1574934847-30372-2-git-send-email-rkambl@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: msm8998: Add gpucc nodeJeffrey Hugo1-0/+14
Add MSM8998 GPU Clock Controller DT node. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191031185806.15602-1-jeffrey.l.hugo@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: sm8150-mtp: Enable UFS nodesVinod Koul1-0/+20
Enable the UFS HC and phy nodes and add regulators used by these. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20191106084656.1749954-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: sm8150: Add ufs nodesVinod Koul1-0/+68
Add the ufs hc node and ufs phy nodes found in SM8150 Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20191106084656.1749954-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: Use gcc clock enumsVinod Koul1-3/+4
Now that header defining gcc clocks is upstream, use the enums instead of numbers Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20191106084604.1746544-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: sc7180: Add cpufreq HW node for cpu scalingTaniya Das1-0/+19
cpufreq hw node required to scale CPU frequency on sc7180. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/0101016ed02b6356-5165eaaa-6c54-47ff-a008-821c91831e56-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: msm8996: Disable USB2 PHY suspend by coreManu Gautam1-0/+4
QUSB2 PHY on msm8996 doesn't work well when autosuspend by dwc3 core using USB2PHYCFG register is enabled. One of the issue seen is that PHY driver reports PLL lock failure and fails phy_init() if dwc3 core has USB2 PHY suspend enabled. Fix this by using quirks to disable USB2 PHY LPM/suspend and dwc3 core already takes care of explicitly suspending PHY during suspend if quirks are specified. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Paolo Pisati <p.pisati@gmail.com> Link: https://lore.kernel.org/r/20191209151501.26993-1-p.pisati@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: sc7180: Add Last level cache controller nodeSai Prakash Ranjan1-0/+7
Add device tree node for LLCC aka system cache controller for SC7180 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/0101016ef3394291-2290a8be-91c9-4d46-b5ca-acd5277eb6e2-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: sm8150: Add APSS watchdog nodeSai Prakash Ranjan1-0/+6
Add APSS (Application Processor Subsystem) watchdog DT node for SM8150 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/0101016ef3393092-487ddf4a-2e17-40f0-8161-3e686a7b57dc-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: qcom: sc7180: Add APSS watchdog nodeSai Prakash Ranjan1-0/+6
Add APSS (Application Processor Subsystem) watchdog DT node for SC7180 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/0101016ef3391ce3-438cca2f-458c-47d9-a62a-381f1c6bfb15-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: sdm845: Update the device tree node for LLCCSai Prakash Ranjan1-1/+1
LLCC cache-controller was renamed to system-cache-controller to make schema pass the dt binding check. Update the device tree node to reflect this change. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/a2bb92de65e90768bf1d6b8c0b7fbd43cba704d2.1573814758.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: sc7180: Add a comment to i2c7 about external pullupDouglas Anderson1-0/+2
Make i2c7 symmetric with the other i2c busses and comment that we have no internal pull because there is an external one. Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191210163530.2.I8d4cbb3d7ac5824f8e950c53038df8c27a512905@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: sc7180: Fix indentation/ordering of qspi nodes in sc7180-idpDouglas Anderson1-36/+37
The qspi pinctrl nodes had the wrong indentation and sort ordering and the main qspi node was placed down in the pinctrl section. Fix. Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191210163530.1.I69a6c29e08924229d160b651769c84508a07b3c6@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-11arm64: dts: msm8916: thermal: Add interrupt supportAmit Kucheria1-0/+2
Register upper-lower interrupt for the tsens controller. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/88eff964b708c8aff57b24370d2e14389ace09e9.1572526427.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-29 13:45:07 +0300