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2021-09-27[NOT-FOR-UPSTREAM] Add build instructionslinux_5.15_rc3_2021.10.01Emil Renner Berthing9-0/+464
For convenience this also adds a small beaglev_defconfig and the firmware needed for the brcmfmac driver along with the signed regulatory database. The firmware is from the linux-firmware repo and the regulatory database from the wireless-regdb Fedora package. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Drew Fustini <drew@beagleboard.org>
2021-09-27[NOT-FOR-UPSTREAM] riscv: Add starfive jh7100 starlight fedora defconfigTekkamanV1-0/+3161
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
2021-09-27riscv: dts: Add early A1 variant of the BeagleV Starlight boardEmil Renner Berthing2-1/+26
This is an early version of the BeagleV Starlight board that has GPIO63 wired up to tell the PMIC to reset the whole board rather than just the ethernet phy as it does on the later versions sent out as part of the BeagleV beta program. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27riscv: dts: Add JH7100 and BeagleV Starlight supportTekkamanV4-1/+1217
Based on the device tree in https://github.com/starfive-tech/u-boot/ with contributions from: yanhong.wang <yanhong.wang@starfivetech.com> Huan.Feng <huan.feng@starfivetech.com> ke.zhu <ke.zhu@starfivetech.com> yiming.li <yiming.li@starfivetech.com> jack.zhu <jack.zhu@starfivetech.com> Samin Guo <samin.guo@starfivetech.com> Chenjieqin <Jessica.Chen@starfivetech.com> bo.li <bo.li@starfivetech.com> Rearranged, cleanups, fixes, TPS65086, pins and resets added by Emil. Cleanups, fixes, LED and clocks added by Geert. Cleanups and GPIO fixes from Drew. Thermal zone added by Stephen. PWM pins added by Jianlong. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org> Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> riscv: dts: starfive: Set jh7100 crtc clocks and resets Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27RISC-V: Support non-coherent DMA operationsAtish Patra4-0/+79
** Do not upstream ** This is hacky fix just for testing. The actual patch would read the RISCV_UNCACHED_OFFSET from the DT for only the non-coherent devices. All other devices on beagleV and all other platform should just set dma_default_coherent to true. [Emil: remove spurious whitespace and fix format string warning] Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27spi: cadence-quadspi: Allow compilation on RISC-VEmil Renner Berthing1-1/+1
This IP is also used on the StarFive JH7100 riscv64 SoC and presumably also the upcoming JH7110 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27nvdla: Support compilation as moduleEmil Renner Berthing3-19/+21
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27nvdla: add NVDLA driverFarzad Farshchi33-0/+32586
Additional update from Prashant Gaikwad <pgaikwad@nvidia.com> Adapted for Linux 5.13 and the BeagleV Starlight board by <cybergaszcz@gmail.com>
2021-09-27[WIP] drm/starfive: Support DRM_FORMAT_XRGB8888Emil Renner Berthing2-0/+2
When creating dumb buffers with 32bpp and 24bit colour depth this is default mode return by drm_mode_legacy_fb_format. So we need to support this for common dumb buffers to just work. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27drm/starfive: Use actual clock rateEmil Renner Berthing1-1/+3
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27drm/starfive: Use reset apiEmil Renner Berthing4-35/+30
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27drm/starfive: Use clock apiEmil Renner Berthing4-13/+27
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27drm/starfive: crtc: Use devm_platform_ioremap_resource_bynameEmil Renner Berthing3-33/+9
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27drm/i2c/tda998x: Hardcode register values for Starlightsw.multimedia1-2/+5
A proper solution to this hack should be found. Signed-off-by: jack.zhu <jack.zhu@starfivetech.com> Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
2021-09-27drm/starfive: Add StarFive drm driversw.multimedia19-0/+3469
1. Add starfive DRM Display driver framework 2. Support M31 Phy and tda998x Signed-off-by: jack.zhu <jack.zhu@starfivetech.com> Signed-off-by: keith.zhao <keith.zhao@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27net: stmmac: use GFP_DMA32Matteo Croce1-4/+8
Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2021-09-27net: stmmac: Configure gtxclk based on speedTom1-0/+47
2021-09-27drivers/dma: dw-axi-dmac-starfive: Remove calls specific to ARM64 ACPIGeert Uytterhoeven1-18/+2
iort_dma_setup() is being removed by commit db59e1b6e49201be ("ACPI: arm64: Move DMA setup operations out of IORT") in iommu/next: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_async_ do_memcpy’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:152:2: error: implicit decl aration of function ‘iort_dma_setup’ [-Werror=implicit-function-declaration] 152 | iort_dma_setup(dma_dev, &dma_addr, &dma_size); | ^~~~~~~~~~~~~~ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:153:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 153 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_memcpy_raw’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:223:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 223 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ iort_dma_setup() and iort_iommu_configure_id() are part of the ARM64 ACPI implementation. As CONFIG_ACPI_IORT cannot be enabled on RISC-V, they were dummies anyway, so these calls can just be removed. [Emil: remove unused local variables too] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- Boot-tested, but the affected code paths were not exercised.
2021-09-27drivers/dma: Fix VIC7100 dw-axi-dmac-platform driver additionMichael Scott1-8/+11
Descriptor management was simplified with commit: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ef6fb2d6f1abd56cc067c694253ea362159b5ac3 Code added to dw-axi-dmac-platform driver due to VIC7100 Cache Coherency issues needed follow those changes. Signed-off-by: Michael Scott <mike@foundries.io>
2021-09-27drivers/dma: Add dw-axi-dmac-starfive driver for JH7100Tom8-20/+774
2021-09-27drivers/pwm/pwm-sifive-ptc: Clear PWM CNTRyiming.li1-0/+4
Clear CNTR of PWM after setting period & duty_cycle
2021-09-27drivers/pwm: Add SiFive PWM PTC driverChenjieqin3-0/+302
2021-09-27drivers/tty/serial/8250: update driver for JH7100Samin Guo1-0/+8
2021-09-27riscv: Add StarFive JH7100 supportTom1-0/+12
2021-09-27sifive/sifive_l2_cache: Align the address to cache lineAtish Patra1-0/+3
[Emil: fix suggested by Geert Uytterhoeven <geert@linux-m68k.org>] Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27sifive/sifive_l2_cache: Print a backtrace on out-of-range flushesGeert Uytterhoeven1-2/+2
This makes it easier to find out which driver passes a wrong address range. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-09-27sifive/sifive_l2_cache: Add disabling IRQ option (workaround)Tom3-0/+53
2021-09-27sifive/sifive_l2_cache: Add Starfive supportTom1-0/+1
2021-09-27sifive/sifive_l2_cache: Add sifive_l2_flush64_range functionTom3-1/+59
2021-09-27drivers/hw_random: Add StarFive JH7100 Random Number Generator driverHuan Feng4-0/+437
2021-09-27[WIP] dt-bindings: dma: dw-axi-dmac: Increase DMA channel limit to 16Geert Uytterhoeven1-3/+3
The first DMAC instance in the StarFive JH7100 SoC supports 16 DMA channels. FIXME Given there are more changes to the driver than just increasing DMAC_MAX_CHANNELS, we probably need a new compatible value, too. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-09-27hwmon: (sfctemp) Add StarFive JH7100 temperature sensorEmil Renner Berthing6-0/+416
Register definitions and conversion constants based on sfctemp driver by Samin in the StarFive 5.10 kernel. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2021-09-27dt-bindings: hwmon: add starfive,jh7100-temp bindingsEmil Renner Berthing1-0/+74
Add bindings for the temperature sensor on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Reviewed-by: Rob Herring <robh@kernel.org>
2021-09-27pinctrl: starfive: Reset pinmux settingsEmil Renner Berthing2-0/+72
Current u-boot doesn't seem to take into account that some GPIOs are configured as inputs/outputs of certain peripherals on power-up. This means it ends up configuring some GPIOs as inputs to more than one peripheral which the documentation explicitly says is illegal. Similarly it also ends up configuring more than one GPIO as output of the same peripheral. While not explicitly mentioned by the documentation this also seems like a bad idea. The easiest way to remedy this mess is to just disconnect all GPIOs from peripherals and have our pinmux configuration set everything up properly. This, however, means that we'd disconnect the serial console from its pins for a while, so add a device tree property to keep certain GPIOs from being reset. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27pinctrl: starfive: Add pinctrl driver for the JH7100 SoCEmil Renner Berthing5-0/+1716
This adds a combined pinctrl and gpio driver for the StarFive Ltd. JH7100 RISC-V SoC [1]. For each "GPIO" there are two registers for configuring the output and output enable signals, which may come from other peripherals, and controlling the GPIOs from software amounts to setting these signals to constant 0 or constant 1. In other words the same registers are used for both pinmuxing and controlling the GPIOs, which makes it easier to combine the pinctrl and gpio driver in one. The gpio code is adapted from the gpio driver in the vendor tree written by Huan Feng with cleanups and fixes by Drew and me. [1] https://github.com/starfive-tech/beaglev_doc Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Drew Fustini <drew@beagleboard.org>
2021-09-27dt-bindings: pinctrl: add starfive,jh7100-pinctrl bindingsEmil Renner Berthing1-0/+269
Add bindings for the pin controller on the StarFive JH7100 SoC [1]. [1] https://github.com/starfive-tech/beaglev_doc Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27reset: jh7100: add StarFive JH7100 reset driverEmil Renner Berthing4-0/+177
This adds a reset controller driver for the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27dt-bindings: reset: add starfive,jh7100-reset bindingsEmil Renner Berthing1-0/+38
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-09-27[WIP] clk: starfive: Add preliminary JH7100 Clock Generator DriverGeert Uytterhoeven5-0/+719
Add a preliminary driver for the StarFive JH7100 Clock Generator. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-09-27[WIP] dt-bindings: clock: starfive: Add preliminary JH7100 bindingsGeert Uytterhoeven1-0/+54
Add preliminary Device Tree bindings for the StarFive JH7100 Clock Generator. To be verified against documentation when it becomes available. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-09-27[WIP] dt-bindings: reset: starfive: Add JH7100 Reset DefinitionsGeert Uytterhoeven1-0/+126
Add all resets for the StarFive JH7100 Reset Controller. Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added to all definitions. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-09-27[WIP] dt-bindings: clock: starfive: Add JH7100 Clock DefinitionsGeert Uytterhoeven1-0/+202
Add all clock outputs for the StarFive JH7100 Clock Generator. Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added to all definitions. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-09-27riscv: Flush current cpu icache before other cpusAlexandre Ghiti1-0/+2
On SiFive Unmatched, I recently fell onto the following BUG when booting: [ 0.000000] ftrace: allocating 36610 entries in 144 pages [ 0.000000] Oops - illegal instruction [#1] [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.13.1+ #5 [ 0.000000] Hardware name: SiFive HiFive Unmatched A00 (DT) [ 0.000000] epc : riscv_cpuid_to_hartid_mask+0x6/0xae [ 0.000000] ra : __sbi_rfence_v02+0xc8/0x10a [ 0.000000] epc : ffffffff80007240 ra : ffffffff80009964 sp : ffffffff81803e10 [ 0.000000] gp : ffffffff81a1ea70 tp : ffffffff8180f500 t0 : ffffffe07fe30000 [ 0.000000] t1 : 0000000000000004 t2 : 0000000000000000 s0 : ffffffff81803e60 [ 0.000000] s1 : 0000000000000000 a0 : ffffffff81a22238 a1 : ffffffff81803e10 [ 0.000000] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 [ 0.000000] a5 : 0000000000000000 a6 : ffffffff8000989c a7 : 0000000052464e43 [ 0.000000] s2 : ffffffff81a220c8 s3 : 0000000000000000 s4 : 0000000000000000 [ 0.000000] s5 : 0000000000000000 s6 : 0000000200000100 s7 : 0000000000000001 [ 0.000000] s8 : ffffffe07fe04040 s9 : ffffffff81a22c80 s10: 0000000000001000 [ 0.000000] s11: 0000000000000004 t3 : 0000000000000001 t4 : 0000000000000008 [ 0.000000] t5 : ffffffcf04000808 t6 : ffffffe3ffddf188 [ 0.000000] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000002 [ 0.000000] [<ffffffff80007240>] riscv_cpuid_to_hartid_mask+0x6/0xae [ 0.000000] [<ffffffff80009474>] sbi_remote_fence_i+0x1e/0x26 [ 0.000000] [<ffffffff8000b8f4>] flush_icache_all+0x12/0x1a [ 0.000000] [<ffffffff8000666c>] patch_text_nosync+0x26/0x32 [ 0.000000] [<ffffffff8000884e>] ftrace_init_nop+0x52/0x8c [ 0.000000] [<ffffffff800f051e>] ftrace_process_locs.isra.0+0x29c/0x360 [ 0.000000] [<ffffffff80a0e3c6>] ftrace_init+0x80/0x130 [ 0.000000] [<ffffffff80a00f8c>] start_kernel+0x5c4/0x8f6 [ 0.000000] ---[ end trace f67eb9af4d8d492b ]--- [ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- While ftrace is looping over a list of addresses to patch, it always failed when patching the same function: riscv_cpuid_to_hartid_mask. Looking at the backtrace, the illegal instruction is encountered in this same function. However, patch_text_nosync, after patching the instructions, calls flush_icache_range. But looking at what happens in this function: flush_icache_range -> flush_icache_all -> sbi_remote_fence_i -> __sbi_rfence_v02 -> riscv_cpuid_to_hartid_mask The icache and dcache of the current cpu are never synchronized between the patching of riscv_cpuid_to_hartid_mask and calling this same function. So fix this by flushing the current cpu's icache before asking for the other cpus to do the same. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
2021-09-27riscv: optimized memsetMatteo Croce6-135/+44
The generic memset is defined as a byte at time write. This is always safe, but it's slower than a 4 byte or even 8 byte write. Write a generic memset which fills the data one byte at time until the destination is aligned, then fills using the largest size allowed, and finally fills the remaining data one byte at time. Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2021-09-27riscv: optimized memmoveMatteo Croce5-70/+26
When the destination buffer is before the source one, or when the buffers doesn't overlap, it's safe to use memcpy() instead, which is optimized to use a bigger data size possible. Signed-off-by: Matteo Croce <mcroce@microsoft.com> Reported-by: kernel test robot <lkp@intel.com>
2021-09-27riscv: optimized memcpyMatteo Croce5-113/+97
Write a C version of memcpy() which uses the biggest data size allowed, without generating unaligned accesses. The procedure is made of three steps: First copy data one byte at time until the destination buffer is aligned to a long boundary. Then copy the data one long at time shifting the current and the next u8 to compose a long at every cycle. Finally, copy the remainder one byte at time. On a BeagleV, the TCP RX throughput increased by 45%: before: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44840 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 76.4 MBytes 641 Mbits/sec 27 624 KBytes [ 5] 1.00-2.00 sec 72.5 MBytes 608 Mbits/sec 0 708 KBytes [ 5] 2.00-3.00 sec 73.8 MBytes 619 Mbits/sec 10 451 KBytes [ 5] 3.00-4.00 sec 72.5 MBytes 608 Mbits/sec 0 564 KBytes [ 5] 4.00-5.00 sec 73.8 MBytes 619 Mbits/sec 0 658 KBytes [ 5] 5.00-6.00 sec 73.8 MBytes 619 Mbits/sec 14 522 KBytes [ 5] 6.00-7.00 sec 73.8 MBytes 619 Mbits/sec 0 621 KBytes [ 5] 7.00-8.00 sec 72.5 MBytes 608 Mbits/sec 0 706 KBytes [ 5] 8.00-9.00 sec 73.8 MBytes 619 Mbits/sec 20 580 KBytes [ 5] 9.00-10.00 sec 73.8 MBytes 619 Mbits/sec 0 672 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 736 MBytes 618 Mbits/sec 71 sender [ 5] 0.00-10.01 sec 733 MBytes 615 Mbits/sec receiver after: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44864 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 109 MBytes 912 Mbits/sec 48 559 KBytes [ 5] 1.00-2.00 sec 108 MBytes 902 Mbits/sec 0 690 KBytes [ 5] 2.00-3.00 sec 106 MBytes 891 Mbits/sec 36 396 KBytes [ 5] 3.00-4.00 sec 108 MBytes 902 Mbits/sec 0 567 KBytes [ 5] 4.00-5.00 sec 106 MBytes 891 Mbits/sec 0 699 KBytes [ 5] 5.00-6.00 sec 106 MBytes 891 Mbits/sec 32 414 KBytes [ 5] 6.00-7.00 sec 106 MBytes 891 Mbits/sec 0 583 KBytes [ 5] 7.00-8.00 sec 106 MBytes 891 Mbits/sec 0 708 KBytes [ 5] 8.00-9.00 sec 106 MBytes 891 Mbits/sec 28 433 KBytes [ 5] 9.00-10.00 sec 108 MBytes 902 Mbits/sec 0 591 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 1.04 GBytes 897 Mbits/sec 144 sender [ 5] 0.00-10.01 sec 1.04 GBytes 894 Mbits/sec receiver And the decreased CPU time of the memcpy() is observable with perf top. This is the `perf top -Ue task-clock` output when doing the test: before: Overhead Shared O Symbol 42.22% [kernel] [k] memcpy 35.00% [kernel] [k] __asm_copy_to_user 3.50% [kernel] [k] sifive_l2_flush64_range 2.30% [kernel] [k] stmmac_napi_poll_rx 1.11% [kernel] [k] memset after: Overhead Shared O Symbol 45.69% [kernel] [k] __asm_copy_to_user 29.06% [kernel] [k] memcpy 4.09% [kernel] [k] sifive_l2_flush64_range 2.77% [kernel] [k] stmmac_napi_poll_rx 1.24% [kernel] [k] memset Signed-off-by: Matteo Croce <mcroce@microsoft.com> Reported-by: kernel test robot <lkp@intel.com>
2021-09-27riscv: add ARCH_DMA_MINALIGN supportXianting Tian1-0/+2
Introduce ARCH_DMA_MINALIGN to riscv arch. Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
2021-09-27Linux 5.15-rc3Linus Torvalds1-1/+1
2021-09-26Merge tag '5.15-rc2-ksmbd-fixes' of git://git.samba.org/ksmbdLinus Torvalds8-260/+164
Pull ksmbd fixes from Steve French: "Five fixes for the ksmbd kernel server, including three security fixes: - remove follow symlinks support - use LOOKUP_BENEATH to prevent out of share access - SMB3 compounding security fix - fix for returning the default streams correctly, fixing a bug when writing ppt or doc files from some clients - logging more clearly that ksmbd is experimental (at module load time)" * tag '5.15-rc2-ksmbd-fixes' of git://git.samba.org/ksmbd: ksmbd: use LOOKUP_BENEATH to prevent the out of share access ksmbd: remove follow symlinks support ksmbd: check protocol id in ksmbd_verify_smb_message() ksmbd: add default data stream name in FILE_STREAM_INFORMATION ksmbd: log that server is experimental at module load
2021-09-26Merge tag 'edac_urgent_for_v5.15_rc3' of ↵Linus Torvalds2-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras Pull EDAC fixes from Borislav Petkov: "Fix two EDAC drivers using the wrong value type for the DIMM mode" * tag 'edac_urgent_for_v5.15_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: EDAC/dmc520: Assign the proper type to dimm->edac_mode EDAC/synopsys: Fix wrong value type assignment for edac_mode
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-24 00:13:21 +0300