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2014-09-25Merge tag 'sunxi-drivers-for-3.18' of ↵Arnd Bergmann4-1/+473
git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/drivers Pull "Allwinner drivers additions for 3.18" from Maxime Ripard: Nothing major, just handling the RTC driver changes needed for the A31/A23. Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'sunxi-drivers-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc rtc: sun6i: Add sun6i RTC driver
2014-09-24drivers/soc: ti: fix build break with modulesOlof Johansson1-1/+1
Fixes below build break by not switching to stubs when the driver is a module: drivers/soc/ti/knav_dma.c:418:7: error: redefinition of 'knav_dma_open_channel' void *knav_dma_open_channel(struct device *dev, const char *name, ^ In file included from drivers/soc/ti/knav_dma.c:26:0: include/linux/soc/ti/knav_dma.h:165:21: note: previous definition of 'knav_dma_open_channel' was here static inline void *knav_dma_open_channel(struct device *dev, const char *name, ^ Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-24Merge tag 'drivers-soc-ti-v2' of ↵Olof Johansson14-0/+4265
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers Merge "soc: Keystone SOC Navigator drivers for 3.18" from Santosh Shilimkar: Keystone SOC Navigator drivers for 3.18 The Keystone Multi-core Navigator contains QMSS and packet DMA subsystems which interwork together to form the Navigator cloud used by various subsystems like NetCP, SRIO, SideBand Crypto engines etc. * tag 'drivers-soc-ti-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: MAINTAINERS: Add Keystone Multicore Navigator drivers entry soc: ti: add Keystone Navigator DMA support Documentation: dt: soc: add Keystone Navigator DMA bindings soc: ti: add Keystone Navigator QMSS driver Documentation: dt: soc: add Keystone Navigator QMSS bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-24MAINTAINERS: Add Keystone Multicore Navigator drivers entrySantosh Shilimkar1-0/+9
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-09-24soc: ti: add Keystone Navigator DMA supportSantosh Shilimkar4-0/+1001
The Keystone Navigator DMA driver sets up the dma channels and flows for the QMSS(Queue Manager SubSystem) who triggers the actual data movements across clients using destination queues. Every client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO Engines has its own instance of packet dma hardware. QMSS has also an internal packet DMA module which is used as an infrastructure DMA with zero copy. Initially this driver was proposed as DMA engine driver but since the hardware is not typical DMA engine and hence doesn't comply with typical DMA engine driver needs, that approach was naked. Link to that discussion - https://lkml.org/lkml/2014/3/18/340 As aligned, now we pair the Navigator DMA with its companion Navigator QMSS subsystem driver. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-09-24Documentation: dt: soc: add Keystone Navigator DMA bindingsSantosh Shilimkar1-0/+111
The Keystone Navigator DMA driver sets up the dma channels and flows for the QMSS(Queue Manager SubSystem) who triggers the actual data movements across clients using destination queues. Every client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO Engines has its own instance of packet dma hardware. QMSS has also an internal packet DMA module which is used as an infrastructure DMA with zero copy. Initially this driver was proposed as DMA engine driver but since the hardware is not typical DMA engine and hence doesn't comply with typical DMA engine driver needs, that approach was naked. Link to that discussion - https://lkml.org/lkml/2014/3/18/340 As aligned, now we pair the Navigator DMA with its companion Navigator QMSS subsystem driver. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-09-24soc: ti: add Keystone Navigator QMSS driverSandeep Nair9-0/+2912
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of the main hardware sub system which forms the backbone of the Keystone Multi-core Navigator. QMSS consist of queue managers, packed-data structure processors(PDSP), linking RAM, descriptor pools and infrastructure Packet DMA. The Queue Manager is a hardware module that is responsible for accelerating management of the packet queues. Packets are queued/de-queued by writing or reading descriptor address to a particular memory mapped location. The PDSPs perform QMSS related functions like accumulation, QoS, or event management. Linking RAM registers are used to link the descriptors which are stored in descriptor RAM. Descriptor RAM is configurable as internal or external memory. The QMSS driver manages the PDSP setups, linking RAM regions, queue pool management (allocation, push, pop and notify) and descriptor pool management. The specifics on the device tree bindings for QMSS can be found in: Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-09-24Documentation: dt: soc: add Keystone Navigator QMSS bindingsSandeep Nair1-0/+232
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of the main hardware sub system which forms the backbone of the Keystone Multi-core Navigator. QMSS consist of queue managers, packed-data structure processors(PDSP), linking RAM, descriptor pools and infrastructure Packet DMA. The Queue Manager is a hardware module that is responsible for accelerating management of the packet queues. Packets are queued/de-queued by writing or reading descriptor address to a particular memory mapped location. The PDSPs perform QMSS related functions like accumulation, QoS, or event management. Linking RAM registers are used to link the descriptors which are stored in descriptor RAM. Descriptor RAM is configurable as internal or external memory. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-09-24Merge tag 'mailbox-for-v3.18' of ↵Olof Johansson2-24/+240
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Mailbox related changes for omaps to get it to work with device tree. * tag 'mailbox-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: mailbox/omap: add support for parsing dt devices Documentation: dt: add omap mailbox bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-24Merge tag 'intc-for-v3.18' of ↵Olof Johansson386-2088/+3346
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Merge "omap intc changes for v3.18 merge window" from Tony Lindgren: Interrupt code related clean-up for omap2 and 3 to make it ready to move to drivers/irqchip. Note that this series does not yet move the interrupt code to drivers, that will be posted separately as a follow-up series. Note that this branch has a dependency to patches both in fixes-v3.18-not-urgent and soc-for-v3.18 and is based on a merge. Without doing the merge, off-idle would not work properly for git bisect. * tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (325 commits) arm: omap: intc: switch over to linear irq domain arm: omap: irq: get rid of ifdef hack arm: omap: irq: introduce omap_nr_pending arm: omap: irq: remove nr_irqs argument arm: omap: irq: remove unnecessary header arm: omap: irq: drop omap2_intc_handle_irq() arm: omap: irq: drop omap3_intc_handle_irq() arm: omap: irq: call set_handle_irq() from .init_irq arm: omap: irq: move some more code around arm: boot: dts: omap2/3/am33xx: drop ti,intc-size arm: omap: irq: drop ti,intc-size support arm: boot: dts: am33xx/omap3: fix intc compatible flag arm: omap: irq: use compatible flag to figure out number of IRQ lines arm: omap: irq: add specific compatibles for omap3 and am33xx devices arm: omap: irq: drop .handle_irq and .init_irq fields arm: omap: irq: use IRQCHIP_DECLARE macro arm: omap: irq: call set_handle_irq() from intc_of_init arm: omap: irq: make intc_of_init static arm: omap: irq: reorganize code a little bit arm: omap: irq: always define omap3 support ... Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-24Merge tag 'at91-drivers2' of git://github.com/at91linux/linux-at91 into ↵Olof Johansson32-339/+363
next/drivers Merge " Second drivers series for AT91/3.18" from Nicolas Ferre: - move of the PIT (basic timer) from mach-at91 to its proper location: drivers/clocksource - big cleanup of this driver along the way * tag 'at91-drivers2' of git://github.com/at91linux/linux-at91: ARM: at91: PIT: Move the driver to drivers/clocksource ARM: at91: Give the PIT irq as an argument of at91sam926x_pit_init ARM: at91: Convert the boards to the init_time callback ARM: at91: soc: Add init_time callback ARM: at91: PIT: (Almost) remove the global variables ARM: at91: PIT: use request_irq instead of setup_irq ARM: at91: PIT: Use pr_fmt ARM: at91: PIT: Use consistent exit path in probe ARM: at91: dt: Remove init_time definitions ARM: at91: PIT: Rework probe functions ARM: at91: PIT: Use of_have_populated_dt instead of CONFIG_OF ARM: at91: PIT: Use DIV_ROUND_CLOSEST to compute the cycles ARM: at91: generic.h: Add include safe guards ARM: at91: PIT: Follow the general coding rules Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-19rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtcChen-Yu Tsai1-1/+1
Now that we have Kconfig options for individual sunxi platforms, let the rtc-sunxi driver depend on the platforms that actually have this hardware, sun4i and sun7i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-19rtc: sun6i: Add sun6i RTC driverChen-Yu Tsai4-0/+472
This patch introduces the driver for the RTC in the Allwinner A31 and A23 SoCs. Unlike the RTC found in A10/A20 SoCs, which was part of the timer, the RTC in A31/A23 are a separate hardware block, which also contain a few controls for the RTC block hardware (a regulator and RTC block GPIO pin latches), while also having separate interrupts for the alarms. The hardware is different enough to make a different driver for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Varka Bhadram <varkabhadram@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-15ARM: at91: PIT: Move the driver to drivers/clocksourceMaxime Ripard5-7/+5
Now that we don't depend on anyting in the mach-at91 directory, we can just move the driver to where it belongs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Conflicts: arch/arm/mach-at91/Kconfig arch/arm/mach-at91/Makefile
2014-09-15ARM: at91: Give the PIT irq as an argument of at91sam926x_pit_initMaxime Ripard7-10/+8
This allows to remove the dependency of the timer driver on mach/hardware.h and having an hardcoded interrupt number in the driver itself. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-09-12arm: omap: intc: switch over to linear irq domainFelipe Balbi1-9/+79
now that we don't need to support legacy board-files, we can completely switch over to a linear irq domain and make use of irq_alloc_domain_generic_chips() to allocate all generic irq chips for us. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: get rid of ifdef hackFelipe Balbi1-15/+7
we don't need the ifdef if we have omap_nr_pending telling us how many pending registers we have on current platform. This solves a possible problem where we could try to handle bogus interrupts on OMAP2 and OMAP3 if using single zImage kernel, because we would end up reading the following pending FIQ register. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: introduce omap_nr_pendingFelipe Balbi1-1/+8
that variable will tell us how many INTC_PENDING_IRQn registers we have. It'll be used on a following patch to cleanup omap_intc_handle_irq() a bit. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove nr_irqs argumentFelipe Balbi1-12/+13
we can set our global omap_nr_irqs early on and drop the extra argument to omap_init_irq(). Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove unnecessary headerFelipe Balbi1-1/+0
There's no need for that header to be included. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop omap2_intc_handle_irq()Felipe Balbi2-11/+6
that was just a no-op wrapper around omap_intc_handle_irq anyway. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop omap3_intc_handle_irq()Felipe Balbi16-22/+0
now that we're calling set_handle_irq() from init_irq(), we can safely drop all callers to omap3_intc_handle_irq() and its definition. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: call set_handle_irq() from .init_irqFelipe Balbi1-0/+3
the idea is that board-files won't need to set .handle_irq on their machine_descs, which lets us drop a little more pointless code. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: move some more code aroundFelipe Balbi1-15/+15
We want .init_irq to call set_irq_handle() for legacy platforms. Note that this code will also be dropped once omap2/3 devices are completely moved to DT. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: boot: dts: omap2/3/am33xx: drop ti,intc-sizeFelipe Balbi3-3/+0
we are now infering number of IRQ lines based on correct compatible flag, which renders this binding completely useless. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop ti,intc-size supportFelipe Balbi1-3/+0
we don't need that anymore since specific devices are passing correct compatible flags. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: boot: dts: am33xx/omap3: fix intc compatible flagFelipe Balbi2-2/+2
that way, our intc driver can figure out how many IRQ lines INTC has. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: use compatible flag to figure out number of IRQ linesFelipe Balbi1-0/+3
so far, only am33xx has 128 lines, all other devices have only 96. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: add specific compatibles for omap3 and am33xx devicesFelipe Balbi1-1/+3
with this, we can use a compatible flag to figure out how many irq lines are wired up, no need for our TI-specific ti,intc-size binding. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop .handle_irq and .init_irq fieldsFelipe Balbi3-20/+0
now we can safely drop those fields from our machine_desc. While at that, also drop the now unused omap_intc_of_init() definition. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: use IRQCHIP_DECLARE macroFelipe Balbi1-5/+3
IRQCHIP_DECLARE macro is used to declare the same of_device_id structure for irqchips, it's just a helper. No functional changes. Note that we're temporarily including irqchip.h with its full path, until we move this driver to drivers/irqchip/. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: call set_handle_irq() from intc_of_initFelipe Balbi1-0/+2
this will let us drop .handle_irq and .init_irq fields from our generic machine_descs. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: make intc_of_init staticFelipe Balbi2-11/+1
nobody uses that function outside of this file, so we don't need to expose it. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: reorganize code a little bitFelipe Balbi1-67/+66
no functional changes, just moving code around. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: always define omap3 supportFelipe Balbi1-2/+0
remove ifdef around omap3 INTC support. This will make it easier to reuse code for PM. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: rename omap3_intc_regsFelipe Balbi1-2/+2
just to make it clearer that it can be used on all omaps. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove unnecessary base_addr argumentFelipe Balbi1-7/+3
omap_intc_handle_irq now had an unnecessary base_addr argument. Let's remove it and fix all callers. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: switch over to intc_readl on omap_intc_handle_irqFelipe Balbi1-6/+8
an almost blind conversion from readl_relaxed to our newly introduced intc_readl(). While at that, also remove some hardcoded register addresses. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove unused macroFelipe Balbi1-2/+0
no functional changes. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove rest of irq_banks usageFelipe Balbi1-81/+47
now we can finally remove the pointless irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: add a global omap_nr_irqs variableFelipe Balbi1-0/+3
this will cache number of irqs. Also in preparation for removal of irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: start to remove irq_banks arrayFelipe Balbi1-37/+27
We have a single bank in that array, this patch is in preparation to remove that array. It just shifts everything to a new set of functions for register IO while also removing old ones. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: define INTC_ILR0 registerFelipe Balbi1-0/+1
this is currently used as a hardcoded 0x100 offset. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: make omap_irq_base globalFelipe Balbi1-1/+1
This is in preparation for removing the pointless irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12Merge branch 'omap-for-v3.18/fixes-not-urgent' into omap-for-v3.18/intc-v2Tony Lindgren7-21/+21
2014-09-11ARM: OMAP2+: make of_device_ids constUwe Kleine-König7-9/+9
of_device_ids (i.e. compatible strings and the respective data) are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const function parameters and structs for OMAP2+ as const, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-11ARM: omap2: make arrays containing machine compatible strings constUwe Kleine-König1-12/+12
The definition static const char *omap3_boards_compat[] __initconst = { defines a changable array of constant strings. That is you must not do: *omap3_boards_compat[0] = 'f'; but omap3_boards_compat[0] = "another string"; is fine. So the annotation __initconst is wrong and yields a compiler error when other really const variables are added with __initconst. As the struct machine_desc member dt_compat is declared as const char *const *dt_compat; making the arrays const is the better alternative over changing all annotations to __initdata. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-11mailbox/omap: add support for parsing dt devicesSuman Anna1-24/+132
Logic has been added to the OMAP2+ mailbox code to parse the mailbox dt nodes and construct the different sub-mailboxes associated with the instance. The DT representation of the sub-mailbox devices is different from legacy platform data representation to allow flexibility of interrupt configuration between Tx and Rx fifos (to also possibly allow simplex devices in the future). The DT representation gathers similar information that was being passed previously through the platform data, except for the interrupt type information, which is gathered through driver compatible match data. The non-DT support has to be maintained for now to not break OMAP3 legacy boot, and the legacy-style code will be cleaned up once OMAP3 is also converted to DT-boot only. Cc: Jassi Brar <jassisinghbrar@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-11Documentation: dt: add omap mailbox bindingsSuman Anna1-0/+108
Add the device tree bindings document for OMAP2+ mailbox. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-09Merge tag 'socfpga_driver_for_v3.18' of ↵Arnd Bergmann4-0/+426
git://git.rocketboards.org/linux-socfpga-next into next/drivers Pull "SOCFPGA driver update for v3.18" from Dinh Nguyen: This is the EDAC driver for EDAC. Boris had given me permission to take this patch together with it's DTS component. The DTS portion was in the previous pull request. Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'socfpga_driver_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next: edac: altera: Add Altera SDRAM EDAC support
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