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2014-03-20mtd: st_spi_fsm: Add a check to if the chip can handle an SoC resetLee Jones1-0/+40
Based on information we can obtain though platform specific data and/or chip capabilities we are able to determine whether or not we can handle a SoC reset or not. To find out why this is important please read the comment provided in the patch. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Prepare read/write sequences according to configurationLee Jones1-0/+17
Firstly we search for our preference read/write configuration based on a given chip's capabilities. Then we actually set up the message sequence accordingly. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Provide the sequence for enabling 32bit addressing modeLee Jones1-0/+22
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for setting 32bit addressing mode on the Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Provide the erase one sector sequenceLee Jones1-0/+35
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for erasing a single sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Fetch boot-device from mode pinsLee Jones1-0/+46
It's important for us to determine which device was used to boot from in order to make some correct decisions surrounding Power Management. On each of the platforms which support the FSM this is communicated via a set of mode pins held in the system configuration area. This patch determine the boot device and stores the result. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Add device-tree binding documentationLee Jones1-0/+26
Cc: devicetree@vger.kernel.org Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Prepare the read/write FSM message sequence(s)Lee Jones1-0/+69
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare read/write FSM message sequence(s) based on chip capability and configuration. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Use device size to determine address widthLee Jones1-0/+4
Take some known parameters, namely size and number of sectors and use them to determine weather a device can support 32bit addressing or not. If it can, set the associated flash capability flag for latter use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Search for preferred FSM message sequence configurationsLee Jones1-0/+27
Here we provide a means to traverse though all supplied FSM message sequence configurations and pick one based on our chip's capabilities. The first one we match will be the preferred one, as they are presented in order of preference. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Dynamically setup flash device based on JEDEC IDLee Jones1-1/+25
Using previously added infrastructure we can now extract a device's JEDEC ID, compare it to a list of known and supported devices and make assumptions based on known characteristics of a given chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Provide device look-up tableLee Jones1-0/+136
Supply a lookup table of all the devices we intend to support. This table is used to store device information such as; a human readable device name, their JEDEC ID (plus the extended version), sector size and amount, a bit store of a device's capabilities, its maximum running frequency and possible use of a per-device configuration call-back. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: devices: Provide header for shared OPCODEs and SFDP commandsLee Jones2-0/+83
JEDEC have helped to standardise a great deal of the commands which can be issued to a Serial Flash devices. Many of the Serial Flash Discoverable Parameters (SFDP) commands are generic across devices. This patch provides a shared point where these commands can be defined. Suggested-by: Mark Brown <broonie@kernel.org> Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Add support for JEDEC ID extractionLee Jones1-0/+55
Once we start supporting devices it will be handy go detect them dynamically. This will be done using the chip's unique JEDEC ID. This patch allows us to extract a device's JEDEC ID using the a predefined FSM register write sequence. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply a method to read from the FSM's FIFOLee Jones1-0/+26
When invoked the driver will attempt to read any available data from the FSM's data register. Any data collected from this FIFO would have originated from the flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply framework for device requestsLee Jones1-0/+56
The FSM hardware works by setting a predetermined sequence of register writes. Rather than open coding them inside each functional block we're going to define them in a series of formatted 'sequence structures'. This patch provides the framework which shall be used for every action. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Initialise and configure the FSM for normal working conditionsLee Jones1-0/+127
This patch uses default values to initialise a connected flash chip. This includes; a device soft reset, setting of a safe working frequency, a switch into Fast Sequencing Mode, configuring of timing data and a purge of the FIFO. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply all register address and bit logic definesLee Jones1-0/+164
Here we provide the FSM's register addresses, register bit names/offsets and some commands which will prove useful as we start bulk the FMS's driver out with functionality. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Allocate resources and register with MTD frameworkLee Jones3-0/+115
This is a new driver. It's used to communicate with a special type of optimised Serial Flash Controller called the FSM. The FSM uses a subset of the SPI protocol to communicate with supported NOR-Flash devices. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: remove is_elm_present flagPekon Gupta1-3/+0
'is_elm_present' flag is not used anywhere. This check is implicitely taken care while selecting appropriate ecc-scheme via DT or board-file. Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.hwctl: clean omap_enable_hwecc_bch for redundant ECC ↵Pekon Gupta1-13/+10
configs This patch - refactors GPMC configurations based on ecc-scheme - removed dependency on is_elm_present() flag, which is implicitely taken care by selecting appropriate ecc-scheme Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.hwctl: refactor omap_enable_hwecc_bch for ECC related ↵Pekon Gupta1-24/+50
GPMC configs Lots of if..then..else conditions in omap_enable_hwecc_bch() can be avoided if code is refactored based on ecc-scheme. Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.hwctl: rename omap3_enable_hwecc_bch to ↵Pekon Gupta1-8/+7
omap_enable_hwecc_bch This patch - renames omap3_enable_hwecc_bch -> omap_enable_hwecc_bch to keep nomenclature independent of any device family. - using '__maybe_unused' instead of `ifdef based conditional compilation to suppress warning for un-used functions Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch8 in ↵Pekon Gupta1-49/+10
omap_calculate_ecc_bch merge omap3_calculate_ecc_bch8() into omap_calculate_ecc_bch() so that common callback can be used for both OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +---------------------+-------------------------------------------------------+ |ecc-scheme | nand_chip->calculate() after this patch | +---------------------+-------------------------------------------------------+ |HAM1_ECC | omap_calculate_ecc() | +---------------------+-------------------------------------------------------+ |BCH4_HW_DETECTION_SW | omap_calculate_ecc_bch() | |BCH4_HW | omap_calculate_ecc_bch() | |BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() -> omap_calculate_ecc_bch()| |BCH8_HW | omap_calculate_ecc_bch() | +---------------------+-------------------------------------------------------+ Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4 in ↵Pekon Gupta1-41/+10
omap_calculate_ecc_bch merges omap3_calculate_ecc_bch4() into omap_calculate_ecc_bch() so that common callback can be used for both OMAP_ECC_BCH4_CODE_HW and OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ecc-schemes +---------------------+-------------------------------------------------------+ |ecc-scheme | nand_chip->calculate() after this patch | +---------------------+-------------------------------------------------------+ |HAM1_ECC | omap_calculate_ecc() | +---------------------+-------------------------------------------------------+ |BCH4_HW_DETECTION_SW | omap3_calculate_ecc_bch4() -> omap_calculate_ecc_bch()| |BCH4_HW | omap_calculate_ecc_bch() | |BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() | |BCH8_HW | omap_calculate_ecc_bch() | +---------------------+-------------------------------------------------------+ Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: refactor omap_calculate_ecc_bch for BCHx_HW ↵Pekon Gupta1-33/+35
ecc-scheme OMAP NAND driver supports multiple flavours of BCH4 and BCH8 ECC algorithms. +------+------------------------------------+---------------+---------------+ | Algo | ECC scheme |ECC calculation|Error detection| +------+------------------------------------+---------------+---------------+ | |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | | BCH4 |OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) | +------+------------------------------------+---------------+---------------+ | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | | BCH8 |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | +------+------------------------------------+---------------+---------------+ This patch refactors omap_calculate_ecc_bch() so that - separate out ecc-scheme specific code so that common-code can be reused between different implementations of same ECC algorithm. - new ecc-schemes can be added with ease in future. Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: rename omap3_calculate_ecc_bch to ↵Pekon Gupta1-5/+5
omap_calculate_ecc_bch rename omap3_calculate_ecc_bch -> omap_calculate_ecc_bch to keep nomenclature independent of any device family. Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.correct: omap_elm_correct_data: fix programmed-page ↵Pekon Gupta1-10/+19
bit-flip correction logic This patch updates following checks when bit-flips are detected by ELM: - Do not evaluate bit-flips when un-correctable bit-flips is reported by ELM, because as per [1] when ELM reports an un-correctable bit-flips, 'number of error' field in its ELM_LOCATION_STATUS register is also invalid. - Return with error-code '-EBADMSG' on detection of un-correctable bit-flip. - Return with error-code '-EBADMSG' when bit-flips position is outside current Sector and OOB area. [1] ELM IP spec Table-25 ELM_LOCATION_STATUS Register. ELM_LOCATION_STATUS[8] = ECC_CORRECTABLE: Error location process exit status 0x0: ECC error location process failed. Number of errors and error locations are invalid. 0x1: all errors were successfully located. Number of errors and error locations are valid. Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.correct: omap_elm_correct_data: cleanup for future ↵Pekon Gupta1-25/+13
enhancements Current omap_elm_correct_data() code is not scalable for future ecc-schemes due to presence of tweaks and hard-coded macros for BCH4_ECC and BCH8_ECC ecc-schemes at multiple places. This patch: - replaces 'ecc_opt' with '(info->nand.ecc.strength == BCH8_MAX_ERROR) used to differentiate between BCH8_HW and BCH4_SW - replaces macros (defining magic number for specific ecc-scheme) with generic variables - removes dependency on macros defined in elm.h (like BCHx_ECC_OOB_BYTES) Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.correct: omap_elm_correct_data: fix erased-page ↵Pekon Gupta1-52/+33
detection for BCHx_HW ECC schemes As erased-pages do not have ECC stored in their OOB area, so they need to be seperated out from programmed-pages, before doing BCH ECC correction. In current implementation of omap_elm_correct_data() which does ECC correction for BCHx ECC schemes, this erased-pages are detected based on specific marker byte (reserved as 0x00) in ecc-layout. However, this approach has some limitation like; 1) All ecc-scheme layouts do not have such Reserved byte marker to differentiate between erased-page v/s programmed-page. Thus this is a customized solution. 2) Reserved marker byte can itself be subjected to bit-flips causing erased-page to be misunderstood as programmed-page. This patch removes dependency on any marker byte in ecc-layout, instead it compares calc_ecc[] with pattern of ECC-of-all(0xff). This implicitely means that both 'data + oob == all(0xff). Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.correct: omap_elm_correct_data: rename ambiguous ↵Pekon Gupta1-16/+23
variable 'eccsize' and 'ecc_vector_size' renaming following variables as they cause confusion due to resemblence to another similar field in 'struct nand_ecc_ctrl' (nand_chip->ecc.size). renaming: ecc_vector_size --> ecc->bytes (info->nand.ecc.bytes) renaming: eccsize --> actual_eccbytes (info->nand.ecc.bytes - 1) for BCH4 and BCH8 Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: add field to indicate current ecc-scheme in 'struct ↵Pekon Gupta1-1/+3
omap_nand_info' Information of currently selected ECC scheme 'enum omap_ecc ecc_opt' should available outside platform-data, so that single nand_chip->ecc callback can support multiple ecc-scheme configurations. Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: Fix the behavior of OTP write if there is not enough room for dataChristian Riesch3-7/+30
If a write to one time programmable memory (OTP) hits the end of this memory area, no more data can be written. The count variable in mtdchar_write() in drivers/mtd/mtdchar.c is not decreased anymore. We are trapped in the loop forever, mtdchar_write() will never return in this case. The desired behavior of a write in such a case is described in [1]: - Try to write as much data as possible, truncate the write to fit into the available memory and return the number of bytes that actually have been written. - If no data could be written at all, return -ENOSPC. This patch fixes the behavior of OTP write if there is not enough space for all data: 1) mtd_write_user_prot_reg() in drivers/mtd/mtdcore.c is modified to return -ENOSPC if no data could be written at all. 2) mtdchar_write() is modified to handle -ENOSPC correctly. Exit if a write returned -ENOSPC and yield the correct return value, either then number of bytes that could be written, or -ENOSPC, if no data could be written at all. Furthermore the patch harmonizes the behavior of the OTP memory write in drivers/mtd/devices/mtd_dataflash.c with the other implementations and the requirements from [1]. Instead of returning -EINVAL if the data does not fit into the OTP memory, we try to write as much data as possible/truncate the write. [1] http://pubs.opengroup.org/onlinepubs/9699919799/functions/write.html Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: block2mtd: check device sizeFabian Frederick1-1/+5
fixme applied : check device size is a multiple of erasesize. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECCHerve Codina1-0/+1
Crash detected on sam5d35 and its pmecc nand ecc controller. The problem was a call to chip->ecc.hwctl from nand_write_subpage_hwecc (nand_base.c) when we write a sub page. chip->ecc.hwctl function is not set when we are using PMECC controller. As a workaround, set NAND_NO_SUBPAGE_WRITE for PMECC controller in order to disable sub page access in nand_write_page. Signed-off-by: Herve Codina <Herve.CODINA@celad.com> Acked-by: Josh Wu <josh.wu@atmel.com> Cc: stable@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: gpmi: add subpage read supportHuang Shijie1-0/+96
1) Why add the subpage read support? The page size of the nand chip becomes larger and larger, the imx6 has to supports the 16K page or even bigger page. But sometimes, the upper layer only needs a small part of the page, such as 512 bytes or less. For example, ubiattach may only read 64 bytes per page. 2) We only enable the subpage read support when it meets the conditions: <1> the chip is imx6 (or later chips) which can supports large nand page. <2> the size of ECC parity is byte aligned. If the size of ECC parity is not byte aligned, the calling of NAND_CMD_RNDOUT will fail. 3) What does this patch do? This patch will fake a virtual small page for the subpage read, and call the gpmi_ecc_read_page() to do the real work. In order to fake a virtual small page, the patch changes the BCH registers and the bch_geometry{}. After the subpage read finished, we will restore them back. 4) Performace: 4.1) Tested with Toshiba TC58NVG2S0F(4096 + 224) with the following command: #ubiattach /dev/ubi_ctrl -m 4 The detail information of /dev/mtd4 shows below: -------------------------------------------------------------- #mtdinfo /dev/mtd4 mtd4 Name: test Type: nand Eraseblock size: 262144 bytes, 256.0 KiB Amount of eraseblocks: 1856 (486539264 bytes, 464.0 MiB) Minimum input/output unit size: 4096 bytes Sub-page size: 4096 bytes OOB size: 224 bytes Character device major/minor: 90:8 Bad blocks are allowed: true Device is writable: true -------------------------------------------------------------- 4.2) Before this patch: -------------------------------------------------------------- [ 94.530495] UBI: attaching mtd4 to ubi0 [ 98.928850] UBI: scanning is finished [ 98.953594] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0 [ 98.958562] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes [ 98.964076] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096 [ 98.969518] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192 [ 98.975128] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0 [ 98.979843] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128 [ 98.985878] UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 2024916145 [ 98.993635] UBI: available PEBs: 0, total reserved PEBs: 1856, PEBs reserved for bad PEB handling: 40 [ 99.001807] UBI: background thread "ubi_bgt0d" started, PID 831 -------------------------------------------------------------- The attach time is about 98.9 - 94.5 = 4.4s 4.3) After this patch: -------------------------------------------------------------- [ 286.464906] UBI: attaching mtd4 to ubi0 [ 289.186129] UBI: scanning is finished [ 289.211416] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0 [ 289.216360] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes [ 289.221858] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096 [ 289.227293] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192 [ 289.232878] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0 [ 289.237628] UBI: user volume: 0, internal volumes: 1, max. volumes count: 128 [ 289.243553] UBI: max/mean erase counter: 1/1, WL threshold: 4096, image sequence number: 2024916145 [ 289.251348] UBI: available PEBs: 1812, total reserved PEBs: 44, PEBs reserved for bad PEB handling: 40 [ 289.259417] UBI: background thread "ubi_bgt0d" started, PID 847 -------------------------------------------------------------- The attach time is about 289.18 - 286.46 = 2.7s 4.4) The conclusion: We achieve (4.4 - 2.7) / 4.4 = 38.6% faster in the ubiattach. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: gpmi: do not use the mtd->writesizeHuang Shijie1-3/+3
The nfc_geo->payload_size is equal to the mtd->writesize now, use the nfc_geo->payload_size to replace the mtd->writesize. This patch makes preparation for the gpmi's subpage read support. In the subpage support, the nfc_geo->payload_size maybe smaller then the mtd->writesize. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: nand: add "page" argument for read_subpage hookHuang Shijie2-3/+6
Add the "page" argument for the read_subpage hook. With this argument, the implementation of this hook could prints out more accurate information for debugging. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: nand: remove unused function input parameterCai Zhiyong1-7/+5
The nand_get_flash_type parameter "busw" input value is not used by any branch, and it is updated before use it in the function, so remove it, define the "busw" as an internal variable. Signed-off-by: Cai Zhiyong <caizhiyong@huawei.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: nand: pxa3xx: Print actual ECC strength in error messageEzequiel Garcia1-1/+1
The actual ECC strength used to select the ECC scheme is 'ecc_strength'. Use it in the error message. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: nand: pxa3xx: Remove unused macroEzequiel Garcia1-1/+0
This macro is not used so it's safe to remove it. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: bcm47xxpart: allow enabling on ARCH_BCM_5301XRafał Miłecki2-2/+2
Home routers based on SoCs like BCM53010 (AKA BCM4708) use flashes which can be nicely partitioned with bcm47xxpart. Header bcm47xx_nvram.h is not available on bcm53xx, so don't include it. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: bcm47xxpart: avoid overflowing when registering trxRafał Miłecki1-0/+5
Our code parsing "trx" header registers few partitions at once (in one loop iteration). Add extra check in that place. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: bcm47xxpart: fix off by one in partitions limitRafał Miłecki1-2/+2
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: allow CONFIG_MTD_PHYSMAP_OF also for CONFIG_MTD_RAMPhilippe De Muyter1-4/+4
Up to now mtd-ram devices described in device trees were only accessible if mtd-flash or mtd-rom were also configured at linux configuration time, because MTD_PHYSMAP_OF was only available if (MTD_CFI || MTD_JEDECPROBE || MTD_ROM). Allow MTD_PHYSMAP_OF selection also when only MTD_RAM is set. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: m25p80: add Macronix mx66l1g55g 1Gbit SPI flashBrian Norris1-0/+1
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2014-03-11mtd: nand: Add a devicetree binding for ECC strength and ECC step sizeEzequiel Garcia1-0/+14
Some flashes can only be properly accessed when the ECC mode is specified, so a way to describe such mode is required. Together, the ECC strength and step size define the correction capability, so that we say we will correct "{strength} bit errors per {size} bytes". The interpretation of these parameters is implementation-defined, but they often have ramifications on the formation, interpretation, and placement of correction metadata on the flash. Not all implementations must support all possible combinations. Implementations are encouraged to further define the value(s) they support. Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11of_mtd: Add helpers to get ECC strength and ECC step sizeEzequiel Garcia2-0/+46
This commit adds simple helpers to obtain the devicetree properties that specify the ECC strength and ECC step size to use on a given NAND controller. Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11mtd: Add a retlen parameter to _get_{fact,user}_prot_infoChristian Riesch7-64/+57
Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11jffs2: Fix crash due to truncation of csizeAjesh Kunhipurayil Vijayan1-1/+1
mounting JFFS2 partition sometimes crashes with this call trace: [ 1322.240000] Kernel bug detected[#1]: [ 1322.244000] Cpu 2 [ 1322.244000] $ 0 : 0000000000000000 0000000000000018 000000003ff00070 0000000000000001 [ 1322.252000] $ 4 : 0000000000000000 c0000000f3980150 0000000000000000 0000000000010000 [ 1322.260000] $ 8 : ffffffffc09cd5f8 0000000000000001 0000000000000088 c0000000ed300de8 [ 1322.268000] $12 : e5e19d9c5f613a45 ffffffffc046d464 0000000000000000 66227ba5ea67b74e [ 1322.276000] $16 : c0000000f1769c00 c0000000ed1e0200 c0000000f3980150 0000000000000000 [ 1322.284000] $20 : c0000000f3a80000 00000000fffffffc c0000000ed2cfbd8 c0000000f39818f0 [ 1322.292000] $24 : 0000000000000004 0000000000000000 [ 1322.300000] $28 : c0000000ed2c0000 c0000000ed2cfab8 0000000000010000 ffffffffc039c0b0 [ 1322.308000] Hi : 000000000000023c [ 1322.312000] Lo : 000000000003f802 [ 1322.316000] epc : ffffffffc039a9f8 check_tn_node+0x88/0x3b0 [ 1322.320000] Not tainted [ 1322.324000] ra : ffffffffc039c0b0 jffs2_do_read_inode_internal+0x1250/0x1e48 [ 1322.332000] Status: 5400f8e3 KX SX UX KERNEL EXL IE [ 1322.336000] Cause : 00800034 [ 1322.340000] PrId : 000c1004 (Netlogic XLP) [ 1322.344000] Modules linked in: [ 1322.348000] Process jffs2_gcd_mtd7 (pid: 264, threadinfo=c0000000ed2c0000, task=c0000000f0e68dd8, tls=0000000000000000) [ 1322.356000] Stack : c0000000f1769e30 c0000000ed010780 c0000000ed010780 c0000000ed300000 c0000000f1769c00 c0000000f3980150 c0000000f3a80000 00000000fffffffc c0000000ed2cfbd8 ffffffffc039c0b0 ffffffffc09c6340 0000000000001000 0000000000000dec ffffffffc016c9d8 c0000000f39805a0 c0000000f3980180 0000008600000000 0000000000000000 0000000000000000 0000000000000000 0001000000000dec c0000000f1769d98 c0000000ed2cfb18 0000000000010000 0000000000010000 0000000000000044 c0000000f3a80000 c0000000f1769c00 c0000000f3d207a8 c0000000f1769d98 c0000000f1769de0 ffffffffc076f9c0 0000000000000009 0000000000000000 0000000000000000 ffffffffc039cf90 0000000000000017 ffffffffc013fbdc 0000000000000001 000000010003e61c ... [ 1322.424000] Call Trace: [ 1322.428000] [<ffffffffc039a9f8>] check_tn_node+0x88/0x3b0 [ 1322.432000] [<ffffffffc039c0b0>] jffs2_do_read_inode_internal+0x1250/0x1e48 [ 1322.440000] [<ffffffffc039cf90>] jffs2_do_crccheck_inode+0x70/0xd0 [ 1322.448000] [<ffffffffc03a1b80>] jffs2_garbage_collect_pass+0x160/0x870 [ 1322.452000] [<ffffffffc03a392c>] jffs2_garbage_collect_thread+0xdc/0x1f0 [ 1322.460000] [<ffffffffc01541c8>] kthread+0xb8/0xc0 [ 1322.464000] [<ffffffffc0106d18>] kernel_thread_helper+0x10/0x18 [ 1322.472000] [ 1322.472000] Code: 67bd0050 94a4002c 2c830001 <00038036> de050218 2403fffc 0080a82d 00431824 24630044 [ 1322.480000] ---[ end trace b052bb90e97dfbf5 ]--- The variable csize in structure jffs2_tmp_dnode_info is of type uint16_t, but it is used to hold the compressed data length(csize) which is declared as uint32_t. So, when the value of csize exceeds 16bits, it gets truncated when assigned to tn->csize. This is causing a kernel BUG. Changing the definition of csize in jffs2_tmp_dnode_info to uint32_t fixes the issue. Signed-off-by: Ajesh Kunhipurayil Vijayan <ajesh@broadcom.com> Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-11jffs2: Fix segmentation fault found in stress testKamlakant Patel1-2/+2
Creating a large file on a JFFS2 partition sometimes crashes with this call trace: [ 306.476000] CPU 13 Unable to handle kernel paging request at virtual address c0000000dfff8002, epc == ffffffffc03a80a8, ra == ffffffffc03a8044 [ 306.488000] Oops[#1]: [ 306.488000] Cpu 13 [ 306.492000] $ 0 : 0000000000000000 0000000000000000 0000000000008008 0000000000008007 [ 306.500000] $ 4 : c0000000dfff8002 000000000000009f c0000000e0007cde c0000000ee95fa58 [ 306.508000] $ 8 : 0000000000000001 0000000000008008 0000000000010000 ffffffffffff8002 [ 306.516000] $12 : 0000000000007fa9 000000000000ff0e 000000000000ff0f 80e55930aebb92bb [ 306.524000] $16 : c0000000e0000000 c0000000ee95fa5c c0000000efc80000 ffffffffc09edd70 [ 306.532000] $20 : ffffffffc2b60000 c0000000ee95fa58 0000000000000000 c0000000efc80000 [ 306.540000] $24 : 0000000000000000 0000000000000004 [ 306.548000] $28 : c0000000ee950000 c0000000ee95f738 0000000000000000 ffffffffc03a8044 [ 306.556000] Hi : 00000000000574a5 [ 306.560000] Lo : 6193b7a7e903d8c9 [ 306.564000] epc : ffffffffc03a80a8 jffs2_rtime_compress+0x98/0x198 [ 306.568000] Tainted: G W [ 306.572000] ra : ffffffffc03a8044 jffs2_rtime_compress+0x34/0x198 [ 306.580000] Status: 5000f8e3 KX SX UX KERNEL EXL IE [ 306.584000] Cause : 00800008 [ 306.588000] BadVA : c0000000dfff8002 [ 306.592000] PrId : 000c1100 (Netlogic XLP) [ 306.596000] Modules linked in: [ 306.596000] Process dd (pid: 170, threadinfo=c0000000ee950000, task=c0000000ee6e0858, tls=0000000000c47490) [ 306.608000] Stack : 7c547f377ddc7ee4 7ffc7f967f5d7fae 7f617f507fc37ff4 7e7d7f817f487f5f 7d8e7fec7ee87eb3 7e977ff27eec7f9e 7d677ec67f917f67 7f3d7e457f017ed7 7fd37f517f867eb2 7fed7fd17ca57e1d 7e5f7fe87f257f77 7fd77f0d7ede7fdb 7fba7fef7e197f99 7fde7fe07ee37eb5 7f5c7f8c7fc67f65 7f457fb87f847e93 7f737f3e7d137cd9 7f8e7e9c7fc47d25 7dbb7fac7fb67e52 7ff17f627da97f64 7f6b7df77ffa7ec5 80057ef17f357fb3 7f767fa27dfc7fd5 7fe37e8e7fd07e53 7e227fcf7efb7fa1 7f547e787fa87fcc 7fcb7fc57f5a7ffb 7fc07f6c7ea97e80 7e2d7ed17e587ee0 7fb17f9d7feb7f31 7f607e797e887faa 7f757fdd7c607ff3 7e877e657ef37fbd 7ec17fd67fe67ff7 7ff67f797ff87dc4 7eef7f3a7c337fa6 7fe57fc97ed87f4b 7ebe7f097f0b8003 7fe97e2a7d997cba 7f587f987f3c7fa9 ... [ 306.676000] Call Trace: [ 306.680000] [<ffffffffc03a80a8>] jffs2_rtime_compress+0x98/0x198 [ 306.684000] [<ffffffffc0394f10>] jffs2_selected_compress+0x110/0x230 [ 306.692000] [<ffffffffc039508c>] jffs2_compress+0x5c/0x388 [ 306.696000] [<ffffffffc039dc58>] jffs2_write_inode_range+0xd8/0x388 [ 306.704000] [<ffffffffc03971bc>] jffs2_write_end+0x16c/0x2d0 [ 306.708000] [<ffffffffc01d3d90>] generic_file_buffered_write+0xf8/0x2b8 [ 306.716000] [<ffffffffc01d4e7c>] __generic_file_aio_write+0x1ac/0x350 [ 306.720000] [<ffffffffc01d50a0>] generic_file_aio_write+0x80/0x168 [ 306.728000] [<ffffffffc021f7dc>] do_sync_write+0x94/0xf8 [ 306.732000] [<ffffffffc021ff6c>] vfs_write+0xa4/0x1a0 [ 306.736000] [<ffffffffc02202e8>] SyS_write+0x50/0x90 [ 306.744000] [<ffffffffc0116cc0>] handle_sys+0x180/0x1a0 [ 306.748000] [ 306.748000] Code: 020b202d 0205282d 90a50000 <90840000> 14a40038 00000000 0060602d 0000282d 016c5823 [ 306.760000] ---[ end trace 79dd088435be02d0 ]--- Segmentation fault This crash is caused because the 'positions' is declared as an array of signed short. The value of position is in the range 0..65535, and will be converted to a negative number when the position is greater than 32767 and causes a corruption and crash. Changing the definition to 'unsigned short' fixes this issue Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-28 12:54:30 +0300