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2022-06-13DRM: use CONFIG_DRM_STARFIVE_MIPI_DSI change display channelVF_SDK_510_V1.1.2changhuang.liang3-2/+26
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: fixed mipi screen color errorchanghuang.liang2-2/+17
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add XR24 format supportchanghuang.liang2-0/+2
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drm: buffer flush l2cachechanghuang.liang3-1/+4
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13Update Kconfigchanghuang.liang1-1/+1
2022-06-13dts/starfive: fixed v4l2 conflictchanghuang.liang2-3/+4
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13v4l2: change file authority to 0644changhuang.liang2-0/+0
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13V4L2: fix v4l2 coding stylechanghuang.liang20-166/+154
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13V4l2: add v4l2 drivers support!changhuang.liang33-3951/+17884
dts/starfive: add v4l2 configure! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drivers/reset: add isp reset support!changhuang.liang5-1/+107
drivers/reset: modify reset-starfive-jh7100.c dts/satrfive: add isp resst support! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drivers/clk: add isp clk support!changhuang.liang5-0/+229
dts/starfive: add isp clk configure! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent1-1/+1
The errata_cip_453.o should be built only when the Kconfig CONFIG_ERRATA_SIFIVE_CIP_453 is enabled. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Vincent <vincent.chen@sifive.com> Fixes: 0e0d4992517f ("riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y") Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: sifive: Apply errata "cip-1200" patchVincent Chen4-2/+40
For certain SiFive CPUs, "sfence.vma addr" cannot exactly flush addr from TLB in the particular cases. The details could be found here: https://sifive.cdn.prismic.io/sifive/167a1a56-03f4-4615-a79e-b2a86153148f_FU740_errata_20210205.pdf In order to ensure the functionality, this patch uses the Alternative scheme to replace all "sfence.vma addr" with "sfence.vma" at runtime. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: sifive: Apply errata "cip-453" patchVincent Chen6-3/+94
Add sign extension to the $badaddr before addressing the instruction page fault and instruction access fault to workaround the issue "cip-453". To avoid affecting the existing code sequence, this patch will creates two trampolines to add sign extension to the $badaddr. By the "alternative" mechanism, these two trampolines will replace the original exception handler of instruction page fault and instruction access fault in the excp_vect_table. In this case, only the specific SiFive CPU core jumps to the do_page_fault and do_trap_insn_fault through these two trampolines. Other CPUs are not affected. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: sifive: Add SiFive alternative portsVincent Chen7-0/+89
Add required ports of the Alternative scheme for SiFive. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: Introduce alternative mechanism to apply errata solutionVincent Chen14-0/+301
Introduce the "alternative" mechanism from ARM64 and x86 to apply the CPU vendors' errata solution at runtime. The main purpose of this patch is to provide a framework. Therefore, the implementation is quite basic for now so that some scenarios could not use this schemei, such as patching code to a module, relocating the patching code and heterogeneous CPU topology. Users could use the macro ALTERNATIVE to apply an errata to the existing code flow. In the macro ALTERNATIVE, users need to specify the manufacturer information(vendorid, archid, and impid) for this errata. Therefore, kernel will know this errata is suitable for which CPU core. During the booting procedure, kernel will select the errata required by the CPU core and then patch it. It means that the kernel only applies the errata to the specified CPU core. In this case, the vendor's errata does not affect each other at runtime. The above patching procedure only occurs during the booting phase, so we only take the overhead of the "alternative" mechanism once. This "alternative" mechanism is enabled by default to ensure that all required errata will be applied. However, users can disable this feature by the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE". Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: Add 3 SBI wrapper functions to get cpu manufacturer informationVincent Chen2-0/+18
Add 3 wrapper functions to get vendor id, architecture id and implement id from M-mode Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13drm: fixed conflict errorchanghuang.liang1-6/+0
2022-06-13dts/starfive: drm config default hdmichanghuang.liang1-1/+1
2022-06-13DRM: fixed drm register before i2c controllerchanghuang.liang10-211/+191
DRM: fixed hdmi color problem Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: open dsi transferchanghuang.liang1-1/+1
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: fixed nv21 format error!changhuang.liang1-3/+3
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add clk and reset apichanghuang.liang17-413/+365
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: delete printk debug logchanghuang.liang9-89/+7
m31: modify name "rx" to "tx" Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13fixed mipi screen errorchanghuang.liang4-2117/+7
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drm: fixed coding stylechanghuang.liang17-2591/+2557
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add drm driver supportchanghuang.liang29-146/+8427
dts/starfive: add drm driver configure Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13dts:starfive:Release Audio devices nodesxingyu.wu2-11/+4
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13sound:soc:pwmdac:modify the codexingyu.wu1-1/+3
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100 in DMAxingyu.wu1-1/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13sound:pwmdac:Modify clock and reset initialization and fixed reset conflict ↵xingyu.wu3-47/+129
with pwmadac and i2s Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13PWMDAC: Deleted invalid code for pwmdac drivercurry.zhang1-1/+0
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-06-13Audio: Add the new sampling rate for pwmdac drivercurry.zhang3-1/+68
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com> Author: curry.zhang <curry.zhang@starfivetech.com>
2022-06-13AUDIO:WM8960: Fixed there had the print error for WM8960 when playing music ↵curry.zhang1-0/+7
with PWMDAC Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-06-13Support AC108 daughter board for 3 dev-boardsWalkerChenL3-1/+9
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-13riscv: dts: starfive: Support AC108 daughter boardWalkerChenL7-3/+53
Add device tree support for AC108 daughter board, using the clock generated by Clock Tree. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-13dt-bindings: reset: Add starfive,jh7100-audrst bindingsEmil Renner Berthing1-0/+38
Add bindings for the audio reset controller on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13dt-bindings: clock: Add starfive,jh7100-audclk bindingsEmil Renner Berthing1-0/+57
Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13sound:dwc:Modify i2s code and remove 'reset_control_bulk'xingyu.wu2-42/+13
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-06-13RISC-V: Add StarFive JH7100 audio reset nodeEmil Renner Berthing1-6/+6
Add device tree node for the audio resets on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100 in audio resetxingyu.wu1-1/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13reset: starfive: Add JH7100 audio reset driverEmil Renner Berthing6-15/+112
The audio resets are almost identical to the system resets, there are just fewer of them. So factor out and export a generic probe function, so most of the reset controller implementation can be shared. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13dt-bindings: reset: Add StarFive JH7100 audio reset definitionsEmil Renner Berthing1-0/+31
Add all resets for the StarFive JH7100 audio reset controller. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13RISC-V: Add StarFive JH7100 audio clock nodeEmil Renner Berthing1-10/+10
Add device tree node for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100 in audio clkxingyu.wu1-1/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13clk: starfive: Add JH7100 audio clock driverEmil Renner Berthing3-4/+12
Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13clk: starfive: jh7100: Handle audio_div clock properlyEmil Renner Berthing1-1/+53
It turns out the audio_div clock is a fractional divider where the lowest byte of the ctrl register is the integer part of the divider and the 2nd byte is the number of 100th added to the divider. The children of this clock is used by the audio peripherals for their sample rate clock, so round to the closest possible rate rather than always rounding down like regular dividers. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13dma/dw-axi-dmac/dw-axi-dmac-platform.c: fix building errojianlong.huang5-88/+28
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-06-13PWMDAC: Deleted invalid code for pwmdac drivercurry.zhang1-1/+28
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-06-13dmaengine: dw-axi-dmac-starfive: Remove calls specific to ARM64 ACPIGeert Uytterhoeven1-18/+2
iort_dma_setup() is being removed by commit db59e1b6e49201be ("ACPI: arm64: Move DMA setup operations out of IORT") in iommu/next: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_async_ do_memcpy’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:152:2: error: implicit decl aration of function ‘iort_dma_setup’ [-Werror=implicit-function-declaration] 152 | iort_dma_setup(dma_dev, &dma_addr, &dma_size); | ^~~~~~~~~~~~~~ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:153:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 153 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_memcpy_raw’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:223:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 223 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ iort_dma_setup() and iort_iommu_configure_id() are part of the ARM64 ACPI implementation. As CONFIG_ACPI_IORT cannot be enabled on RISC-V, they were dummies anyway, so these calls can just be removed. [Emil: remove unused local variables too] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- Boot-tested, but the affected code paths were not exercised.
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 22:20:06 +0300