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2022-10-27riscv: deconfig: Enable pm advanced debugmason.huo1-0/+2
Enable pm advanced debug, so that we can check runtime PM status. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-10-27sound:starfive:pwmdac:Add runtime pm operationXingyu Wu1-28/+91
Add runtime pm operation in PWMDAC driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-10-27rtc:starfive: add pm ops for rtcziv.xu1-0/+1
add pm ops for rtc Signed-off-by: ziv.xu <ziv.xu@starfive.com>
2022-10-27i2c: designware: Descend startup priorityHal Feng1-1/+1
So i2c will be initialized after uart. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-10-27i2c: designware: Uncomment and recover the pm functionsHal Feng1-4/+1
Uncomment the system pm and runtime pm ops functions. Restore the Synopsys DesignWare i2c driver to the original version. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-10-27CR_2345_Audio_DevicePM_walker.chenWalker Chen1-2/+2
Fix the bug that pdm function name spell error. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-10-27CR_2345_Audio_DevicePM_walker.chenWalker Chen2-8/+18
Disable clock when audio driver is loaded. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-10-27driver:gpu: add gpu runtime pmshanlong.li7-16/+91
fix up system pm error and add runtime pm Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-10-27sound:starfive:Add hibernation in I2SXingyu Wu1-68/+29
Add hibernation in starfive I2S driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-10-27rtc-starfive.c:add system pm for rtcziv.xu1-1/+4
add system pm for rtc Signed-off-by: ziv.xu <ziv.xu@starfive.com>
2022-10-27drive:mailbox:add pm opsys1-1/+40
add runtime pm and system pm ops Signed-off-by: ys <eason.xiong@starfivetech.com>
2022-10-27sec:starfive:add sec runtime PM opsWilliam Qiu3-0/+29
add sec runtime PM ops. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2022-10-27SDIO:starfive:modify SDIO/EMMC runtime PM callback functionWilliam Qiu1-3/+6
modify SDIO/EMMC runtime PM callback function. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2022-10-27canfd:ipms:modify runtime PM callback funcitonWilliam Qiu1-2/+6
modify runtime PM callback function. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2022-10-27clk:starfive:isp:Add runtime and system pm controlXingyu Wu3-43/+126
Add runtime and system pm in isp clock tree driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-10-27pwm: starfive: Remove macro UNIVERSAL_DEV_PM_OPSHal Feng1-4/+8
Because it causes error when system pm. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-10-27drivers: temp sensor: reset execute permissionsziv.xu1-0/+1
reset execute permissions for FILE: drivers/hwmon/sfctemp.c Signed-off-by: ziv.xu <ziv.xu@starfive.com>
2022-10-27add devcie pm for temp sensorziv.xu1-1/+42
add device pm for temp sensor Signed-off-by: ziv.xu <ziv.xu@starfive.com>
2022-10-27add device pm for trngZiv.Xu1-2/+54
add device pm for trng Signed-off-by: Ziv.Xu <Ziv.Xu@starfivetech.com>
2022-10-27add device pm for spiZiv.Xu1-13/+25
add device pm for spi Signed-off-by: Ziv.Xu <Ziv.Xu@starfivetech.com>
2022-10-27SDIO:starfive:add SDIO/EMMC runtime pm opsWilliam Qiu1-6/+68
add SDIO/EMMC runtime pm ops. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2022-10-27canfd:ipms:add canfd runtime PM opsWilliam Qiu1-0/+50
add canfd runtime PM ops. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2022-10-27sound:starfive:spdif:Add hibernation operationXingyu Wu3-19/+86
Add runtime pm and system pm in spdif driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-10-27pwm: starfive: Add pm handling (system/runtime pm ops)Hal Feng1-23/+66
Add system/runtime pm ops functions and enable runtime pm. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-10-27pinctrl:starfive: Add system pm interfaceJianlong Huang1-0/+1
Support system pm fuction when suspend and resume. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-10-27CR_2345_Audio_DevicePM_walker.chenWalker Chen3-34/+228
Implement Runtime PM and System PM for PDM and TDM module. Signed-off-by: Walker Chen <walker.chen@linux.starfivetech.com>
2022-10-27add system pm for watchdogZiv.Xu1-19/+23
add system pm for watchdog Signed-off-by: Ziv.Xu <Ziv.Xu@starfivetech.com>
2022-10-27add runtime pm for watchdogZiv.Xu1-3/+44
add runtime pm for watchdog Signed-off-by: Ziv.Xu <Ziv.Xu@starfivetech.com>
2022-10-27usb: cdns: add pm and runtume pm opsminda.chen1-0/+46
add starfive pm supend/resume and runtime pm runtime suspend and resume ops Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-10-27drivers: pci: Support system pm no irq ops.Kevin.xie1-0/+37
Because of the limitation of hardware design, only enable/disable clk here. Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
2022-10-27drivers: pci: Support runtime pm & release when found empty slot in probe.Kevin.xie4-11/+95
Used PLDA link up/down status in probe to indicate the slot situations. Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
2022-10-27media: starfive: Remove hardware operations in vin initchanghuang.liang1-3/+0
Remove hardware operations in vin init, hardware operation need turn on power domain. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27dts: starfive: VIN delete noc bus clockchanghuang.liang1-4/+3
VIN delete noc bus clock. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27media: starfive: Delete isp noc bus clockchanghuang.liang2-8/+0
Delete operate isp noc bus clock in vin module. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27media: starfive: Vin module get reset use sharechanghuang.liang1-1/+1
Vin module get reset use share due to the same reset single with isp clock module. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27v4l2: Fixed vin line stream_out not change except WR.changhuang.liang1-9/+11
Fixed vin line stream_out not change except WR. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27v4l2: VIN driver use pmchanghuang.liang5-78/+153
VIN driver use pm save power, delete turn on pmu multiple times and modify isp clk and reset after turn on pmu. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27ov4689: Correct some codechanghuang.liang1-32/+10
Correct some code. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27sc2235: Delete the control direct control registerchanghuang.liang1-71/+15
Delete the control direct control register and correct some code. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27sc2235: Use runtime/system pmchanghuang.liang1-42/+62
Use runtime/system pm save power. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27imx219: Separate set stream and runtime PMchanghuang.liang1-47/+14
Separate set stream and runtime PM, use runtime PM. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27ov4689: Use runtime PMchanghuang.liang1-84/+66
Switch to using runtime PM for power management. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27ov4689: delete read chip id in set powerchanghuang.liang1-19/+0
delete read chip id in set power on. Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-10-27cpuidle: riscv-sbi: Fix code to allow a genpd governor to be usedUlf Hansson1-2/+2
The intent is to use a genpd governor when there are some states that needs to be managed. Although, the current code ends up to never assign a governor, let's fix this. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-10-27RISC-V: Avoid using per cpu array for ordered bootingAtish Patra4-19/+61
Currently both order booting and spinwait approach uses a per cpu array to update stack & task pointer. This approach will not work for the following cases. 1. If NR_CPUs are configured to be less than highest hart id. 2. A platform has sparse hartid. This issue can be fixed for ordered booting as the booting cpu brings up one cpu at a time using SBI HSM extension which has opaque parameter that is unused until now. Introduce a common secondary boot data structure that can store the stack and task pointer. Secondary harts will use this data while booting up to setup the sp & tp. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> From 9a2451f1866344d38b4a1dc20396e3a03954fcd7 Resolved merge conflict. Signed-off-by: <jeeheng.sia@starfivetech.com> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-10-27RISC-V: Use SBI SRST extension when availableAnup Patel2-0/+51
The SBI SRST extension provides a standard way to poweroff and reboot the system irrespective to whether Linux RISC-V S-mode is running natively (HS-mode) or inside Guest/VM (VS-mode). The SBI SRST extension is available in the SBI v0.3 specification. (Refer, https://github.com/riscv/riscv-sbi-doc/releases/tag/v0.3.0-rc1) This patch extends Linux RISC-V SBI implementation to detect and use SBI SRST extension. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-10-27cpuidle: riscv-sbi: Correct the compatible stringmason.huo1-1/+1
The riscv-sbi driver compatible string should not changed to starfive since it's a common driver for riscv. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-10-27riscv: dts: Remove unsupport idle statesmason.huo1-46/+14
The JH7110 soc only support WFI cpu idle state, remove the unsupport states. Add a long WFI for entering the cpu_suspend(). Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-10-26clk:starfive:Count PLL1 rateXingyu Wu2-7/+1
Count PLL1 rate through reading syscon registers. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-10-26clk:starfive:Change PLL0 rate to 1.5GHzXingyu Wu2-0/+36
Change PLL0 rate to 1.5GHz and change cpu_core divider. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 16:06:32 +0300