| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-04-13 | clk:starfive: Add JH7110 clock tree driver for kernel 5.15 | xingyu.wu | 12 | -13/+2212 | |
| Add clock driver about sys, stg and aon clock for JH7110. Clock references refer to include/dt-bindings/clock/starfive-jh7110-clkgen.h Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-13 | Merge branch 'CR_792_PINCTRL_jianlong' into 'jh7110_fpga_dev_5.15' | andy.hu | 11 | -2/+3586 | |
| add jh7110 pinctrl dts and driver See merge request sdk/sft-riscvpi-linux-5.10!4 | |||||
| 2022-04-12 | enable sdio pinctrcl | jianlong.huang | 1 | -0/+12 | |
| Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com> | |||||
| 2022-04-07 | enable pinctrl and modify gpio irq init | jianlonghuang | 4 | -6/+60 | |
| Signed-off-by: jianlonghuang <jianlong.huang@starfivetech.com> | |||||
| 2022-04-07 | [pinctrl]Synchronize vic7100&jh7110 pinctrl subsystem | “jenny.zhang” | 6 | -101/+56 | |
| 2022-04-07 | [pinctrl] Update parse gpio dts node | “jenny.zhang” | 1 | -8/+1 | |
| 2022-04-07 | [pinctrl]Update gpio control code | “jenny.zhang” | 3 | -192/+162 | |
| 2022-04-07 | [pinctrl] disable jh7110 pinctrl | “jenny.zhang” | 1 | -1/+1 | |
| 2022-04-07 | [pinctrl] 1.Update jh7110 pinctrl dts; 2.Adjust pinctrl coding style; | “jenny.zhang” | 4 | -701/+748 | |
| 2022-04-07 | [pinctrl] add jh7110 pinctrl dts and driver | “jenny.zhang” | 9 | -0/+3553 | |
| 2022-03-23 | Merge branch 'CR_730_RTC_samin.guo' into 'jh7110_dev_5.15' | andy.hu | 1 | -30/+45 | |
| rtc: starfive: Get the interrupt status using Completion. See merge request sdk/sft-riscvpi-linux-5.10!3 | |||||
| 2022-03-16 | rtc: starfive: Get the interrupt status using Completion. | samin | 1 | -30/+45 | |
| starfiv rtc needs to get interrupt status when setting rtc clock and configuring hardware calibration. Use completion to identify states in interrupt handlers. In addition, when clearing the interrupt, you need to pull to determine whether to clear the state, otherwise the clearing will be unsuccessful. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-03-15 | Merge branch 'CR_722_DRM_keith.zhao' into 'jh7110_dev_5.15' | andy.hu | 1 | -1/+1 | |
| riscv:driver:drm:DC8200 See merge request sdk/sft-riscvpi-linux-5.10!2 | |||||
| 2022-03-14 | riscv:driver:drm:DC8200 | keith.zhao | 1 | -1/+1 | |
| fix build error caused by vs-drm.h modify SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note Signed-off-by:keith.zhao <keith.zhao@statfivetech.com> | |||||
| 2022-01-14 | riscv::starfive:driver:dc8200 | keith.zhao | 1 | -0/+50 | |
| add head file vs-drm.h Signed-off-by:keith.zhao<keith.zhao@statfivetech.com> | |||||
| 2022-01-14 | riscv:uboot:starfive:dc8200 | keith.zhao | 50 | -2/+16420 | |
| update drdc8200iver kenerl version from 5.10 to 5.13 Signed-off-by:keith.zhao<keith.zhao@statfivetech.com> | |||||
| 2022-01-14 | soc:starfive: add jh7110 pmu driver. | samin | 4 | -0/+442 | |
| The JH7110 PMU can dynamically switch on or off power domians and set the power-on and power-off sequence. API Instructions refer to include/soc/starfive/jh7110_pmu.h Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-01-14 | dt-bingings:pmu:add jh7110 pmu dt-bingings. | samin | 1 | -0/+8 | |
| Add jh7110 pmu support. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-01-13 | 1.add mailbox driver; 2.add mailbox test driver. | shanlong.li | 6 | -1/+786 | |
| 2022-01-13 | add patches for libkcapi tool | Huan.Feng | 15 | -51/+1319 | |
| 2022-01-12 | v4l2: add mipi pipeline suppport and ov13850 sensor | changhuang.liang | 9 | -57/+2238 | |
| 2022-01-06 | [v4l2][update kernel5.15] | david.li | 5 | -36/+33 | |
| 2022-01-05 | reset: starfive-jh7110: Add isp/vout reset support. | samin | 1 | -2/+30 | |
| Add isp/vout reset support for jh7110. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-01-05 | reset: starfive-jh7110: use platform_ioremap_iomem_byname. | samin | 1 | -3/+17 | |
| The reset module is scattered in several domains, and each address segment may be located in the module device management. Using devm_platform_get_and_ioremap_resource->devm_ioremap_resource will cause the address of this segment to be occupied by the reset driver, and other modules cannot be used, so use ioremap that can be mapped multiple times instead. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-01-05 | dt-bingings:reset:jh7110: Add isp/vout reg reset node. | samin | 2 | -5/+9 | |
| Add isp/vout reg reset node for jh7110. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-01-05 | dt-bingings:reset:jh7110: Add isp/vout domain reset define. | samin | 1 | -1/+31 | |
| isp/vout domain are independent of other CRGS. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-01-05 | [v4l2] [add vin path] | david.li | 7 | -161/+108 | |
| 2021-12-23 | open pcie | david.li | 1 | -1/+0 | |
| 2021-12-22 | dt-bingings:reset: Add reset node for vdec&&jpeg. | samin | 1 | -0/+16 | |
| Add reset bindings for the vdec&jpeg. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2021-12-22 | dt-bingings:reset: Add Starfive JH7110 reset bindings | samin | 2 | -2/+47 | |
| Add bindings for the reset controller on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2021-12-22 | reset: starfive-jh7110: Add StarFive JH7110 reset driver | samin | 6 | -0/+457 | |
| Add a driver for the StarFive JH7110 reset controller. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2021-12-20 | [pwm] Add jh7110 pwm driver code | “jenny.zhang” | 4 | -0/+337 | |
| 2021-12-16 | [can] Add jh7110 can driver code | “jenny.zhang” | 4 | -0/+1527 | |
| 2021-12-16 | [trng] Add jh7110 trng driver code | “jenny.zhang” | 5 | -0/+571 | |
| 2021-12-16 | [alsa] Add jh7110 audio module driver code | “jenny.zhang” | 25 | -3/+8061 | |
| 2021-12-15 | v4l2 add dvp modify | david.li | 1 | -2/+2 | |
| 2021-12-14 | [add v4l2 driver && close pcie] | david.li | 33 | -1/+17084 | |
| 2021-12-13 | modified dts file for jh7110 i2c | Huan.Feng | 1 | -1/+17 | |
| 2021-12-10 | modified gpio driver for jh7110 | Huan.Feng | 1 | -3/+7 | |
| 2021-12-10 | modified i2c driver for jh7110 | Huan.Feng | 2 | -2/+30 | |
| 2021-12-10 | remove IMG-rogue and null-disp and drm_legacy | vincent.zhang | 1 | -2/+1 | |
| Signed-off-by: vincent.zhang <vincent.zhang@starfivetech.com> | |||||
| 2021-12-10 | add IMG-rogue, DRM, GEM & KMS, enable DRM legacy for default config | vincent.zhang | 1 | -3/+5 | |
| 2021-12-10 | change the IRQ number of GPU | vincent.zhang | 1 | -1/+1 | |
| Signed-off-by: vincent.zhang <vincent.zhang@starfivetech.com> | |||||
| 2021-12-03 | Merge branch 'jh7110_dev_5.15' of ↵ | Huan.Feng | 1 | -1/+7 | |
| http://192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15 | |||||
| 2021-12-03 | modify jh7110 gpio driver irq register function | Huan.Feng | 1 | -2/+52 | |
| 2021-12-03 | Merge branch 'jh7110_dev_5.15' of ↵ | ke.zhu | 1 | -96/+48 | |
| http://192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15 | |||||
| 2021-12-03 | modify jh7110 gpio driver | Huan.Feng | 1 | -96/+48 | |
| 2021-12-03 | PLIC cannot EOI masked interrupts，so Re-enable the interrupt before ↵ | ke.zhu | 1 | -1/+7 | |
| completion if it has been masked during the handling and remask it afterwards. | |||||
| 2021-12-01 | Kconfig/dw-axi-dmac-starfive: selected by SOC_STARFIVE | samin | 1 | -1/+1 | |
| Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2021-11-26 | clocksource: add starfive hw-timer driver | Samin Guo | 5 | -0/+521 | |
| This driver applies to JH7100|JH7110 Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |