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2022-04-24net:stmmac: remove DWMAC_CORE_5_20 hw configyanhong.wang1-18/+0
The version DWMAC_CORE_5_20 and DWMAC_CORE_5_10 would use the same configuration,so remove the DWMAC_CORE_5_20 configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-24Merge branch 'CR_881_DMA_curry.zhang' into 'jh7110_fpga_dev_5.15'andy.hu3-1/+23
[DMA] : Add standard system clock tree & reset API See merge request sdk/sft-riscvpi-linux-5.10!22
2022-04-24Merge branch 'CR_876_BoardTypeDef_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu3-24/+3
Cr 876 board type def xingyu.wu See merge request sdk/sft-riscvpi-linux-5.10!18
2022-04-24Merge branch 'CR_863_UART_yanhong.wang' into 'jh7110_fpga_dev_5.15'andy.hu2-11/+16
dt-bingings:uart:jh7110: add clks and reset signals to uarts See merge request sdk/sft-riscvpi-linux-5.10!21
2022-04-24[DMA] : Add standard system clock tree & reset APIcurry.zhang3-1/+23
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-04-24dt-bingings:uart:jh7110: add clks and reset signals to uartsyanhong.wang2-11/+16
Uart uses the clock and reset framework API. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-22Merge branch 'CR_834_VENC_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu2-10/+22
Cr 834 venc samin.guo See merge request sdk/sft-riscvpi-linux-5.10!20
2022-04-22dt-bingings:clk: remove venc_rootclk fixed clk define.samin1-6/+0
The clktree is ready. The Venc uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-22dt-bingings:venc:jh7110: Add CLK signals to Venc.samin1-4/+22
Venc uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-22Merge branch 'CR_835_JPU_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu2-11/+5
Cr 835 jpu samin.guo See merge request sdk/sft-riscvpi-linux-5.10!14
2022-04-22Merge branch 'CR_884_syscon_mason.huo' into 'jh7110_fpga_dev_5.15'andy.hu1-0/+15
riscv: dts: jh7110: Add syscon support See merge request sdk/sft-riscvpi-linux-5.10!19
2022-04-22riscv: dts: jh7110: Add syscon supportmason.huo1-0/+15
Add 'stg', 'sys', 'aon' system control register support, access these registers through syscon framework. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-21dt-bingings:clk: remove jpu_rootclk fixed clk define.samin1-6/+0
The clktree is ready. The JPU uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-21dt-bingings:jpu:jh7110: Add CLK signals to JPU.samin1-5/+5
Jpu uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-21Merge branch 'CR_866_SDIO_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu1-1/+4
dt-bingings:sd:update jh7110 sd dt-bingings See merge request sdk/sft-riscvpi-linux-5.10!17
2022-04-21Merge branch 'CR_867_eMMC_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu1-1/+5
dt-bingings:emmc:update jh7110 emmc dt-bingings See merge request sdk/sft-riscvpi-linux-5.10!16
2022-04-21Makefile: Add Board Type Definition with MODULExingyu.wu1-0/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-21arch:riscv:modify Kconfig.socsxingyu.wu2-24/+1
Kconfig.socs: remove the definitions like 'STARFIVE_BOARD_FPGA'. drivers:watchdog: change the definition. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-21Makefile: Add Board Type Definitionxingyu.wu1-0/+1
Add some definition about 'HWBOARD_FPGA', 'HWBOARD_EVB' or 'HWBOARD_VISIONFIVE' in kernel. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-20dt-bingings:emmc:update jh7110 emmc dt-bingingsClivia.Cai1-1/+5
Add clock and reset for sdio0 nodes in device tree Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-20dt-bingings:sd:update jh7110 sd dt-bingingsClivia.Cai1-1/+4
Add clock and reset for sdio1 nodes in device tree Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-19Merge branch 'CR_847_watchdog_xingyu.wu' into 'jh7110_fpga_dev_5.15'andy.hu9-568/+607
Cr 847 watchdog xingyu.wu See merge request sdk/sft-riscvpi-linux-5.10!9
2022-04-19driver:watchdog:Add config definition to different uses of board levelxingyu.wu2-20/+22
1. The watchdog driver can get different rate from clock by different board. 2. arch:riscv:Kconfig: Adjust the format. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-19driver:watchdog: Add clock & resetxingyu.wu2-19/+56
Add clock and reset in watchdog's driver and device tree. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-19clk:starfive: Adjust the formatxingyu.wu7-528/+528
Adjust and modify the clock driver's format Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-19Merge branch 'CR_786_CAN_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu5-992/+816
Cr 786 can clivia.cai See merge request sdk/sft-riscvpi-linux-5.10!8
2022-04-19dt-bingings:can:update jh7110 can dt-bingings.Clivia.Cai1-7/+35
Update jh7110 can/canfd dt-bindings configuration Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-19riscv:defconfig: enable CAN,IPMS_CANClivia.Cai1-1/+2
Enable can/canfd config in defconfig. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-19dt-bindings:net:can:ipms-can: add ipms-can.yaml referencesClivia.Cai1-0/+107
Add CAN/CANFD binding documentation for jh7110 SoC. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-19can:ipms_can: fix code styleClivia.Cai1-984/+670
Optimize the can driver code to conform to the upstream specification Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-19dt-bindings: Add vendor prefixClivia.Cai1-0/+2
Add vendor prefix for can device Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-19Merge branch 'CR_864_update_pinctrl_jianlong' into 'jh7110_fpga_dev_5.15'andy.hu1-730/+1202
update pinctrl marco to more lines See merge request sdk/sft-riscvpi-linux-5.10!12
2022-04-19update pinctrl marco to more linesjianlong.huang1-730/+1202
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-19Merge branch 'CR_870_Reset_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu3-55/+66
Cr 870 reset samin.guo See merge request sdk/sft-riscvpi-linux-5.10!11
2022-04-19Merge branch 'CR_833_VDEC_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu4-10/+11
CR 833 vdec samin.guo See merge request sdk/sft-riscvpi-linux-5.10!10
2022-04-19reset:starfive:jh7110: Fix wrong macro definition.samin2-6/+6
Fix wrong macro definition. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-19reset:starfive:jh7110: Macro definitions are rearranged in order.samin1-12/+9
Macro definitions are rearranged in order, for better coding style. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-19reset:starfive:jh7110: change how to obtain an assert addresssamin1-45/+59
Get assert addresses dynamically to reduce static array memory usage Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-18dt-bingings:clk: remove dec_rootclk fixed clk define.samin1-6/+0
The clktree is ready. The VDEC uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-18dt-bingings:vdec:jh7110: Add CLK signals to Vdecsamin1-4/+9
Vdec uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-15drivers:soc:starfive: support driver for starfive soc.samin2-0/+2
Add Kconfig/Makefile support for starfive soc. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-14Merge branch 'CR_783_dts_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu10-892/+1068
riscv: dts: starfive: Improve the structure of device tree See merge request sdk/sft-riscvpi-linux-5.10!5
2022-04-14riscv: dts: starfive: Improve the structure of device treeHal Feng10-892/+1068
Divide the old device tree into several files according to different layers. Make the device tree clearer and more readable. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-14Merge branch 'CR_792_PINCTRL_jianlong' into 'jh7110_fpga_dev_5.15'andy.hu4-2/+128
modify pinctrl about vin_dvp function sel See merge request sdk/sft-riscvpi-linux-5.10!7
2022-04-14modify vin pinctrl dtsjianlong.huang1-1/+1
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-13add dvp pinctrl dtsjianlong.huang1-0/+107
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-13modify pinctrl about vin_dvp function seljianlong.huang3-2/+21
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-13Merge branch 'CR_737_CLOCK_TREE_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu15-13/+2585
Cr 737 clock tree xingyu.wu See merge request sdk/sft-riscvpi-linux-5.10!6
2022-04-13arch:riscv:Kconfig: Add choice with SOC board typexingyu.wu6-24/+49
Add config about user can choose the board type about FPGA, EVB or Visionfive Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-13clk:starfive: Add vout clock tree driverxingyu.wu6-0/+348
Clock references refer to include/dt-bindings/clock/starfive-jh7110-vout.h Change the value about 'status' of clkvout node in dts file when want to use vout clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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